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adam.huang
Arm Trusted Firmware
Commits
0ed87212
Commit
0ed87212
authored
3 years ago
by
Varun Wadekar
Committed by
TrustedFirmware Code Review
3 years ago
Browse files
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Merge "feat(cpus): workaround for Cortex A78 AE erratum 1951502" into integration
parents
459b2445
8913047a
No related merge requests found
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3 changed files
docs/design/cpu-specific-build-macros.rst
+6
-0
docs/design/cpu-specific-build-macros.rst
lib/cpus/aarch64/cortex_a78_ae.S
+79
-10
lib/cpus/aarch64/cortex_a78_ae.S
lib/cpus/cpu-ops.mk
+9
-1
lib/cpus/cpu-ops.mk
with
94 additions
and
11 deletions
+94
-11
docs/design/cpu-specific-build-macros.rst
View file @
0ed87212
...
...
@@ -281,6 +281,12 @@ For Cortex-A78, the following errata build flags are defined :
- ``ERRATA_A78_1821534``: This applies errata 1821534 workaround to Cortex-A78
CPU. This needs to be enabled for revisions r0p0 and r1p0.
For Cortex-A78 AE, the following errata build flags are defined :
- ``ERRATA_A78_AE_1951502`` : This applies errata 1951502 workaround to Cortex-A78
AE CPU. This needs to be enabled for revisions r0p0 and r0p1. This erratum is
still open.
For Neoverse N1, the following errata build flags are defined :
- ``ERRATA_N1_1073348``: This applies errata 1073348 workaround to Neoverse-N1
...
...
This diff is collapsed.
Click to expand it.
lib/cpus/aarch64/cortex_a78_ae.S
View file @
0ed87212
/*
*
Copyright
(
c
)
2019
-
2020
,
ARM
Limited
.
All
rights
reserved
.
*
Copyright
(
c
)
2021
,
NVIDIA
Corporation
.
All
rights
reserved
.
*
*
SPDX
-
License
-
Identifier
:
BSD
-
3
-
Clause
*/
...
...
@@ -16,12 +17,73 @@
#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
#endif
/*
--------------------------------------------------
*
Errata
Workaround
for
A78
AE
Erratum
1951502
.
*
This
applies
to
revisions
r0p0
and
r0p1
of
A78
AE
.
*
Inputs
:
*
x0
:
variant
[
4
:
7
]
and
revision
[
0
:
3
]
of
current
cpu
.
*
Shall
clobber
:
x0
-
x17
*
--------------------------------------------------
*/
func
errata_a78_ae_1951502_wa
/
*
Compare
x0
against
revisions
r0p0
-
r0p1
*/
mov
x17
,
x30
bl
check_errata_1951502
cbz
x0
,
1
f
msr
S3_6_c15_c8_0
,
xzr
ldr
x0
,
=
0x10E3900002
msr
S3_6_c15_c8_2
,
x0
ldr
x0
,
=
0x10FFF00083
msr
S3_6_c15_c8_3
,
x0
ldr
x0
,
=
0x2001003FF
msr
S3_6_c15_c8_1
,
x0
mov
x0
,
#
1
msr
S3_6_c15_c8_0
,
x0
ldr
x0
,
=
0x10E3800082
msr
S3_6_c15_c8_2
,
x0
ldr
x0
,
=
0x10FFF00083
msr
S3_6_c15_c8_3
,
x0
ldr
x0
,
=
0x2001003FF
msr
S3_6_c15_c8_1
,
x0
mov
x0
,
#
2
msr
S3_6_c15_c8_0
,
x0
ldr
x0
,
=
0x10E3800200
msr
S3_6_c15_c8_2
,
x0
ldr
x0
,
=
0x10FFF003E0
msr
S3_6_c15_c8_3
,
x0
ldr
x0
,
=
0x2001003FF
msr
S3_6_c15_c8_1
,
x0
isb
1
:
ret
x17
endfunc
errata_a78_ae_1951502_wa
func
check_errata_1951502
/
*
Applies
to
revisions
r0p0
and
r0p1
.
*/
mov
x1
,
#
CPU_REV
(
0
,
0
)
mov
x2
,
#
CPU_REV
(
0
,
1
)
b
cpu_rev_var_range
endfunc
check_errata_1951502
/
*
-------------------------------------------------
*
The
CPU
Ops
reset
function
for
Cortex
-
A78
-
AE
*
-------------------------------------------------
*/
#if ENABLE_AMU
func
cortex_a78_ae_reset_func
mov
x19
,
x30
bl
cpu_get_rev_var
mov
x18
,
x0
#if ERRATA_A78_AE_1951502
mov
x0
,
x18
bl
errata_a78_ae_1951502_wa
#endif
#if ENABLE_AMU
/
*
Make
sure
accesses
from
EL0
/
EL1
and
EL2
are
not
trapped
to
EL3
*/
mrs
x0
,
actlr_el3
bic
x0
,
x0
,
#
CORTEX_A78_ACTLR_TAM_BIT
...
...
@@ -39,11 +101,12 @@ func cortex_a78_ae_reset_func
/
*
Enable
group1
counters
*/
mov
x0
,
#
CORTEX_A78_AMU_GROUP1_MASK
msr
CPUAMCNTENSET1_EL0
,
x0
#endif
isb
ret
ret
x19
endfunc
cortex_a78_ae_reset_func
#endif
/
*
-------------------------------------------------------
*
HW
will
do
the
cache
maintenance
while
powering
down
...
...
@@ -66,6 +129,18 @@ endfunc cortex_a78_ae_core_pwr_dwn
*/
#if REPORT_ERRATA
func
cortex_a78_ae_errata_report
stp
x8
,
x30
,
[
sp
,
#-
16
]!
bl
cpu_get_rev_var
mov
x8
,
x0
/
*
*
Report
all
errata
.
The
revision
-
variant
information
is
passed
to
*
checking
functions
of
each
errata
.
*/
report_errata
ERRATA_A78_AE_1951502
,
cortex_a78_ae
,
1951502
ldp
x8
,
x30
,
[
sp
],
#
16
ret
endfunc
cortex_a78_ae_errata_report
#endif
...
...
@@ -89,12 +164,6 @@ func cortex_a78_ae_cpu_reg_dump
ret
endfunc
cortex_a78_ae_cpu_reg_dump
#if ENABLE_AMU
#define A78_AE_RESET_FUNC cortex_a78_ae_reset_func
#else
#define A78_AE_RESET_FUNC CPU_NO_RESET_FUNC
#endif
declare_cpu_ops
cortex_a78_ae
,
CORTEX_A78_AE_MIDR
,
\
A78_AE_RESET_FUNC
,
\
cortex_a78_ae_reset_func
,
\
cortex_a78_ae_core_pwr_dwn
This diff is collapsed.
Click to expand it.
lib/cpus/cpu-ops.mk
View file @
0ed87212
#
# Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
# Copyright (c) 2020, NVIDIA Corporation. All rights reserved.
# Copyright (c) 2020
-2021
, NVIDIA Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
...
...
@@ -311,6 +311,10 @@ ERRATA_A78_1941498 ?=0
# well but there is no workaround for that revision.
ERRATA_A78_1951500
?=
0
# Flag to apply erratum 1951502 workaround during reset. This erratum applies
# to revisions r0p0 and r0p1 of the A78 AE cpu. It is still open.
ERRATA_A78_AE_1951502
?=
0
# Flag to apply erratum 1821534 workaround during reset. This erratum applies
# to revisions r0p0 and r1p0 of the A78 cpu.
ERRATA_A78_1821534
?=
0
...
...
@@ -646,6 +650,10 @@ $(eval $(call add_define,ERRATA_A78_1941498))
$(eval
$(call
assert_boolean,ERRATA_A78_1951500))
$(eval
$(call
add_define,ERRATA_A78_1951500))
# Process ERRATA_A78_AE_1951502 flag
$(eval
$(call
assert_boolean,ERRATA_A78_AE_1951502))
$(eval
$(call
add_define,ERRATA_A78_AE_1951502))
# Process ERRATA_A78_1821534 flag
$(eval
$(call
assert_boolean,ERRATA_A78_1821534))
$(eval
$(call
add_define,ERRATA_A78_1821534))
...
...
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