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Commit 0efb83e1 authored by Sandrine Bailleux's avatar Sandrine Bailleux Committed by TrustedFirmware Code Review
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Merge "Fix white space errors + remove #if defined" into integration

parents 63b96271 22cab650
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lib/cpus/aarch64/neoverse_n1.S
View file @ 0efb83e1
...@@ -21,9 +21,7 @@ ...@@ -21,9 +21,7 @@
#error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #error "Neoverse-N1 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
#endif #endif
#if ERRATA_N1_IC_TRAP
.global neoverse_n1_errata_ic_trap_handler .global neoverse_n1_errata_ic_trap_handler
#endif
/* -------------------------------------------------- /* --------------------------------------------------
* Errata Workaround for Neoverse N1 Erratum 1043202. * Errata Workaround for Neoverse N1 Erratum 1043202.
...@@ -356,7 +354,7 @@ func errata_n1_1542419_wa ...@@ -356,7 +354,7 @@ func errata_n1_1542419_wa
bl check_errata_1542419 bl check_errata_1542419
cbz x0, 1f cbz x0, 1f
/* Apply instruction patching sequence */ /* Apply instruction patching sequence */
ldr x0, =0x0 ldr x0, =0x0
msr CPUPSELR_EL3, x0 msr CPUPSELR_EL3, x0
ldr x0, =0xEE670D35 ldr x0, =0xEE670D35
...@@ -536,10 +534,10 @@ func neoverse_n1_errata_ic_trap_handler ...@@ -536,10 +534,10 @@ func neoverse_n1_errata_ic_trap_handler
tlbi vae3is, xzr tlbi vae3is, xzr
dsb sy dsb sy
# Skip the IC instruction itself # Skip the IC instruction itself
mrs x3, elr_el3 mrs x3, elr_el3
add x3, x3, #4 add x3, x3, #4
msr elr_el3, x3 msr elr_el3, x3
ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0] ldp x0, x1, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X0]
ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2] ldp x2, x3, [sp, #CTX_GPREGS_OFFSET + CTX_GPREG_X2]
......
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