Merge branch 'integration' into tf_issue_461

Makefile

@@ -50,10 +50,14 @@ include ${MAKE_HELPERS_DIRECTORY}build_env.mk
 # Default values for build configurations, and their dependencies
 ################################################################################
 
+ifdef ASM_ASSERTION
+        $(warning ASM_ASSERTION is removed, use ENABLE_ASSERTIONS instead.)
+endif
+
 include ${MAKE_HELPERS_DIRECTORY}defaults.mk
 
-# ASM_ASSERTION enabled for DEBUG builds only
-ASM_ASSERTION			:= ${DEBUG}
+# Assertions enabled for DEBUG builds by default
+ENABLE_ASSERTIONS		:= ${DEBUG}
 ENABLE_PMF			:= ${ENABLE_RUNTIME_INSTRUMENTATION}
 PLAT				:= ${DEFAULT_PLAT}
 
@@ -347,6 +351,11 @@ ifdef BL2_SOURCES
         endif
 endif
 
+# If SCP_BL2 is given, we always want FIP to include it.
+ifdef SCP_BL2
+        NEED_SCP_BL2		:=	yes
+endif
+
 # Process TBB related flags
 ifneq (${GENERATE_COT},0)
         # Common cert_create options
@@ -434,13 +443,13 @@ endif
 # Build options checks
 ################################################################################
 
-$(eval $(call assert_boolean,ASM_ASSERTION))
 $(eval $(call assert_boolean,COLD_BOOT_SINGLE_CPU))
 $(eval $(call assert_boolean,CREATE_KEYS))
 $(eval $(call assert_boolean,CTX_INCLUDE_AARCH32_REGS))
 $(eval $(call assert_boolean,CTX_INCLUDE_FPREGS))
 $(eval $(call assert_boolean,DEBUG))
 $(eval $(call assert_boolean,DISABLE_PEDANTIC))
+$(eval $(call assert_boolean,ENABLE_ASSERTIONS))
 $(eval $(call assert_boolean,ENABLE_PLAT_COMPAT))
 $(eval $(call assert_boolean,ENABLE_PMF))
 $(eval $(call assert_boolean,ENABLE_PSCI_STAT))
@@ -459,6 +468,7 @@ $(eval $(call assert_boolean,SEPARATE_CODE_AND_RODATA))
 $(eval $(call assert_boolean,SPIN_ON_BL1_EXIT))
 $(eval $(call assert_boolean,TRUSTED_BOARD_BOOT))
 $(eval $(call assert_boolean,USE_COHERENT_MEM))
+$(eval $(call assert_boolean,WARMBOOT_ENABLE_DCACHE_EARLY))
 
 $(eval $(call assert_numeric,ARM_ARCH_MAJOR))
 $(eval $(call assert_numeric,ARM_ARCH_MINOR))
@@ -473,10 +483,10 @@ $(eval $(call add_define,ARM_CCI_PRODUCT_ID))
 $(eval $(call add_define,ARM_ARCH_MAJOR))
 $(eval $(call add_define,ARM_ARCH_MINOR))
 $(eval $(call add_define,ARM_GIC_ARCH))
-$(eval $(call add_define,ASM_ASSERTION))
 $(eval $(call add_define,COLD_BOOT_SINGLE_CPU))
 $(eval $(call add_define,CTX_INCLUDE_AARCH32_REGS))
 $(eval $(call add_define,CTX_INCLUDE_FPREGS))
+$(eval $(call add_define,ENABLE_ASSERTIONS))
 $(eval $(call add_define,ENABLE_PLAT_COMPAT))
 $(eval $(call add_define,ENABLE_PMF))
 $(eval $(call add_define,ENABLE_PSCI_STAT))
@@ -496,6 +506,7 @@ $(eval $(call add_define,SPD_${SPD}))
 $(eval $(call add_define,SPIN_ON_BL1_EXIT))
 $(eval $(call add_define,TRUSTED_BOARD_BOOT))
 $(eval $(call add_define,USE_COHERENT_MEM))
+$(eval $(call add_define,WARMBOOT_ENABLE_DCACHE_EARLY))
 
 # Define the EL3_PAYLOAD_BASE flag only if it is provided.
 ifdef EL3_PAYLOAD_BASE
@@ -541,6 +552,10 @@ $(if ${BL2}, $(eval $(call MAKE_TOOL_ARGS,2,${BL2},tb-fw)),\
 	$(eval $(call MAKE_BL,2,tb-fw)))
 endif
 
+ifeq (${NEED_SCP_BL2},yes)
+$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
+endif
+
 ifeq (${NEED_BL31},yes)
 BL31_SOURCES += ${SPD_SOURCES}
 $(if ${BL31}, $(eval $(call MAKE_TOOL_ARGS,31,${BL31},soc-fw)),\

bl1/bl1_fwu.c

@@ -109,7 +109,7 @@ register_t bl1_fwu_smc_handler(unsigned int smc_fid,
 		break;
 	}
 
-	SMC_RET0(handle);
+	SMC_RET1(handle, SMC_UNK);
 }
 
 /*******************************************************************************

bl1/bl1_main.c

@@ -34,6 +34,7 @@
 #include <auth_mod.h>
 #include <bl1.h>
 #include <bl_common.h>
+#include <console.h>
 #include <debug.h>
 #include <errata_report.h>
 #include <platform.h>
@@ -113,7 +114,7 @@ void bl1_main(void)
 
 	print_errata_status();
 
-#if DEBUG
+#if ENABLE_ASSERTIONS
 	u_register_t val;
 	/*
 	 * Ensure that MMU/Caches and coherency are turned on
@@ -140,7 +141,7 @@ void bl1_main(void)
 		assert(CACHE_WRITEBACK_GRANULE == SIZE_FROM_LOG2_WORDS(val));
 	else
 		assert(CACHE_WRITEBACK_GRANULE <= MAX_CACHE_LINE_SIZE);
-#endif
+#endif /* ENABLE_ASSERTIONS */
 
 	/* Perform remaining generic architectural setup from EL3 */
 	bl1_arch_setup();
@@ -166,6 +167,8 @@ void bl1_main(void)
 		NOTICE("BL1-FWU: *******FWU Process Started*******\n");
 
 	bl1_prepare_next_image(image_id);
+
+	console_flush();
 }
 
 /*******************************************************************************

bl2/bl2_image_load_v2.c

@@ -109,6 +109,10 @@ entry_point_info_t *bl2_load_images(void)
 	assert(bl2_to_next_bl_params->head);
 	assert(bl2_to_next_bl_params->h.type == PARAM_BL_PARAMS);
 	assert(bl2_to_next_bl_params->h.version >= VERSION_2);
+	assert(bl2_to_next_bl_params->head->ep_info);
+
+	/* Populate arg0 for the next BL image */
+	bl2_to_next_bl_params->head->ep_info->args.arg0 = (u_register_t)bl2_to_next_bl_params;
 
 	/* Flush the parameters to be passed to next image */
 	plat_flush_next_bl_params();

bl2/bl2_main.c

 /*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -32,6 +32,7 @@
 #include <auth_mod.h>
 #include <bl1.h>
 #include <bl_common.h>
+#include <console.h>
 #include <debug.h>
 #include <platform.h>
 #include "bl2_private.h"
@@ -69,6 +70,8 @@ void bl2_main(void)
 	disable_mmu_icache_secure();
 #endif /* AARCH32 */
 
+	console_flush();
+
 	/*
 	 * Run next BL image via an SMC to BL1. Information on how to pass
 	 * control to the BL32 (if present) and BL33 software images will

bl2u/bl2u_main.c

 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -34,6 +34,7 @@
 #include <auth_mod.h>
 #include <bl_common.h>
 #include <bl1.h>
+#include <console.h>
 #include <debug.h>
 #include <platform.h>
 #include <platform_def.h>
@@ -63,6 +64,8 @@ void bl2u_main(void)
 	/* Perform platform setup in BL2U after loading SCP_BL2U */
 	bl2u_platform_setup();
 
+	console_flush();
+
 	/*
 	 * Indicate that BL2U is done and resume back to
 	 * normal world via an SMC to BL1.

bl31/aarch64/bl31_entrypoint.S

@@ -185,26 +185,27 @@ func bl31_warm_entrypoint
 	 *
 	 * The PSCI implementation invokes platform routines that enable CPUs to
 	 * participate in coherency. On a system where CPUs are not
-	 * cache-coherent out of reset, having caches enabled until such time
-	 * might lead to coherency issues (resulting from stale data getting
-	 * speculatively fetched, among others). Therefore we keep data caches
-	 * disabled while enabling the MMU, thereby forcing data accesses to
-	 * have non-cacheable, nGnRnE attributes (these will always be coherent
-	 * with main memory).
+	 * cache-coherent without appropriate platform specific programming,
+	 * having caches enabled until such time might lead to coherency issues
+	 * (resulting from stale data getting speculatively fetched, among
+	 * others). Therefore we keep data caches disabled even after enabling
+	 * the MMU for such platforms.
 	 *
-	 * On systems with hardware-assisted coherency, where CPUs are expected
-	 * to be cache-coherent out of reset without needing explicit software
-	 * intervention, PSCI need not invoke platform routines to enter
-	 * coherency (as CPUs already are); and there's no reason to have caches
-	 * disabled either.
+	 * On systems with hardware-assisted coherency, or on single cluster
+	 * platforms, such platform specific programming is not required to
+	 * enter coherency (as CPUs already are); and there's no reason to have
+	 * caches disabled either.
 	 */
-#if HW_ASSISTED_COHERENCY
-	mov	x0, #0
-#else
 	mov	x0, #DISABLE_DCACHE
-#endif
 	bl	bl31_plat_enable_mmu
 
+#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
+	mrs	x0, sctlr_el3
+	orr	x0, x0, #SCTLR_C_BIT
+	msr	sctlr_el3, x0
+	isb
+#endif
+
 	bl	psci_warmboot_entrypoint
 
 #if ENABLE_RUNTIME_INSTRUMENTATION

bl31/aarch64/crash_reporting.S

 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -349,6 +349,8 @@ func do_crash_reporting
 	/* Print some platform registers */
 	plat_crash_print_regs
 
+	bl	plat_crash_console_flush
+
 	/* Done reporting */
 	no_ret	plat_panic_handler
 endfunc do_crash_reporting

bl31/bl31_main.c

 /*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,6 +33,7 @@
 #include <assert.h>
 #include <bl_common.h>
 #include <bl31.h>
+#include <console.h>
 #include <context_mgmt.h>
 #include <debug.h>
 #include <platform.h>
@@ -129,6 +130,8 @@ void bl31_main(void)
 	 */
 	bl31_prepare_next_image_entry();
 
+	console_flush();
+
 	/*
 	 * Perform any platform specific runtime setup prior to cold boot exit
 	 * from BL31

bl32/sp_min/aarch32/entrypoint.S

@@ -236,24 +236,27 @@ func sp_min_warm_entrypoint
 	 *
 	 * The PSCI implementation invokes platform routines that enable CPUs to
 	 * participate in coherency. On a system where CPUs are not
-	 * cache-coherent out of reset, having caches enabled until such time
-	 * might lead to coherency issues (resulting from stale data getting
-	 * speculatively fetched, among others). Therefore we keep data caches
-	 * disabled while enabling the MMU, thereby forcing data accesses to
-	 * have non-cacheable, nGnRnE attributes (these will always be coherent
-	 * with main memory).
+	 * cache-coherent without appropriate platform specific programming,
+	 * having caches enabled until such time might lead to coherency issues
+	 * (resulting from stale data getting speculatively fetched, among
+	 * others). Therefore we keep data caches disabled even after enabling
+	 * the MMU for such platforms.
 	 *
-	 * On systems where CPUs are cache-coherent out of reset, however, PSCI
-	 * need not invoke platform routines to enter coherency (as CPUs already
-	 * are), and there's no reason to have caches disabled either.
+	 * On systems with hardware-assisted coherency, or on single cluster
+	 * platforms, such platform specific programming is not required to
+	 * enter coherency (as CPUs already are); and there's no reason to have
+	 * caches disabled either.
 	 */
-#if HW_ASSISTED_COHERENCY
-	mov	r0, #0
-#else
 	mov	r0, #DISABLE_DCACHE
-#endif
 	bl	bl32_plat_enable_mmu
 
+#if HW_ASSISTED_COHERENCY || WARMBOOT_ENABLE_DCACHE_EARLY
+	ldcopr	r0, SCTLR
+	orr	r0, r0, #SCTLR_C_BIT
+	stcopr	r0, SCTLR
+	isb
+#endif
+
 	bl	sp_min_warm_boot
 
 	/* Program the registers in cpu_context and exit monitor mode */

common/aarch32/debug.S

 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -70,9 +70,12 @@ func do_panic
 	/* Print new line */
 	ldr	r4, =panic_end
 	bl	asm_print_str
+
+	bl	plat_crash_console_flush
+
 1:
 	mov	lr, r6
-	b	plat_panic_handler
+	no_ret	plat_panic_handler
 endfunc do_panic
 
 	/***********************************************************
@@ -87,7 +90,7 @@ func report_exception
 	no_ret	plat_panic_handler
 endfunc report_exception
 
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
 .section .rodata.assert_str, "aS"
 assert_msg1:
 	.asciz "ASSERT: File "
@@ -104,6 +107,11 @@ assert_msg2:
  * ---------------------------------------------------------------------------
  */
 func asm_assert
+#if LOG_LEVEL >= LOG_LEVEL_INFO
+	/*
+	 * Only print the output if LOG_LEVEL is higher or equal to
+	 * LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
+	 */
 	/* Stash the parameters already in r0 and r1 */
 	mov	r5, r0
 	mov	r6, r1
@@ -140,10 +148,14 @@ dec_print_loop:
 	udiv	r5, r5, r6			/* Reduce divisor */
 	cmp	r5, #0
 	bne	dec_print_loop
+
+	bl	plat_crash_console_flush
+
 1:
+#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */
 	no_ret	plat_panic_handler
 endfunc asm_assert
-#endif
+#endif /* ENABLE_ASSERTIONS */
 
 /*
  * This function prints a string from address in r4

common/aarch64/debug.S

 /*
- * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -41,7 +41,7 @@
 /* The offset to add to get ascii for numerals '0 - 9' */
 #define ASCII_OFFSET_NUM	0x30
 
-#if ASM_ASSERTION
+#if ENABLE_ASSERTIONS
 .section .rodata.assert_str, "aS"
 assert_msg1:
 	.asciz "ASSERT: File "
@@ -78,6 +78,11 @@ dec_print_loop:
  * ---------------------------------------------------------------------------
  */
 func asm_assert
+#if LOG_LEVEL >= LOG_LEVEL_INFO
+	/*
+	 * Only print the output if LOG_LEVEL is higher or equal to
+	 * LOG_LEVEL_INFO, which is the default value for builds with DEBUG=1.
+	 */
 	mov	x5, x0
 	mov	x6, x1
 	/* Ensure the console is initialized */
@@ -96,10 +101,12 @@ func asm_assert
 	b.ne	_assert_loop
 	mov	x4, x6
 	asm_print_line_dec
+	bl	plat_crash_console_flush
 _assert_loop:
-	b	_assert_loop
+#endif /* LOG_LEVEL >= LOG_LEVEL_INFO */
+	no_ret	plat_panic_handler
 endfunc asm_assert
-#endif
+#endif /* ENABLE_ASSERTIONS */
 
 /*
  * This function prints a string from address in x4.
@@ -187,6 +194,8 @@ el3_panic:
 	sub	x4, x4, #4
 	bl	asm_print_hex
 
+	bl	plat_crash_console_flush
+
 _panic_handler:
 	/* Pass to plat_panic_handler the address from where el3_panic was
 	 * called, not the address of the call from el3_panic. */

common/desc_image_load.c

@@ -47,8 +47,11 @@ static bl_params_t next_bl_params;
  ******************************************************************************/
 void flush_bl_params_desc(void)
 {
-	flush_dcache_range((unsigned long)bl_mem_params_desc_ptr,
+	flush_dcache_range((uintptr_t)bl_mem_params_desc_ptr,
 			sizeof(*bl_mem_params_desc_ptr) * bl_mem_params_desc_num);
+
+	flush_dcache_range((uintptr_t)&next_bl_params,
+			sizeof(next_bl_params));
 }
 
 /*******************************************************************************
@@ -209,12 +212,5 @@ bl_params_t *get_next_bl_params_from_mem_params_desc(void)
 	/* Invalid image is expected to terminate the loop */
 	assert(img_id == INVALID_IMAGE_ID);
 
-	/* Populate arg0 for the next BL image */
-	next_bl_params.head->ep_info->args.arg0 = (unsigned long)&next_bl_params;
-
-	/* Flush the parameters to be passed to the next BL image */
-	flush_dcache_range((unsigned long)&next_bl_params,
-			sizeof(next_bl_params));
-
 	return &next_bl_params;
 }

docs/porting-guide.md

@@ -2242,6 +2242,17 @@ designated crash console. It must only use general purpose registers x1 and
 x2 to do its work. The parameter and the return value are in general purpose
 register x0.
 
+### Function : plat_crash_console_flush
+
+    Argument : void
+    Return   : int
+
+This API is used by the crash reporting mechanism to force write of all buffered
+data on the designated crash console. It should only use general purpose
+registers x0 and x1 to do its work. The return value is 0 on successful
+completion; otherwise the return value is -1.
+
+
 4.  Build flags
 ---------------
 

docs/user-guide.md

@@ -203,11 +203,6 @@ performed.
     in MPIDR is set and access the bit-fields in MPIDR accordingly. Default
     value of this flag is 0.
 
-*   `ASM_ASSERTION`: This flag determines whether the assertion checks within
-    assembly source files are enabled or not. This option defaults to the
-    value of `DEBUG` - that is, by default this is only enabled for a debug
-    build of the firmware.
-
 *   `BL2`: This is an optional build option which specifies the path to BL2
     image for the `fip` target. In this case, the BL2 in the ARM Trusted
     Firmware will not be built.
@@ -286,6 +281,14 @@ performed.
     payload. Please refer to the "Booting an EL3 payload" section for more
     details.
 
+*   `ENABLE_ASSERTIONS`: This option controls whether or not calls to `assert()`
+    are compiled out. For debug builds, this option defaults to 1, and calls to
+    `assert()` are left in place. For release builds, this option defaults to 0
+    and calls to `assert()` function are compiled out. This option can be set
+    independently of `DEBUG`. It can also be used to hide any auxiliary code
+    that is only required for the assertion and does not fit in the assertion
+    itself.
+
 *   `ENABLE_PMF`: Boolean option to enable support for optional Performance
      Measurement Framework(PMF). Default is 0.
 
@@ -349,7 +352,8 @@ performed.
     initiate the operations, and the rest is managed in hardware, minimizing
     active software management. In such systems, this boolean option enables ARM
     Trusted Firmware to carry out build and run-time optimizations during boot
-    and power management operations. This option defaults to 0.
+    and power management operations. This option defaults to 0 and if it is
+    enabled, then it implies `WARMBOOT_ENABLE_DCACHE_EARLY` is also enabled.
 
 *   `LOAD_IMAGE_V2`: Boolean option to enable support for new version (v2) of
     image loading, which provides more flexibility and scalability around what
@@ -508,6 +512,12 @@ performed.
     to a string formed by concatenating the version number, build type and build
     string.
 
+*   `WARMBOOT_ENABLE_DCACHE_EARLY` : Boolean option to enable D-cache early on
+    the CPU after warm boot. This is applicable for platforms which do not
+    require interconnect programming to enable cache coherency (eg: single
+    cluster platforms). If this option is enabled, then warm boot path
+    enables D-caches immediately after enabling MMU. This option defaults to 0.
+
 #### ARM development platform specific build options
 
 *   `ARM_BL31_IN_DRAM`: Boolean option to select loading of BL31 in TZC secured
@@ -568,6 +578,10 @@ performed.
     -   `tdram` : Trusted DRAM (if available)
     -   `dram`  : Secure region in DRAM (configured by the TrustZone controller)
 
+*   `ARM_XLAT_TABLES_LIB_V1`: boolean option to compile the Trusted Firmware
+    with version 1 of the translation tables library instead of version 2. It is
+    set to 0 by default, which selects version 2.
+
 For a better understanding of these options, the ARM development platform memory
 map is explained in the [Firmware Design].
 

drivers/arm/cci/cci.c

 /*
- * Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -39,7 +39,7 @@ static uintptr_t g_cci_base;
 static unsigned int g_max_master_id;
 static const int *g_cci_slave_if_map;
 
-#if DEBUG
+#if ENABLE_ASSERTIONS
 static int validate_cci_map(const int *map)
 {
 	unsigned int valid_cci_map = 0;
@@ -54,26 +54,25 @@ static int validate_cci_map(const int *map)
 			continue;
 
 		if (slave_if_id >= CCI_SLAVE_INTERFACE_COUNT) {
-			tf_printf("Slave interface ID is invalid\n");
+			ERROR("Slave interface ID is invalid\n");
 			return 0;
 		}
 
 		if (valid_cci_map & (1 << slave_if_id)) {
-			tf_printf("Multiple masters are assigned same"
-						" slave interface ID\n");
+			ERROR("Multiple masters are assigned same slave interface ID\n");
 			return 0;
 		}
 		valid_cci_map |= 1 << slave_if_id;
 	}
 
 	if (!valid_cci_map) {
-		tf_printf("No master is assigned a valid slave interface\n");
+		ERROR("No master is assigned a valid slave interface\n");
 		return 0;
 	}
 
 	return 1;
 }
-#endif /* DEBUG */
+#endif /* ENABLE_ASSERTIONS */
 
 void cci_init(uintptr_t cci_base,
 		const int *map,

drivers/arm/ccn/ccn.c

@@ -81,7 +81,7 @@ static inline void ccn_reg_write(uintptr_t periphbase,
 	mmio_write_64(region_base + register_offset, value);
 }
 
-#if DEBUG
+#if ENABLE_ASSERTIONS
 
 typedef struct rn_info {
 		unsigned char node_desc[MAX_RN_NODES];
@@ -224,7 +224,7 @@ static void ccn_validate_plat_params(const ccn_desc_t *plat_desc)
 		info.node_desc[node_id]--;
 	}
 }
-#endif /* DEBUG */
+#endif /* ENABLE_ASSERTIONS */
 
 /*******************************************************************************
  * This function validates parameters passed by the platform (in a debug build)
@@ -234,7 +234,7 @@ static void ccn_validate_plat_params(const ccn_desc_t *plat_desc)
  ******************************************************************************/
 void ccn_init(const ccn_desc_t *plat_desc)
 {
-#if DEBUG
+#if ENABLE_ASSERTIONS
 	ccn_validate_plat_params(plat_desc);
 #endif
 

drivers/arm/pl011/aarch32/pl011_console.S

 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -40,6 +40,7 @@
 	.globl	console_core_init
 	.globl	console_core_putc
 	.globl	console_core_getc
+	.globl	console_core_flush
 
 
 	/* -----------------------------------------------
@@ -158,3 +159,29 @@ getc_error:
 	mov	r0, #-1
 	bx	lr
 endfunc console_core_getc
+
+	/* ---------------------------------------------
+	 * int console_core_flush(uintptr_t base_addr)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * In : r0 - console base address
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : r0, r1
+	 * ---------------------------------------------
+	 */
+func console_core_flush
+	cmp	r0, #0
+	beq	flush_error
+
+1:
+	/* Loop while the transmit FIFO is busy */
+	ldr	r1, [r0, #UARTFR]
+	tst	r1, #PL011_UARTFR_BUSY
+	bne	1b
+
+	mov	r0, #0
+	bx	lr
+flush_error:
+	mov	r0, #-1
+	bx	lr
+endfunc console_core_flush

drivers/arm/pl011/aarch64/pl011_console.S

 /*
- * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -41,6 +41,7 @@
 	.globl	console_core_init
 	.globl	console_core_putc
 	.globl	console_core_getc
+	.globl	console_core_flush
 
 
 	/* -----------------------------------------------
@@ -151,3 +152,27 @@ getc_error:
 	mov	w0, #-1
 	ret
 endfunc console_core_getc
+
+	/* ---------------------------------------------
+	 * int console_core_flush(uintptr_t base_addr)
+	 * Function to force a write of all buffered
+	 * data that hasn't been output.
+	 * In : x0 - console base address
+	 * Out : return -1 on error else return 0.
+	 * Clobber list : x0, x1
+	 * ---------------------------------------------
+	 */
+func console_core_flush
+	cbz	x0, flush_error
+
+1:
+	/* Loop until the transmit FIFO is empty */
+	ldr	w1, [x0, #UARTFR]
+	tbnz	w1, #PL011_UARTFR_BUSY_BIT, 1b
+
+	mov	w0, #0
+	ret
+flush_error:
+	mov	w0, #-1
+	ret
+endfunc console_core_flush

drivers/arm/tzc/tzc400.c

 /*
- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -33,7 +33,7 @@
 #include <mmio.h>
 #include <stddef.h>
 #include <tzc400.h>
-#include "tzc_common_private.c"
+#include "tzc_common_private.h"
 
 /*
  * Macros which will be used by common core functions.