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Commit 0f22bef3 authored by Scott Branden's avatar Scott Branden Committed by GitHub
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Merge branch 'integration' into tf_issue_461

parents 53d9c9c8 dd454b40
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plat/arm/common/aarch64/arm_helpers.S
View file @ 0f22bef3
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -34,6 +34,7 @@
.weak plat_my_core_pos
.globl plat_crash_console_init
.globl plat_crash_console_putc
.globl plat_crash_console_flush
.globl platform_mem_init
......@@ -88,6 +89,19 @@ func plat_crash_console_putc
b console_core_putc
endfunc plat_crash_console_putc
/* ---------------------------------------------
* int plat_crash_console_flush()
* Function to force a write of all buffered
* data that hasn't been output.
* Out : return -1 on error else return 0.
* Clobber list : r0 - r1
* ---------------------------------------------
*/
func plat_crash_console_flush
mov_imm x1, PLAT_ARM_CRASH_UART_BASE
b console_core_flush
endfunc plat_crash_console_flush
/* ---------------------------------------------------------------------
* We don't need to carry out any memory initialization on ARM
* platforms. The Secure RAM is accessible straight away.
......
plat/arm/common/arm_bl1_setup.c
View file @ 0f22bef3
......@@ -30,13 +30,13 @@
#include <arch.h>
#include <arm_def.h>
#include <arm_xlat_tables.h>
#include <bl_common.h>
#include <console.h>
#include <platform_def.h>
#include <plat_arm.h>
#include <sp805.h>
#include <utils.h>
#include <xlat_tables_v2.h>
#include "../../../bl1/bl1_private.h"
/* Weak definitions may be overridden in specific ARM standard platform */
......@@ -44,6 +44,7 @@
#pragma weak bl1_plat_arch_setup
#pragma weak bl1_platform_setup
#pragma weak bl1_plat_sec_mem_layout
#pragma weak bl1_plat_prepare_exit
/* Data structure which holds the extents of the trusted SRAM for BL1*/
......
plat/arm/common/arm_bl2_setup.c
View file @ 0f22bef3
......@@ -249,11 +249,7 @@ void bl2_plat_arch_setup(void)
}
#if LOAD_IMAGE_V2
/*******************************************************************************
* This function can be used by the platforms to update/use image
* information for given `image_id`.
******************************************************************************/
int bl2_plat_handle_post_image_load(unsigned int image_id)
int arm_bl2_handle_post_image_load(unsigned int image_id)
{
int err = 0;
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
......@@ -286,6 +282,15 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
return err;
}
/*******************************************************************************
* This function can be used by the platforms to update/use image
* information for given `image_id`.
******************************************************************************/
int bl2_plat_handle_post_image_load(unsigned int image_id)
{
return arm_bl2_handle_post_image_load(image_id);
}
#else /* LOAD_IMAGE_V2 */
/*******************************************************************************
......
plat/arm/common/arm_common.c
View file @ 0f22bef3
......@@ -29,12 +29,12 @@
*/
#include <arch.h>
#include <arch_helpers.h>
#include <arm_xlat_tables.h>
#include <assert.h>
#include <debug.h>
#include <mmio.h>
#include <plat_arm.h>
#include <platform_def.h>
#include <xlat_tables_v2.h>
extern const mmap_region_t plat_arm_mmap[];
......
plat/arm/common/arm_common.mk
View file @ 0f22bef3
......@@ -95,6 +95,11 @@ ARM_PLAT_MT := 0
$(eval $(call assert_boolean,ARM_PLAT_MT))
$(eval $(call add_define,ARM_PLAT_MT))
# Use translation tables library v2 by default
ARM_XLAT_TABLES_LIB_V1 := 0
$(eval $(call assert_boolean,ARM_XLAT_TABLES_LIB_V1))
$(eval $(call add_define,ARM_XLAT_TABLES_LIB_V1))
# Enable PSCI_STAT_COUNT/RESIDENCY APIs on ARM platforms
ENABLE_PSCI_STAT := 1
ENABLE_PMF := 1
......@@ -113,11 +118,17 @@ ifeq (${ARCH}, aarch64)
PLAT_INCLUDES += -Iinclude/plat/arm/common/aarch64
endif
PLAT_BL_COMMON_SOURCES += plat/arm/common/${ARCH}/arm_helpers.S \
plat/arm/common/arm_common.c
ifeq (${ARM_XLAT_TABLES_LIB_V1}, 1)
PLAT_BL_COMMON_SOURCES += lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/${ARCH}/xlat_tables.c
else
include lib/xlat_tables_v2/xlat_tables.mk
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS} \
plat/arm/common/${ARCH}/arm_helpers.S \
plat/arm/common/arm_common.c
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
endif
BL1_SOURCES += drivers/arm/sp805/sp805.c \
drivers/io/io_fip.c \
......@@ -137,8 +148,14 @@ BL2_SOURCES += drivers/io/io_fip.c \
plat/arm/common/arm_bl2_setup.c \
plat/arm/common/arm_io_storage.c
ifeq (${LOAD_IMAGE_V2},1)
BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c\
plat/arm/common/arm_image_load.c \
# Because BL1/BL2 execute in AArch64 mode but BL32 in AArch32 we need to use
# the AArch32 descriptors.
ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
else
BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
endif
BL2_SOURCES += plat/arm/common/arm_image_load.c \
common/desc_image_load.c
endif
......
plat/arm/css/common/aarch32/css_helpers.S 0 → 100644
View file @ 0f22bef3
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <arch.h>
#include <asm_macros.S>
#include <cpu_macros.S>
#include <css_def.h>
.weak plat_secondary_cold_boot_setup
.weak plat_get_my_entrypoint
.globl css_calc_core_pos_swap_cluster
.weak plat_is_my_cpu_primary
/* ---------------------------------------------------------------------
* void plat_secondary_cold_boot_setup(void);
* In the normal boot flow, cold-booting secondary
* CPUs is not yet implemented and they panic.
* ---------------------------------------------------------------------
*/
func plat_secondary_cold_boot_setup
/* TODO: Implement secondary CPU cold boot setup on CSS platforms */
cb_panic:
b cb_panic
endfunc plat_secondary_cold_boot_setup
/* ---------------------------------------------------------------------
* uintptr_t plat_get_my_entrypoint (void);
*
* Main job of this routine is to distinguish between a cold and a warm
* boot. On CSS platforms, this distinction is based on the contents of
* the Trusted Mailbox. It is initialised to zero by the SCP before the
* AP cores are released from reset. Therefore, a zero mailbox means
* it's a cold reset.
*
* This functions returns the contents of the mailbox, i.e.:
* - 0 for a cold boot;
* - the warm boot entrypoint for a warm boot.
* ---------------------------------------------------------------------
*/
func plat_get_my_entrypoint
ldr r0, =PLAT_ARM_TRUSTED_MAILBOX_BASE
ldr r0, [r0]
bx lr
endfunc plat_get_my_entrypoint
/* -----------------------------------------------------------
* unsigned int css_calc_core_pos_swap_cluster(u_register_t mpidr)
* Utility function to calculate the core position by
* swapping the cluster order. This is necessary in order to
* match the format of the boot information passed by the SCP
* and read in plat_is_my_cpu_primary below.
* -----------------------------------------------------------
*/
func css_calc_core_pos_swap_cluster
and r1, r0, #MPIDR_CPU_MASK
and r0, r0, #MPIDR_CLUSTER_MASK
eor r0, r0, #(1 << MPIDR_AFFINITY_BITS) // swap cluster order
add r0, r1, r0, LSR #6
bx lr
endfunc css_calc_core_pos_swap_cluster
/* -----------------------------------------------------
* unsigned int plat_is_my_cpu_primary (void);
*
* Find out whether the current cpu is the primary
* cpu (applicable ony after a cold boot)
* -----------------------------------------------------
*/
func plat_is_my_cpu_primary
mov r10, lr
bl plat_my_core_pos
ldr r1, =SCP_BOOT_CFG_ADDR
ldr r1, [r1]
ubfx r1, r1, #PLAT_CSS_PRIMARY_CPU_SHIFT, \
#PLAT_CSS_PRIMARY_CPU_BIT_WIDTH
cmp r0, r1
moveq r0, #1
movne r0, #0
bx r10
endfunc plat_is_my_cpu_primary
plat/arm/css/common/css_common.mk
View file @ 0f22bef3
......@@ -36,7 +36,7 @@ PLAT_INCLUDES += -Iinclude/plat/arm/css/common \
-Iinclude/plat/arm/css/common/aarch64
PLAT_BL_COMMON_SOURCES += plat/arm/css/common/aarch64/css_helpers.S
PLAT_BL_COMMON_SOURCES += plat/arm/css/common/${ARCH}/css_helpers.S
BL1_SOURCES += plat/arm/css/common/css_bl1_setup.c
......@@ -64,7 +64,7 @@ $(eval $(call assert_boolean,CSS_LOAD_SCP_IMAGES))
$(eval $(call add_define,CSS_LOAD_SCP_IMAGES))
ifeq (${CSS_LOAD_SCP_IMAGES},1)
$(eval $(call FIP_ADD_IMG,SCP_BL2,--scp-fw))
NEED_SCP_BL2 := yes
ifneq (${TRUSTED_BOARD_BOOT},0)
$(eval $(call FWU_FIP_ADD_IMG,SCP_BL2U,--scp-fwu-cfg))
endif
......
plat/arm/css/common/css_pm.c
View file @ 0f22bef3
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -75,6 +75,13 @@ const unsigned int arm_pm_idle_states[] = {
CASSERT(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL1,
assert_max_pwr_lvl_supported_mismatch);
/*
* Ensure that the PLAT_MAX_PWR_LVL is not greater than CSS_SYSTEM_PWR_DMN_LVL
* assumed by the CSS layer.
*/
CASSERT(PLAT_MAX_PWR_LVL <= CSS_SYSTEM_PWR_DMN_LVL,
assert_max_pwr_lvl_higher_than_css_sys_lvl);
/*******************************************************************************
* Handler called when a power domain is about to be turned on. The
* level and mpidr determine the affinity instance.
......@@ -243,7 +250,7 @@ void css_get_sys_suspend_power_state(psci_power_state_t *req_state)
* System Suspend is supported only if the system power domain node
* is implemented.
*/
assert(PLAT_MAX_PWR_LVL >= ARM_PWR_LVL2);
assert(PLAT_MAX_PWR_LVL == CSS_SYSTEM_PWR_DMN_LVL);
for (i = ARM_PWR_LVL0; i <= PLAT_MAX_PWR_LVL; i++)
req_state->pwr_domain_state[i] = ARM_LOCAL_STATE_OFF;
......@@ -257,6 +264,39 @@ int css_node_hw_state(u_register_t mpidr, unsigned int power_level)
return css_scp_get_power_state(mpidr, power_level);
}
/*
* The system power domain suspend is only supported only via
* PSCI SYSTEM_SUSPEND API. PSCI CPU_SUSPEND request to system power domain
* will be downgraded to the lower level.
*/
static int css_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
int rc;
rc = arm_validate_power_state(power_state, req_state);
/*
* Ensure that the system power domain level is never suspended
* via PSCI CPU SUSPEND API. Currently system suspend is only
* supported via PSCI SYSTEM SUSPEND API.
*/
req_state->pwr_domain_state[CSS_SYSTEM_PWR_DMN_LVL] = ARM_LOCAL_STATE_RUN;
return rc;
}
/*
* Custom `translate_power_state_by_mpidr` handler for CSS. Unlike in the
* `css_validate_power_state`, we do not downgrade the system power
* domain level request in `power_state` as it will be used to query the
* PSCI_STAT_COUNT/RESIDENCY at the system power domain level.
*/
static int css_translate_power_state_by_mpidr(u_register_t mpidr,
unsigned int power_state,
psci_power_state_t *output_state)
{
return arm_validate_power_state(power_state, output_state);
}
/*******************************************************************************
* Export the platform handlers via plat_arm_psci_pm_ops. The ARM Standard
* platform will take care of registering the handlers with PSCI.
......@@ -270,7 +310,9 @@ plat_psci_ops_t plat_arm_psci_pm_ops = {
.pwr_domain_suspend_finish = css_pwr_domain_suspend_finish,
.system_off = css_system_off,
.system_reset = css_system_reset,
.validate_power_state = arm_validate_power_state,
.validate_power_state = css_validate_power_state,
.validate_ns_entrypoint = arm_validate_ns_entrypoint,
.get_node_hw_state = css_node_hw_state
.translate_power_state_by_mpidr = css_translate_power_state_by_mpidr,
.get_node_hw_state = css_node_hw_state,
.get_sys_suspend_power_state = css_get_sys_suspend_power_state
};
plat/arm/css/drivers/scp/css_pm_scpi.c
View file @ 0f22bef3
......@@ -32,6 +32,7 @@
#include <assert.h>
#include <css_pm.h>
#include <debug.h>
#include <plat_arm.h>
#include "../scpi/css_scpi.h"
#include "css_scp.h"
......@@ -134,6 +135,12 @@ void __dead2 css_scp_sys_shutdown(void)
{
uint32_t response;
/*
* Disable GIC CPU interface to prevent pending interrupt
* from waking up the AP from WFI.
*/
plat_arm_gic_cpuif_disable();
/* Send the power down request to the SCP */
response = scpi_sys_power_state(scpi_system_shutdown);
......@@ -153,6 +160,12 @@ void __dead2 css_scp_sys_reboot(void)
{
uint32_t response;
/*
* Disable GIC CPU interface to prevent pending interrupt
* from waking up the AP from WFI.
*/
plat_arm_gic_cpuif_disable();
/* Send the system reset request to the SCP */
response = scpi_sys_power_state(scpi_system_reboot);
......
plat/common/aarch32/platform_helpers.S
View file @ 0f22bef3
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -31,11 +31,43 @@
#include <arch.h>
#include <asm_macros.S>
.weak plat_crash_console_init
.weak plat_crash_console_putc
.weak plat_crash_console_flush
.weak plat_reset_handler
.weak plat_disable_acp
.weak platform_mem_init
.weak plat_panic_handler
/* -----------------------------------------------------
* Placeholder function which should be redefined by
* each platform.
* -----------------------------------------------------
*/
func plat_crash_console_init
mov r0, #0
bx lr
endfunc plat_crash_console_init
/* -----------------------------------------------------
* Placeholder function which should be redefined by
* each platform.
* -----------------------------------------------------
*/
func plat_crash_console_putc
bx lr
endfunc plat_crash_console_putc
/* -----------------------------------------------------
* Placeholder function which should be redefined by
* each platform.
* -----------------------------------------------------
*/
func plat_crash_console_flush
mov r0, #0
bx lr
endfunc plat_crash_console_flush
/* -----------------------------------------------------
* Placeholder function which should be redefined by
* each platform.
......
plat/common/aarch64/platform_helpers.S
View file @ 0f22bef3
/*
* Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -35,6 +35,7 @@
.weak plat_report_exception
.weak plat_crash_console_init
.weak plat_crash_console_putc
.weak plat_crash_console_flush
.weak plat_reset_handler
.weak plat_disable_acp
.weak bl1_plat_prepare_exit
......@@ -96,6 +97,15 @@ func plat_crash_console_putc
ret
endfunc plat_crash_console_putc
/* -----------------------------------------------------
* Placeholder function which should be redefined by
* each platform.
* -----------------------------------------------------
*/
func plat_crash_console_flush
ret
endfunc plat_crash_console_flush
/* -----------------------------------------------------
* Placeholder function which should be redefined by
* each platform. This function should preserve x19 - x29.
......
plat/common/aarch64/platform_mp_stack.S
View file @ 0f22bef3
/*
* Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -131,7 +131,7 @@ endfunc platform_set_stack
* -------------------------------------------------------
*/
func_deprecated platform_get_stack
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
mrs x1, mpidr_el1
cmp x0, x1
ASM_ASSERT(eq)
......@@ -150,7 +150,7 @@ endfunc_deprecated platform_get_stack
* -----------------------------------------------------
*/
func_deprecated platform_set_stack
#if ASM_ASSERTION
#if ENABLE_ASSERTIONS
mrs x1, mpidr_el1
cmp x0, x1
ASM_ASSERT(eq)
......
plat/mediatek/common/drivers/uart/8250_console.S
View file @ 0f22bef3
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -33,6 +33,7 @@
.globl console_core_init
.globl console_core_putc
.globl console_core_getc
.globl console_core_flush
/* -----------------------------------------------
* int console_core_init(unsigned long base_addr,
......@@ -170,3 +171,18 @@ getc_error:
mov w0, #-1
ret
endfunc console_core_getc
/* ---------------------------------------------
* int console_core_flush(uintptr_t base_addr)
* Function to force a write of all buffered
* data that hasn't been output.
* In : x0 - console base address
* Out : return -1 on error else return 0.
* Clobber list : x0, x1
* ---------------------------------------------
*/
func console_core_flush
/* Placeholder */
mov w0, #0
ret
endfunc console_core_flush
plat/nvidia/tegra/common/aarch64/tegra_helpers.S
View file @ 0f22bef3
......@@ -243,11 +243,12 @@ endfunc platform_mem_init
* ---------------------------------------------
*/
func plat_crash_console_init
adr x0, tegra_console_base
ldr x0, [x0]
mov_imm x1, TEGRA_BOOT_UART_CLK_IN_HZ
mov_imm x2, TEGRA_CONSOLE_BAUDRATE
b console_core_init
mov x0, #0
adr x1, tegra_console_base
ldr x1, [x1]
cbz x1, 1f
mov w0, #1
1: ret
endfunc plat_crash_console_init
/* ---------------------------------------------
......
plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
View file @ 0f22bef3
......@@ -37,7 +37,7 @@
#include <string.h>
#include <tegra_def.h>
#include <utils.h>
#include <xlat_tables.h>
#include <xlat_tables_v2.h>
#define TEGRA_GPU_RESET_REG_OFFSET 0x28c
#define GPU_RESET_BIT (1 << 24)
......@@ -135,17 +135,18 @@ static void tegra_clear_videomem(uintptr_t non_overlap_area_start,
unsigned long long non_overlap_area_size)
{
/*
* Perform cache maintenance to ensure that the non-overlapping area is
* zeroed out. The first invalidation of this range ensures that
* possible evictions of dirty cache lines do not interfere with the
* 'zeromem' operation. Other CPUs could speculatively prefetch the
* main memory contents of this area between the first invalidation and
* the 'zeromem' operation. The second invalidation ensures that any
* such cache lines are removed as well.
* Map the NS memory first, clean it and then unmap it.
*/
inv_dcache_range(non_overlap_area_start, non_overlap_area_size);
mmap_add_dynamic_region(non_overlap_area_start, /* PA */
non_overlap_area_start, /* VA */
non_overlap_area_size, /* size */
MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */
zeromem((void *)non_overlap_area_start, non_overlap_area_size);
inv_dcache_range(non_overlap_area_start, non_overlap_area_size);
flush_dcache_range(non_overlap_area_start, non_overlap_area_size);
mmap_remove_dynamic_region(non_overlap_area_start,
non_overlap_area_size);
}
/*
......@@ -194,7 +195,6 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
*/
INFO("Cleaning previous Video Memory Carveout\n");
disable_mmu_el3();
if (phys_base > vmem_end_old || video_mem_base > vmem_end_new) {
tegra_clear_videomem(video_mem_base, video_mem_size << 20);
} else {
......@@ -207,7 +207,6 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
tegra_clear_videomem(vmem_end_new, non_overlap_area_size);
}
}
enable_mmu_el3(0);
done:
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, (uint32_t)(phys_base >> 32));
......@@ -218,3 +217,29 @@ done:
video_mem_base = phys_base;
video_mem_size = size_in_bytes >> 20;
}
/*
* During boot, USB3 and flash media (SDMMC/SATA) devices need access to
* IRAM. Because these clients connect to the MC and do not have a direct
* path to the IRAM, the MC implements AHB redirection during boot to allow
* path to IRAM. In this mode, accesses to a programmed memory address aperture
* are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
* is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
* initialized to disable this aperture.
*
* Once bootup is complete, we must program IRAM base to 0xffffffff and
* IRAM top to 0x00000000, thus disabling access to IRAM. DRAM is then
* potentially accessible in this address range. These aperture registers
* also have an access_control/lock bit. After disabling the aperture, the
* access_control register should be programmed to lock the registers.
*/
void tegra_memctrl_disable_ahb_redirection(void)
{
/* program the aperture registers */
tegra_mc_write_32(MC_IRAM_BASE_LO, 0xFFFFFFFF);
tegra_mc_write_32(MC_IRAM_TOP_LO, 0);
tegra_mc_write_32(MC_IRAM_BASE_TOP_HI, 0);
/* lock the aperture registers */
tegra_mc_write_32(MC_IRAM_REG_CTRL, MC_DISABLE_IRAM_CFG_WRITES);
}
plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
View file @ 0f22bef3
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -30,6 +30,7 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
#include <mce.h>
#include <memctrl.h>
......@@ -48,193 +49,6 @@
static uint64_t video_mem_base;
static uint64_t video_mem_size_mb;
/* array to hold stream_id override config register offsets */
const static uint32_t streamid_overrides[] = {
MC_STREAMID_OVERRIDE_CFG_PTCR,
MC_STREAMID_OVERRIDE_CFG_AFIR,
MC_STREAMID_OVERRIDE_CFG_HDAR,
MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR,
MC_STREAMID_OVERRIDE_CFG_NVENCSRD,
MC_STREAMID_OVERRIDE_CFG_SATAR,
MC_STREAMID_OVERRIDE_CFG_MPCORER,
MC_STREAMID_OVERRIDE_CFG_NVENCSWR,
MC_STREAMID_OVERRIDE_CFG_AFIW,
MC_STREAMID_OVERRIDE_CFG_SATAW,
MC_STREAMID_OVERRIDE_CFG_MPCOREW,
MC_STREAMID_OVERRIDE_CFG_SATAW,
MC_STREAMID_OVERRIDE_CFG_HDAW,
MC_STREAMID_OVERRIDE_CFG_ISPRA,
MC_STREAMID_OVERRIDE_CFG_ISPWA,
MC_STREAMID_OVERRIDE_CFG_ISPWB,
MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR,
MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW,
MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR,
MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW,
MC_STREAMID_OVERRIDE_CFG_TSECSRD,
MC_STREAMID_OVERRIDE_CFG_TSECSWR,
MC_STREAMID_OVERRIDE_CFG_GPUSRD,
MC_STREAMID_OVERRIDE_CFG_GPUSWR,
MC_STREAMID_OVERRIDE_CFG_SDMMCRA,
MC_STREAMID_OVERRIDE_CFG_SDMMCRAA,
MC_STREAMID_OVERRIDE_CFG_SDMMCR,
MC_STREAMID_OVERRIDE_CFG_SDMMCRAB,
MC_STREAMID_OVERRIDE_CFG_SDMMCWA,
MC_STREAMID_OVERRIDE_CFG_SDMMCWAA,
MC_STREAMID_OVERRIDE_CFG_SDMMCW,
MC_STREAMID_OVERRIDE_CFG_SDMMCWAB,
MC_STREAMID_OVERRIDE_CFG_VICSRD,
MC_STREAMID_OVERRIDE_CFG_VICSWR,
MC_STREAMID_OVERRIDE_CFG_VIW,
MC_STREAMID_OVERRIDE_CFG_NVDECSRD,
MC_STREAMID_OVERRIDE_CFG_NVDECSWR,
MC_STREAMID_OVERRIDE_CFG_APER,
MC_STREAMID_OVERRIDE_CFG_APEW,
MC_STREAMID_OVERRIDE_CFG_NVJPGSRD,
MC_STREAMID_OVERRIDE_CFG_NVJPGSWR,
MC_STREAMID_OVERRIDE_CFG_SESRD,
MC_STREAMID_OVERRIDE_CFG_SESWR,
MC_STREAMID_OVERRIDE_CFG_ETRR,
MC_STREAMID_OVERRIDE_CFG_ETRW,
MC_STREAMID_OVERRIDE_CFG_TSECSRDB,
MC_STREAMID_OVERRIDE_CFG_TSECSWRB,
MC_STREAMID_OVERRIDE_CFG_GPUSRD2,
MC_STREAMID_OVERRIDE_CFG_GPUSWR2,
MC_STREAMID_OVERRIDE_CFG_AXISR,
MC_STREAMID_OVERRIDE_CFG_AXISW,
MC_STREAMID_OVERRIDE_CFG_EQOSR,
MC_STREAMID_OVERRIDE_CFG_EQOSW,
MC_STREAMID_OVERRIDE_CFG_UFSHCR,
MC_STREAMID_OVERRIDE_CFG_UFSHCW,
MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR,
MC_STREAMID_OVERRIDE_CFG_BPMPR,
MC_STREAMID_OVERRIDE_CFG_BPMPW,
MC_STREAMID_OVERRIDE_CFG_BPMPDMAR,
MC_STREAMID_OVERRIDE_CFG_BPMPDMAW,
MC_STREAMID_OVERRIDE_CFG_AONR,
MC_STREAMID_OVERRIDE_CFG_AONW,
MC_STREAMID_OVERRIDE_CFG_AONDMAR,
MC_STREAMID_OVERRIDE_CFG_AONDMAW,
MC_STREAMID_OVERRIDE_CFG_SCER,
MC_STREAMID_OVERRIDE_CFG_SCEW,
MC_STREAMID_OVERRIDE_CFG_SCEDMAR,
MC_STREAMID_OVERRIDE_CFG_SCEDMAW,
MC_STREAMID_OVERRIDE_CFG_APEDMAR,
MC_STREAMID_OVERRIDE_CFG_APEDMAW,
MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1,
MC_STREAMID_OVERRIDE_CFG_VICSRD1,
MC_STREAMID_OVERRIDE_CFG_NVDECSRD1
};
/* array to hold the security configs for stream IDs */
const static mc_streamid_security_cfg_t sec_cfgs[] = {
mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(XUSB_DEVR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(VICSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(NVENCSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(TSECSRDB, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(AXISW, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SDMMCWAB, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(AONDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(GPUSWR2, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(XUSB_HOSTW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(TSECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCRAA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(AONW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCRA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(AONR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(SESRD, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(NVENCSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(GPUSWR, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
};
const static mc_txn_override_cfg_t mc_override_cfgs[] = {
mc_make_txn_override_cfg(BPMPW, CGID_TAG_ADR),
mc_make_txn_override_cfg(EQOSW, CGID_TAG_ADR),
mc_make_txn_override_cfg(NVJPGSWR, CGID_TAG_ADR),
mc_make_txn_override_cfg(SDMMCWAA, CGID_TAG_ADR),
mc_make_txn_override_cfg(MPCOREW, CGID_TAG_ADR),
mc_make_txn_override_cfg(SCEDMAW, CGID_TAG_ADR),
mc_make_txn_override_cfg(SDMMCW, CGID_TAG_ADR),
mc_make_txn_override_cfg(AXISW, CGID_TAG_ADR),
mc_make_txn_override_cfg(TSECSWR, CGID_TAG_ADR),
mc_make_txn_override_cfg(GPUSWR, CGID_TAG_ADR),
mc_make_txn_override_cfg(XUSB_HOSTW, CGID_TAG_ADR),
mc_make_txn_override_cfg(TSECSWRB, CGID_TAG_ADR),
mc_make_txn_override_cfg(GPUSWR2, CGID_TAG_ADR),
mc_make_txn_override_cfg(AONDMAW, CGID_TAG_ADR),
mc_make_txn_override_cfg(AONW, CGID_TAG_ADR),
mc_make_txn_override_cfg(SESWR, CGID_TAG_ADR),
mc_make_txn_override_cfg(BPMPDMAW, CGID_TAG_ADR),
mc_make_txn_override_cfg(SDMMCWA, CGID_TAG_ADR),
mc_make_txn_override_cfg(HDAW, CGID_TAG_ADR),
mc_make_txn_override_cfg(NVDECSWR, CGID_TAG_ADR),
mc_make_txn_override_cfg(UFSHCW, CGID_TAG_ADR),
mc_make_txn_override_cfg(SATAW, CGID_TAG_ADR),
mc_make_txn_override_cfg(ETRW, CGID_TAG_ADR),
mc_make_txn_override_cfg(VICSWR, CGID_TAG_ADR),
mc_make_txn_override_cfg(NVENCSWR, CGID_TAG_ADR),
mc_make_txn_override_cfg(SDMMCWAB, CGID_TAG_ADR),
mc_make_txn_override_cfg(ISPWB, CGID_TAG_ADR),
mc_make_txn_override_cfg(APEW, CGID_TAG_ADR),
mc_make_txn_override_cfg(XUSB_DEVW, CGID_TAG_ADR),
mc_make_txn_override_cfg(AFIW, CGID_TAG_ADR),
mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
};
static void tegra_memctrl_reconfig_mss_clients(void)
{
#if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS
......@@ -248,8 +62,10 @@ static void tegra_memctrl_reconfig_mss_clients(void)
val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL);
wdata_0 = MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
#if ENABLE_AFI_DEVICE
MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
#endif
MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB;
......@@ -296,7 +112,9 @@ static void tegra_memctrl_reconfig_mss_clients(void)
* of control on overriding the memory type. So, remove TSA's
* memtype override.
*/
#if ENABLE_AFI_DEVICE
mc_set_tsa_passthrough(AFIW);
#endif
mc_set_tsa_passthrough(HDAW);
mc_set_tsa_passthrough(SATAW);
mc_set_tsa_passthrough(XUSB_HOSTW);
......@@ -321,15 +139,19 @@ static void tegra_memctrl_reconfig_mss_clients(void)
* whose AXI IDs we know and trust.
*/
#if ENABLE_AFI_DEVICE
/* Match AFIW */
mc_set_forced_coherent_so_dev_cfg(AFIR);
#endif
/*
* See bug 200131110 comment #35 - there are no normal requests
* and AWID for SO/DEV requests is hardcoded in RTL for a
* particular PCIE controller
*/
#if ENABLE_AFI_DEVICE
mc_set_forced_coherent_so_dev_cfg(AFIW);
#endif
mc_set_forced_coherent_cfg(HDAR);
mc_set_forced_coherent_cfg(HDAW);
mc_set_forced_coherent_cfg(SATAR);
......@@ -374,7 +196,9 @@ static void tegra_memctrl_reconfig_mss_clients(void)
* boot and strongly ordered MSS clients
*/
val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL &
#if ENABLE_AFI_DEVICE
mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) &
#endif
mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) &
mc_set_pcfifo_unordered_boot_so_mss(1, SATAW);
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val);
......@@ -411,7 +235,9 @@ static void tegra_memctrl_reconfig_mss_clients(void)
* for boot and strongly ordered MSS clients
*/
val = MC_SMMU_CLIENT_CONFIG1_RESET_VAL &
#if ENABLE_AFI_DEVICE
mc_set_smmu_unordered_boot_so_mss(1, AFIW) &
#endif
mc_set_smmu_unordered_boot_so_mss(1, HDAW) &
mc_set_smmu_unordered_boot_so_mss(1, SATAW);
tegra_mc_write_32(MC_SMMU_CLIENT_CONFIG1, val);
......@@ -480,33 +306,95 @@ static void tegra_memctrl_reconfig_mss_clients(void)
#endif
}
static void tegra_memctrl_set_overrides(void)
{
tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
const mc_txn_override_cfg_t *mc_txn_override_cfgs;
uint32_t num_txn_override_cfgs;
uint32_t i, val;
/* Get the settings from the platform */
assert(plat_mc_settings);
mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
/*
* Set the MC_TXN_OVERRIDE registers for write clients.
*/
if ((tegra_chipid_is_t186()) &&
(!tegra_platform_is_silicon() ||
(tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1)))) {
/*
* GPU and NVENC settings for Tegra186 simulation and
* Silicon rev. A01
*/
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2,
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR,
val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
} else {
/*
* Settings for Tegra186 silicon rev. A02 and onwards.
*/
for (i = 0; i < num_txn_override_cfgs; i++) {
val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
val | mc_txn_override_cfgs[i].cgid_tag);
}
}
}
/*
* Init Memory controller during boot.
*/
void tegra_memctrl_setup(void)
{
uint32_t val;
uint32_t num_overrides = sizeof(streamid_overrides) / sizeof(uint32_t);
uint32_t num_sec_cfgs = sizeof(sec_cfgs) / sizeof(mc_streamid_security_cfg_t);
uint32_t num_txn_overrides = sizeof(mc_override_cfgs) / sizeof(mc_txn_override_cfg_t);
int i;
const uint32_t *mc_streamid_override_regs;
uint32_t num_streamid_override_regs;
const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs;
uint32_t num_streamid_sec_cfgs;
tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
uint32_t i;
INFO("Tegra Memory Controller (v2)\n");
#if ENABLE_SMMU_DEVICE
/* Program the SMMU pagesize */
tegra_smmu_init();
#endif
/* Get the settings from the platform */
assert(plat_mc_settings);
mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg;
num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs;
/* Program all the Stream ID overrides */
for (i = 0; i < num_overrides; i++)
tegra_mc_streamid_write_32(streamid_overrides[i],
for (i = 0; i < num_streamid_override_regs; i++)
tegra_mc_streamid_write_32(mc_streamid_override_regs[i],
MC_STREAM_ID_MAX);
/* Program the security config settings for all Stream IDs */
for (i = 0; i < num_sec_cfgs; i++) {
val = sec_cfgs[i].override_enable << 16 |
sec_cfgs[i].override_client_inputs << 8 |
sec_cfgs[i].override_client_ns_flag << 0;
tegra_mc_streamid_write_32(sec_cfgs[i].offset, val);
for (i = 0; i < num_streamid_sec_cfgs; i++) {
val = mc_streamid_sec_cfgs[i].override_enable << 16 |
mc_streamid_sec_cfgs[i].override_client_inputs << 8 |
mc_streamid_sec_cfgs[i].override_client_ns_flag << 0;
tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val);
}
/*
......@@ -533,39 +421,8 @@ void tegra_memctrl_setup(void)
*/
tegra_memctrl_reconfig_mss_clients();
/*
* Set the MC_TXN_OVERRIDE registers for write clients.
*/
if (!tegra_platform_is_silicon() ||
(tegra_platform_is_silicon() && tegra_get_chipid_minor() == 1)) {
/* GPU and NVENC settings for rev. A01 */
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2,
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR,
val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
} else {
/* settings for rev. A02 */
for (i = 0; i < num_txn_overrides; i++) {
val = tegra_mc_read_32(mc_override_cfgs[i].offset);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(mc_override_cfgs[i].offset,
val | mc_override_cfgs[i].cgid_tag);
}
}
/* Program overrides for MC transactions */
tegra_memctrl_set_overrides();
}
/*
......@@ -581,6 +438,9 @@ void tegra_memctrl_restore_settings(void)
*/
tegra_memctrl_reconfig_mss_clients();
/* Program overrides for MC transactions */
tegra_memctrl_set_overrides();
/* video memory carveout region */
if (video_mem_base) {
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
......@@ -658,13 +518,6 @@ void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes)
index += 4)
tegra_mc_write_32(index, 0);
/*
* Allow CPU read/write access to the aperture
*/
tegra_mc_write_32(MC_TZRAM_CARVEOUT_CLIENT_ACCESS_CFG1,
TZRAM_CARVEOUT_CPU_WRITE_ACCESS_BIT |
TZRAM_CARVEOUT_CPU_READ_ACCESS_BIT);
/*
* Set the TZRAM base. TZRAM base must be 4k aligned, at least.
*/
......@@ -743,3 +596,11 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
*/
mce_update_gsc_videomem();
}
/*
* This feature exists only for v1 of the Tegra Memory Controller.
*/
void tegra_memctrl_disable_ahb_redirection(void)
{
; /* do nothing */
}
plat/nvidia/tegra/common/drivers/smmu/smmu.c 0 → 100644
View file @ 0f22bef3
/*
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
#include <platform_def.h>
#include <smmu.h>
#include <string.h>
#include <tegra_private.h>
/* SMMU IDs currently supported by the driver */
enum {
TEGRA_SMMU0,
TEGRA_SMMU1,
TEGRA_SMMU2
};
static uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
{
#if defined(TEGRA_SMMU0_BASE)
if (smmu_id == TEGRA_SMMU0)
return mmio_read_32(TEGRA_SMMU0_BASE + off);
#endif
#if defined(TEGRA_SMMU1_BASE)
if (smmu_id == TEGRA_SMMU1)
return mmio_read_32(TEGRA_SMMU1_BASE + off);
#endif
#if defined(TEGRA_SMMU2_BASE)
if (smmu_id == TEGRA_SMMU2)
return mmio_read_32(TEGRA_SMMU2_BASE + off);
#endif
return 0;
}
static void tegra_smmu_write_32(uint32_t smmu_id,
uint32_t off, uint32_t val)
{
#if defined(TEGRA_SMMU0_BASE)
if (smmu_id == TEGRA_SMMU0)
mmio_write_32(TEGRA_SMMU0_BASE + off, val);
#endif
#if defined(TEGRA_SMMU1_BASE)
if (smmu_id == TEGRA_SMMU1)
mmio_write_32(TEGRA_SMMU1_BASE + off, val);
#endif
#if defined(TEGRA_SMMU2_BASE)
if (smmu_id == TEGRA_SMMU2)
mmio_write_32(TEGRA_SMMU2_BASE + off, val);
#endif
}
/*
* Save SMMU settings before "System Suspend" to TZDRAM
*/
void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
{
uint32_t i, num_entries = 0;
smmu_regs_t *smmu_ctx_regs;
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t tzdram_base = params_from_bl2->tzdram_base;
uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size;
uint32_t reg_id1, pgshift, cb_size;
/* sanity check SMMU settings c*/
reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1));
pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12;
cb_size = (2 << pgshift) * \
(1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1));
assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
/* get SMMU context table */
smmu_ctx_regs = plat_get_smmu_ctx();
assert(smmu_ctx_regs);
/*
* smmu_ctx_regs[0].val contains the size of the context table minus
* the last entry. Sanity check the table size before we start with
* the context save operation.
*/
while (smmu_ctx_regs[num_entries].val != 0xFFFFFFFFU) {
num_entries++;
}
/* panic if the sizes do not match */
if (num_entries != smmu_ctx_regs[0].val)
panic();
/* save SMMU register values */
for (i = 1; i < num_entries; i++)
smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
/* increment by 1 to take care of the last entry */
num_entries++;
/* Save SMMU config settings */
memcpy16((void *)(uintptr_t)smmu_ctx_addr, (void *)smmu_ctx_regs,
(sizeof(smmu_regs_t) * num_entries));
/* save the SMMU table address */
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_LO,
(uint32_t)smmu_ctx_addr);
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV11_HI,
(uint32_t)(smmu_ctx_addr >> 32));
}
#define SMMU_NUM_CONTEXTS 64
#define SMMU_CONTEXT_BANK_MAX_IDX 64
/*
* Init SMMU during boot or "System Suspend" exit
*/
void tegra_smmu_init(void)
{
uint32_t val, cb_idx, smmu_id, ctx_base;
for (smmu_id = 0; smmu_id < NUM_SMMU_DEVICES; smmu_id++) {
/* Program the SMMU pagesize and reset CACHE_LOCK bit */
val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
val |= SMMU_GSR0_PGSIZE_64K;
val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
/* reset CACHE LOCK bit for NS Aux. Config. Register */
val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
/* disable TCU prefetch for all contexts */
ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS)
+ SMMU_CBn_ACTLR;
for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
val = tegra_smmu_read_32(smmu_id,
ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
val &= ~SMMU_CBn_ACTLR_CPRE_BIT;
tegra_smmu_write_32(smmu_id, ctx_base +
(SMMU_GSR0_PGSIZE_64K * cb_idx), val);
}
/* set CACHE LOCK bit for NS Aux. Config. Register */
val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
/* set CACHE LOCK bit for S Aux. Config. Register */
val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
}
}
plat/nvidia/tegra/common/tegra_bl31_setup.c
View file @ 0f22bef3
......@@ -202,9 +202,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
*/
console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
TEGRA_CONSOLE_BAUDRATE);
/* Initialise crash console */
plat_crash_console_init();
}
/*
......@@ -299,7 +296,16 @@ void bl31_platform_setup(void)
******************************************************************************/
void bl31_plat_runtime_setup(void)
{
; /* do nothing */
/*
* During boot, USB3 and flash media (SDMMC/SATA) devices need
* access to IRAM. Because these clients connect to the MC and
* do not have a direct path to the IRAM, the MC implements AHB
* redirection during boot to allow path to IRAM. In this mode
* accesses to a programmed memory address aperture are directed
* to the AHB bus, allowing access to the IRAM. This mode must be
* disabled before we jump to the non-secure world.
*/
tegra_memctrl_disable_ahb_redirection();
}
/*******************************************************************************
......
plat/nvidia/tegra/common/tegra_common.mk
View file @ 0f22bef3
......@@ -28,22 +28,12 @@
# POSSIBILITY OF SUCH DAMAGE.
#
CRASH_REPORTING := 1
$(eval $(call add_define,CRASH_REPORTING))
ASM_ASSERTION := 1
$(eval $(call add_define,ASM_ASSERTION))
USE_COHERENT_MEM := 0
SEPARATE_CODE_AND_RODATA := 1
PLAT_INCLUDES := -Iplat/nvidia/tegra/include/drivers \
-Iplat/nvidia/tegra/include \
-Iplat/nvidia/tegra/include/${TARGET_SOC}
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/xlat_tables_common.c \
lib/xlat_tables/aarch64/xlat_tables.c
include lib/xlat_tables_v2/xlat_tables.mk
PLAT_BL_COMMON_SOURCES += ${XLAT_TABLES_LIB_SRCS}
COMMON_DIR := plat/nvidia/tegra/common
......
plat/nvidia/tegra/common/tegra_platform.c
View file @ 0f22bef3
......@@ -69,6 +69,7 @@ typedef enum tegra_platform {
typedef enum tegra_chipid {
TEGRA_CHIPID_TEGRA13 = 0x13,
TEGRA_CHIPID_TEGRA21 = 0x21,
TEGRA_CHIPID_TEGRA18 = 0x18,
} tegra_chipid_t;
/*
......@@ -109,6 +110,13 @@ uint8_t tegra_chipid_is_t210(void)
return (chip_id == TEGRA_CHIPID_TEGRA21);
}
uint8_t tegra_chipid_is_t186(void)
{
uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
return (chip_id == TEGRA_CHIPID_TEGRA18);
}
/*
* Read the chip ID value and derive the platform
*/
......
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