Commit 1272391e authored by Madhukar Pappireddy's avatar Madhukar Pappireddy Committed by TrustedFirmware Code Review
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Merge changes Ie5c48303,I5d363c46 into integration

* changes:
  tzc400: adjust filter flag if it is set to FILTER_BIT_ALL
  tzc400: fix logical error in FILTER_BIT definitions
parents c36e2d48 d4c61c38
/* /*
* Copyright (c) 2016-2020, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -162,7 +162,9 @@ void tzc400_configure_region0(unsigned int sec_attr, ...@@ -162,7 +162,9 @@ void tzc400_configure_region0(unsigned int sec_attr,
/* /*
* `tzc400_configure_region` is used to program regions into the TrustZone * `tzc400_configure_region` is used to program regions into the TrustZone
* controller. A region can be associated with more than one filter. The * controller. A region can be associated with more than one filter. The
* associated filters are passed in as a bitmap (bit0 = filter0). * associated filters are passed in as a bitmap (bit0 = filter0), except that
* the value TZC_400_REGION_ATTR_FILTER_BIT_ALL selects all filters, based on
* the value of tzc400.num_filters.
* NOTE: * NOTE:
* Region 0 is special; it is preferable to use tzc400_configure_region0 * Region 0 is special; it is preferable to use tzc400_configure_region0
* for this region (see comment for that function). * for this region (see comment for that function).
...@@ -176,6 +178,11 @@ void tzc400_configure_region(unsigned int filters, ...@@ -176,6 +178,11 @@ void tzc400_configure_region(unsigned int filters,
{ {
assert(tzc400.base != 0U); assert(tzc400.base != 0U);
/* Adjust filter mask by real filter number */
if (filters == TZC_400_REGION_ATTR_FILTER_BIT_ALL) {
filters = (1U << tzc400.num_filters) - 1U;
}
/* Do range checks on filters and regions. */ /* Do range checks on filters and regions. */
assert(((filters >> tzc400.num_filters) == 0U) && assert(((filters >> tzc400.num_filters) == 0U) &&
(region < tzc400.num_regions)); (region < tzc400.num_regions));
......
/* /*
* Copyright (c) 2014-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -80,11 +80,8 @@ ...@@ -80,11 +80,8 @@
/* Filter enable bits in a TZC */ /* Filter enable bits in a TZC */
#define TZC_400_REGION_ATTR_F_EN_MASK U(0xf) #define TZC_400_REGION_ATTR_F_EN_MASK U(0xf)
#define TZC_400_REGION_ATTR_FILTER_BIT(x) \ #define TZC_400_REGION_ATTR_FILTER_BIT(x) (U(1) << (x))
((U(1) << (x)) << TZC_REGION_ATTR_F_EN_SHIFT) #define TZC_400_REGION_ATTR_FILTER_BIT_ALL TZC_400_REGION_ATTR_F_EN_MASK
#define TZC_400_REGION_ATTR_FILTER_BIT_ALL \
(TZC_400_REGION_ATTR_F_EN_MASK << \
TZC_REGION_ATTR_F_EN_SHIFT)
/* /*
* All TZC region configuration registers are placed one after another. It * All TZC region configuration registers are placed one after another. It
......
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