zynqmp: pm: Add CLK_SET_RATE_PARENT in gem clock node

Existing implementation does not allow to change the value of the
DIV1 because DIV2 does not have SET_RATE_PARENT flag.
This causes DIV1 value to be fixed and only value of DIV2 will be
adjusted according to required clock rate.
Signed-off-by: Ravi Patel <ravi.patel@xilinx.com>
Signed-off-by: Jolly Shah <jolly.shah@xilinx.com>
Change-Id: Ic6c4ca091bf0c5dc91ebddf86621c82c705dc87b

plat/xilinx/zynqmp/pm_service/pm_api_clock.c

@@ -582,7 +582,8 @@ static struct pm_clock_node gem_ref_ungated_nodes[] = {
 		.type = TYPE_DIV2,
 		.offset = 16,
 		.width = 6,
-		.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC,
+		.clkflags = CLK_SET_RATE_NO_REPARENT | CLK_IS_BASIC |
+			    CLK_SET_RATE_PARENT,
 		.typeflags = CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
 		.mult = NA_MULT,
 		.div = NA_DIV,