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Commit 1830f790 authored by Xing Zheng's avatar Xing Zheng
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rockchip: Clean up header and referenced files 



So far, there are more and more features are supported on the RK3399,
meanwhile, these features are increasingly being defined and intertwined.
It's time to clean up and make them clearer.
Signed-off-by: default avatarXing Zheng <zhengxing@rock-chips.com>
parent a7519b6b
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plat/rockchip/rk3399/drivers/dram/dram.h
View file @ 1830f790
......@@ -30,111 +30,11 @@
#ifndef __SOC_ROCKCHIP_RK3399_DRAM_H__
#define __SOC_ROCKCHIP_RK3399_DRAM_H__
#include <dram_regs.h>
#include <plat_private.h>
#include <stdint.h>
#define CTL_BASE(ch) (0xffa80000 + (ch) * 0x8000)
#define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4)
#define PI_OFFSET 0x800
#define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET)
#define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4)
#define PHY_OFFSET 0x2000
#define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET)
#define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4)
#define MSCH_BASE(ch) (0xffa84000 + (ch) * 0x8000)
#define MSCH_ID_COREID 0x0
#define MSCH_ID_REVISIONID 0x4
#define MSCH_DEVICECONF 0x8
#define MSCH_DEVICESIZE 0xc
#define MSCH_DDRTIMINGA0 0x10
#define MSCH_DDRTIMINGB0 0x14
#define MSCH_DDRTIMINGC0 0x18
#define MSCH_DEVTODEV0 0x1c
#define MSCH_DDRMODE 0x110
#define MSCH_AGINGX0 0x1000
#define CIC_CTRL0 0x0
#define CIC_CTRL1 0x4
#define CIC_IDLE_TH 0x8
#define CIC_CG_WAIT_TH 0xc
#define CIC_STATUS0 0x10
#define CIC_STATUS1 0x14
#define CIC_CTRL2 0x18
#define CIC_CTRL3 0x1c
#define CIC_CTRL4 0x20
/* DENALI_CTL_00 */
#define START 1
/* DENALI_CTL_68 */
#define PWRUP_SREFRESH_EXIT (1 << 16)
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
#define PHY_DRV_ODT_Hi_Z 0x0
#define PHY_DRV_ODT_240 0x1
#define PHY_DRV_ODT_120 0x8
#define PHY_DRV_ODT_80 0x9
#define PHY_DRV_ODT_60 0xc
#define PHY_DRV_ODT_48 0xd
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
/*
* sys_reg bitfield struct
* [31] row_3_4_ch1
* [30] row_3_4_ch0
* [29:28] chinfo
* [27] rank_ch1
* [26:25] col_ch1
* [24] bk_ch1
* [23:22] cs0_row_ch1
* [21:20] cs1_row_ch1
* [19:18] bw_ch1
* [17:16] dbw_ch1;
* [15:13] ddrtype
* [12] channelnum
* [11] rank_ch0
* [10:9] col_ch0
* [8] bk_ch0
* [7:6] cs0_row_ch0
* [5:4] cs1_row_ch0
* [3:2] bw_ch0
* [1:0] dbw_ch0
*/
#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1)
#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
#define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1)
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7)
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1))
#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16))
#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1))
#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16))
#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16))
#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1))
#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + (ch) * 16))
#define SYS_REG_DEC_CS0_ROW(n, ch) (13 + (((n) >> (6 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + (ch) * 16))
#define SYS_REG_DEC_CS1_ROW(n, ch) (13 + (((n) >> (4 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16))
#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + (ch) * 16))
#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + (ch) * 16)) & 0x3))
#define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \
(0x1f<<(10+16))|((n)<<10))
#define CTL_REG_NUM 332
#define PHY_REG_NUM 959
#define PI_REG_NUM 200
enum {
DDR3 = 3,
LPDDR2 = 5,
......
plat/rockchip/rk3399/drivers/m0/include/addressmap.h 0 → 100644
View file @ 1830f790
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ROCKCHIP_RK3399_M0_INCLUDE_SHARED_ADDRESSMAP_H__
#define __ROCKCHIP_RK3399_M0_INCLUDE_SHARED_ADDRESSMAP_H__
#include <addressmap_shared.h>
/* Registers base address for M0 */
#define MMIO_BASE 0x40000000
#endif /* __ROCKCHIP_RK3399_M0_INCLUDE_SHARED_ADDRESSMAP_H__ */
plat/rockchip/rk3399/drivers/m0/include/rk3399_mcu.h
View file @ 1830f790
......@@ -31,6 +31,8 @@
#ifndef __RK3399_MCU_H__
#define __RK3399_MCU_H__
#include <addressmap.h>
typedef unsigned int uint32_t;
#define mmio_read_32(c) ({unsigned int __v = \
......@@ -44,18 +46,6 @@ typedef unsigned int uint32_t;
#define mmio_clrsetbits_32(addr, clear, set) \
mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
#define MIN(a, b) ((a) < (b) ? (a) : (b))
#define MAX(a, b) ((a) > (b) ? (a) : (b))
#define MCU_BASE 0x40000000
#define PMU_BASE (MCU_BASE + 0x07310000)
#define CRU_BASE_ADDR 0x47760000
#define GRF_BASE_ADDR 0x47770000
#define PMU_CRU_BASE_ADDR 0x47750000
#define VOP_LITE_BASE_ADDR 0x478F0000
#define VOP_BIG_BASE_ADDR 0x47900000
#define CIC_BASE_ADDR 0x47620000
void handle_suspend(void);
void handle_dram(void);
void stopwatch_init_usecs_expire(unsigned int usecs);
......
plat/rockchip/rk3399/drivers/m0/src/dram.c
View file @ 1830f790
......@@ -28,106 +28,71 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <dram_regs.h>
#include <m0_param.h>
#include <pmu_bits.h>
#include <pmu_regs.h>
#include "misc_regs.h"
#include "rk3399_mcu.h"
/* PMU */
#define PMU_PWRDN_ST 0x18
#define PMU_BUS_IDLE_REQ 0x60
#define PMU_BUS_IDLE_ST 0x64
#define PMU_NOC_AUTO_ENA 0xd8
/* PMU_BUS_IDLE_REQ */
#define IDLE_REQ_MSCH1 (1 << 19)
#define IDLE_REQ_MSCH0 (1 << 18)
/* #define PMU_BUS_IDLE_ST */
#define IDLE_MSCH1 (1 << 19)
#define IDLE_MSCH0 (1 << 18)
/* CRU */
#define CRU_DPLL_CON0 0x40
#define CRU_DPLL_CON1 0x44
#define CRU_DPLL_CON2 0x48
#define CRU_DPLL_CON3 0x4c
#define CRU_DPLL_CON4 0x50
#define CRU_DPLL_CON5 0x54
#define CRU_DPLL_CON2 0x48
#define CRU_DPLL_CON3 0x4c
#define CRU_CLKGATE10_CON 0x328
#define CRU_CLKGATE28_CON 0x370
/* CRU_PLL_CON3 */
#define PLL_SLOW_MODE 0
#define PLL_NORMAL_MODE 1
#define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8))
#define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0))
/* PMU CRU */
#define PMU_CRU_GATEDIS_CON0 0x130
/* CIC */
#define CIC_CTRL0 0
#define CIC_CTRL1 0x4
#define CIC_STATUS0 0x10
uint32_t gatedis_con0;
static uint32_t gatedis_con0;
static void idle_port(void)
{
gatedis_con0 = mmio_read_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0);
mmio_write_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0, 0x3fffffff);
gatedis_con0 = mmio_read_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0);
mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, 0x3fffffff);
mmio_setbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
IDLE_REQ_MSCH0 | IDLE_REQ_MSCH1);
(1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1));
while ((mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) &
(IDLE_MSCH1 | IDLE_MSCH0)) != (IDLE_MSCH1 | IDLE_MSCH0))
((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0))) !=
((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0)))
continue;
}
static void deidle_port(void)
{
mmio_clrbits_32(PMU_BASE + PMU_BUS_IDLE_REQ,
IDLE_REQ_MSCH0 | IDLE_REQ_MSCH1);
(1 << PMU_IDLE_REQ_MSCH0) | (1 << PMU_IDLE_REQ_MSCH1));
while (mmio_read_32(PMU_BASE + PMU_BUS_IDLE_ST) &
(IDLE_MSCH1 | IDLE_MSCH0))
((1 << PMU_IDLE_ST_MSCH1) | (1 << PMU_IDLE_ST_MSCH0)))
continue;
/* document is wrong, PMU_CRU_GATEDIS_CON0 do not need set MASK BIT */
mmio_write_32(PMU_CRU_BASE_ADDR + PMU_CRU_GATEDIS_CON0, gatedis_con0);
mmio_write_32(PMUCRU_BASE + PMU_CRU_GATEDIS_CON0, gatedis_con0);
}
static void ddr_set_pll(void)
{
mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE));
mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_SLOW_MODE));
mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_POWER_DOWN(1));
mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON0,
mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(1));
mmio_write_32(CRU_BASE + CRU_DPLL_CON0,
mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON0));
mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON1,
mmio_write_32(CRU_BASE + CRU_DPLL_CON1,
mmio_read_32(PARAM_ADDR + PARAM_DPLL_CON1));
mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_POWER_DOWN(0));
mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_POWER_DOWN(0));
while ((mmio_read_32(CRU_BASE_ADDR + CRU_DPLL_CON2) & (1u << 31)) == 0)
while ((mmio_read_32(CRU_BASE + CRU_DPLL_CON2) & (1u << 31)) == 0)
continue;
mmio_write_32(CRU_BASE_ADDR + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE));
mmio_write_32(CRU_BASE + CRU_DPLL_CON3, PLL_MODE(PLL_NORMAL_MODE));
}
void handle_dram(void)
{
idle_port();
mmio_write_32(CIC_BASE_ADDR + CIC_CTRL0,
mmio_write_32(CIC_BASE + CIC_CTRL0,
(((0x3 << 4) | (1 << 2) | 1) << 16) |
(1 << 2) | 1 |
mmio_read_32(PARAM_ADDR + PARAM_FREQ_SELECT));
while ((mmio_read_32(CIC_BASE_ADDR + CIC_STATUS0) & (1 << 2)) == 0)
while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 2)) == 0)
continue;
ddr_set_pll();
mmio_write_32(CIC_BASE_ADDR + CIC_CTRL0, 0x20002);
while ((mmio_read_32(CIC_BASE_ADDR + CIC_STATUS0) & (1 << 0)) == 0)
mmio_write_32(CIC_BASE + CIC_CTRL0, 0x20002);
while ((mmio_read_32(CIC_BASE + CIC_STATUS0) & (1 << 0)) == 0)
continue;
deidle_port();
......
plat/rockchip/rk3399/drivers/m0/src/suspend.c
View file @ 1830f790
......@@ -28,11 +28,9 @@
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <pmu_regs.h>
#include "rk3399_mcu.h"
#define PMU_PWRMODE_CON 0x20
#define PMU_POWER_ST 0x78
#define M0_SCR 0xe000ed10 /* System Control Register (SCR) */
#define SCR_SLEEPDEEP_SHIFT (1 << 2)
......
plat/rockchip/rk3399/drivers/pmu/pmu.h
View file @ 1830f790
......@@ -31,6 +31,7 @@
#ifndef __PMU_H__
#define __PMU_H__
#include <pmu_bits.h>
#include <pmu_regs.h>
#include <soc.h>
......@@ -67,693 +68,6 @@ enum pmu_core_pwrst_shift {
#define CKECK_WFI_MSK 0x10
#define CKECK_WFEI_MSK 0x11
enum pmu_powerdomain_id {
PD_CPUL0 = 0,
PD_CPUL1,
PD_CPUL2,
PD_CPUL3,
PD_CPUB0,
PD_CPUB1,
PD_SCUL,
PD_SCUB,
PD_TCPD0,
PD_TCPD1,
PD_CCI,
PD_PERILP,
PD_PERIHP,
PD_CENTER,
PD_VIO,
PD_GPU,
PD_VCODEC,
PD_VDU,
PD_RGA,
PD_IEP,
PD_VO,
PD_ISP0 = 22,
PD_ISP1,
PD_HDCP,
PD_GMAC,
PD_EMMC,
PD_USB3,
PD_EDP,
PD_GIC,
PD_SD,
PD_SDIOAUDIO,
PD_END
};
enum powerdomain_state {
PMU_POWER_ON = 0,
PMU_POWER_OFF,
};
enum pmu_bus_id {
BUS_ID_GPU = 0,
BUS_ID_PERILP,
BUS_ID_PERIHP,
BUS_ID_VCODEC,
BUS_ID_VDU,
BUS_ID_RGA,
BUS_ID_IEP,
BUS_ID_VOPB,
BUS_ID_VOPL,
BUS_ID_ISP0,
BUS_ID_ISP1,
BUS_ID_HDCP,
BUS_ID_USB3,
BUS_ID_PERILPM0,
BUS_ID_CENTER,
BUS_ID_CCIM0,
BUS_ID_CCIM1,
BUS_ID_VIO,
BUS_ID_MSCH0,
BUS_ID_MSCH1,
BUS_ID_ALIVE,
BUS_ID_PMU,
BUS_ID_EDP,
BUS_ID_GMAC,
BUS_ID_EMMC,
BUS_ID_CENTER1,
BUS_ID_PMUM0,
BUS_ID_GIC,
BUS_ID_SD,
BUS_ID_SDIOAUDIO,
};
enum pmu_bus_state {
BUS_ACTIVE,
BUS_IDLE,
};
/* pmu_cpuapm bit */
enum pmu_cores_pm_by_wfi {
core_pm_en = 0,
core_pm_int_wakeup_en,
core_pm_resv,
core_pm_sft_wakeup_en
};
enum pmu_wkup_cfg0 {
PMU_GPIO0A_POSE_WKUP_EN = 0,
PMU_GPIO0B_POSE_WKUP_EN = 8,
PMU_GPIO0C_POSE_WKUP_EN = 16,
PMU_GPIO0D_POSE_WKUP_EN = 24,
};
enum pmu_wkup_cfg1 {
PMU_GPIO0A_NEGEDGE_WKUP_EN = 0,
PMU_GPIO0B_NEGEDGE_WKUP_EN = 7,
PMU_GPIO0C_NEGEDGE_WKUP_EN = 16,
PMU_GPIO0D_NEGEDGE_WKUP_EN = 24,
};
enum pmu_wkup_cfg2 {
PMU_GPIO1A_POSE_WKUP_EN = 0,
PMU_GPIO1B_POSE_WKUP_EN = 7,
PMU_GPIO1C_POSE_WKUP_EN = 16,
PMU_GPIO1D_POSE_WKUP_EN = 24,
};
enum pmu_wkup_cfg3 {
PMU_GPIO1A_NEGEDGE_WKUP_EN = 0,
PMU_GPIO1B_NEGEDGE_WKUP_EN = 7,
PMU_GPIO1C_NEGEDGE_WKUP_EN = 16,
PMU_GPIO1D_NEGEDGE_WKUP_EN = 24,
};
/* pmu_wkup_cfg4 */
enum pmu_wkup_cfg4 {
PMU_CLUSTER_L_WKUP_EN = 0,
PMU_CLUSTER_B_WKUP_EN,
PMU_GPIO_WKUP_EN,
PMU_SDIO_WKUP_EN,
PMU_SDMMC_WKUP_EN,
PMU_TIMER_WKUP_EN = 6,
PMU_USBDEV_WKUP_EN,
PMU_SFT_WKUP_EN,
PMU_M0_WDT_WKUP_EN,
PMU_TIMEOUT_WKUP_EN,
PMU_PWM_WKUP_EN,
PMU_PCIE_WKUP_EN = 13,
};
enum pmu_pwrdn_con {
PMU_A53_L0_PWRDWN_EN = 0,
PMU_A53_L1_PWRDWN_EN,
PMU_A53_L2_PWRDWN_EN,
PMU_A53_L3_PWRDWN_EN,
PMU_A72_B0_PWRDWN_EN,
PMU_A72_B1_PWRDWN_EN,
PMU_SCU_L_PWRDWN_EN,
PMU_SCU_B_PWRDWN_EN,
PMU_TCPD0_PWRDWN_EN,
PMU_TCPD1_PWRDWN_EN,
PMU_CCI_PWRDWN_EN,
PMU_PERILP_PWRDWN_EN,
PMU_PERIHP_PWRDWN_EN,
PMU_CENTER_PWRDWN_EN,
PMU_VIO_PWRDWN_EN,
PMU_GPU_PWRDWN_EN,
PMU_VCODEC_PWRDWN_EN,
PMU_VDU_PWRDWN_EN,
PMU_RGA_PWRDWN_EN,
PMU_IEP_PWRDWN_EN,
PMU_VO_PWRDWN_EN,
PMU_ISP0_PWRDWN_EN = 22,
PMU_ISP1_PWRDWN_EN,
PMU_HDCP_PWRDWN_EN,
PMU_GMAC_PWRDWN_EN,
PMU_EMMC_PWRDWN_EN,
PMU_USB3_PWRDWN_EN,
PMU_EDP_PWRDWN_EN,
PMU_GIC_PWRDWN_EN,
PMU_SD_PWRDWN_EN,
PMU_SDIOAUDIO_PWRDWN_EN,
};
enum pmu_pwrdn_st {
PMU_A53_L0_PWRDWN_ST = 0,
PMU_A53_L1_PWRDWN_ST,
PMU_A53_L2_PWRDWN_ST,
PMU_A53_L3_PWRDWN_ST,
PMU_A72_B0_PWRDWN_ST,
PMU_A72_B1_PWRDWN_ST,
PMU_SCU_L_PWRDWN_ST,
PMU_SCU_B_PWRDWN_ST,
PMU_TCPD0_PWRDWN_ST,
PMU_TCPD1_PWRDWN_ST,
PMU_CCI_PWRDWN_ST,
PMU_PERILP_PWRDWN_ST,
PMU_PERIHP_PWRDWN_ST,
PMU_CENTER_PWRDWN_ST,
PMU_VIO_PWRDWN_ST,
PMU_GPU_PWRDWN_ST,
PMU_VCODEC_PWRDWN_ST,
PMU_VDU_PWRDWN_ST,
PMU_RGA_PWRDWN_ST,
PMU_IEP_PWRDWN_ST,
PMU_VO_PWRDWN_ST,
PMU_ISP0_PWRDWN_ST = 22,
PMU_ISP1_PWRDWN_ST,
PMU_HDCP_PWRDWN_ST,
PMU_GMAC_PWRDWN_ST,
PMU_EMMC_PWRDWN_ST,
PMU_USB3_PWRDWN_ST,
PMU_EDP_PWRDWN_ST,
PMU_GIC_PWRDWN_ST,
PMU_SD_PWRDWN_ST,
PMU_SDIOAUDIO_PWRDWN_ST,
};
enum pmu_pll_con {
PMU_PLL_PD_CFG = 0,
PMU_SFT_PLL_PD = 8,
};
enum pmu_pwermode_con {
PMU_PWR_MODE_EN = 0,
PMU_WKUP_RST_EN,
PMU_INPUT_CLAMP_EN,
PMU_OSC_DIS,
PMU_ALIVE_USE_LF,
PMU_PMU_USE_LF,
PMU_POWER_OFF_REQ_CFG,
PMU_CHIP_PD_EN,
PMU_PLL_PD_EN,
PMU_CPU0_PD_EN,
PMU_L2_FLUSH_EN,
PMU_L2_IDLE_EN,
PMU_SCU_PD_EN,
PMU_CCI_PD_EN,
PMU_PERILP_PD_EN,
PMU_CENTER_PD_EN,
PMU_SREF0_ENTER_EN,
PMU_DDRC0_GATING_EN,
PMU_DDRIO0_RET_EN,
PMU_DDRIO0_RET_DE_REQ,
PMU_SREF1_ENTER_EN,
PMU_DDRC1_GATING_EN,
PMU_DDRIO1_RET_EN,
PMU_DDRIO1_RET_DE_REQ,
PMU_CLK_CENTER_SRC_GATE_EN = 26,
PMU_CLK_PERILP_SRC_GATE_EN,
PMU_CLK_CORE_SRC_GATE_EN,
PMU_DDRIO_RET_HW_DE_REQ,
PMU_SLP_OUTPUT_CFG,
PMU_MAIN_CLUSTER,
};
enum pmu_sft_con {
PMU_WKUP_SFT = 0,
PMU_INPUT_CLAMP_CFG,
PMU_OSC_DIS_CFG,
PMU_PMU_LF_EN_CFG,
PMU_ALIVE_LF_EN_CFG,
PMU_24M_EN_CFG,
PMU_DBG_PWRUP_L0_CFG,
PMU_WKUP_SFT_M0,
PMU_DDRCTL0_C_SYSREQ_CFG,
PMU_DDR0_IO_RET_CFG,
PMU_DDRCTL1_C_SYSREQ_CFG = 12,
PMU_DDR1_IO_RET_CFG,
DBG_PWRUP_B0_CFG = 15,
DBG_NOPWERDWN_L0_EN,
DBG_NOPWERDWN_L1_EN,
DBG_NOPWERDWN_L2_EN,
DBG_NOPWERDWN_L3_EN,
DBG_PWRUP_REQ_L_EN = 20,
CLUSTER_L_CLK_SRC_GATING_CFG,
L2_FLUSH_REQ_CLUSTER_L,
ACINACTM_CLUSTER_L_CFG,
DBG_NO_PWERDWN_B0_EN,
DBG_NO_PWERDWN_B1_EN,
DBG_PWRUP_REQ_B_EN = 28,
CLUSTER_B_CLK_SRC_GATING_CFG,
L2_FLUSH_REQ_CLUSTER_B,
ACINACTM_CLUSTER_B_CFG,
};
enum pmu_int_con {
PMU_PMU_INT_EN = 0,
PMU_PWRMD_WKUP_INT_EN,
PMU_WKUP_GPIO0_NEG_INT_EN,
PMU_WKUP_GPIO0_POS_INT_EN,
PMU_WKUP_GPIO1_NEG_INT_EN,
PMU_WKUP_GPIO1_POS_INT_EN,
};
enum pmu_int_st {
PMU_PWRMD_WKUP_INT_ST = 1,
PMU_WKUP_GPIO0_NEG_INT_ST,
PMU_WKUP_GPIO0_POS_INT_ST,
PMU_WKUP_GPIO1_NEG_INT_ST,
PMU_WKUP_GPIO1_POS_INT_ST,
};
enum pmu_gpio0_pos_int_con {
PMU_GPIO0A_POS_INT_EN = 0,
PMU_GPIO0B_POS_INT_EN = 8,
PMU_GPIO0C_POS_INT_EN = 16,
PMU_GPIO0D_POS_INT_EN = 24,
};
enum pmu_gpio0_neg_int_con {
PMU_GPIO0A_NEG_INT_EN = 0,
PMU_GPIO0B_NEG_INT_EN = 8,
PMU_GPIO0C_NEG_INT_EN = 16,
PMU_GPIO0D_NEG_INT_EN = 24,
};
enum pmu_gpio1_pos_int_con {
PMU_GPIO1A_POS_INT_EN = 0,
PMU_GPIO1B_POS_INT_EN = 8,
PMU_GPIO1C_POS_INT_EN = 16,
PMU_GPIO1D_POS_INT_EN = 24,
};
enum pmu_gpio1_neg_int_con {
PMU_GPIO1A_NEG_INT_EN = 0,
PMU_GPIO1B_NEG_INT_EN = 8,
PMU_GPIO1C_NEG_INT_EN = 16,
PMU_GPIO1D_NEG_INT_EN = 24,
};
enum pmu_gpio0_pos_int_st {
PMU_GPIO0A_POS_INT_ST = 0,
PMU_GPIO0B_POS_INT_ST = 8,
PMU_GPIO0C_POS_INT_ST = 16,
PMU_GPIO0D_POS_INT_ST = 24,
};
enum pmu_gpio0_neg_int_st {
PMU_GPIO0A_NEG_INT_ST = 0,
PMU_GPIO0B_NEG_INT_ST = 8,
PMU_GPIO0C_NEG_INT_ST = 16,
PMU_GPIO0D_NEG_INT_ST = 24,
};
enum pmu_gpio1_pos_int_st {
PMU_GPIO1A_POS_INT_ST = 0,
PMU_GPIO1B_POS_INT_ST = 8,
PMU_GPIO1C_POS_INT_ST = 16,
PMU_GPIO1D_POS_INT_ST = 24,
};
enum pmu_gpio1_neg_int_st {
PMU_GPIO1A_NEG_INT_ST = 0,
PMU_GPIO1B_NEG_INT_ST = 8,
PMU_GPIO1C_NEG_INT_ST = 16,
PMU_GPIO1D_NEG_INT_ST = 24,
};
/* pmu power down configure register 0x0050 */
enum pmu_pwrdn_inten {
PMU_A53_L0_PWR_SWITCH_INT_EN = 0,
PMU_A53_L1_PWR_SWITCH_INT_EN,
PMU_A53_L2_PWR_SWITCH_INT_EN,
PMU_A53_L3_PWR_SWITCH_INT_EN,
PMU_A72_B0_PWR_SWITCH_INT_EN,
PMU_A72_B1_PWR_SWITCH_INT_EN,
PMU_SCU_L_PWR_SWITCH_INT_EN,
PMU_SCU_B_PWR_SWITCH_INT_EN,
PMU_TCPD0_PWR_SWITCH_INT_EN,
PMU_TCPD1_PWR_SWITCH_INT_EN,
PMU_CCI_PWR_SWITCH_INT_EN,
PMU_PERILP_PWR_SWITCH_INT_EN,
PMU_PERIHP_PWR_SWITCH_INT_EN,
PMU_CENTER_PWR_SWITCH_INT_EN,
PMU_VIO_PWR_SWITCH_INT_EN,
PMU_GPU_PWR_SWITCH_INT_EN,
PMU_VCODEC_PWR_SWITCH_INT_EN,
PMU_VDU_PWR_SWITCH_INT_EN,
PMU_RGA_PWR_SWITCH_INT_EN,
PMU_IEP_PWR_SWITCH_INT_EN,
PMU_VO_PWR_SWITCH_INT_EN,
PMU_ISP0_PWR_SWITCH_INT_EN = 22,
PMU_ISP1_PWR_SWITCH_INT_EN,
PMU_HDCP_PWR_SWITCH_INT_EN,
PMU_GMAC_PWR_SWITCH_INT_EN,
PMU_EMMC_PWR_SWITCH_INT_EN,
PMU_USB3_PWR_SWITCH_INT_EN,
PMU_EDP_PWR_SWITCH_INT_EN,
PMU_GIC_PWR_SWITCH_INT_EN,
PMU_SD_PWR_SWITCH_INT_EN,
PMU_SDIOAUDIO_PWR_SWITCH_INT_EN,
};
enum pmu_wkup_status {
PMU_WKUP_BY_CLSTER_L_INT = 0,
PMU_WKUP_BY_CLSTER_b_INT,
PMU_WKUP_BY_GPIO_INT,
PMU_WKUP_BY_SDIO_DET,
PMU_WKUP_BY_SDMMC_DET,
PMU_WKUP_BY_TIMER = 6,
PMU_WKUP_BY_USBDEV_DET,
PMU_WKUP_BY_M0_SFT,
PMU_WKUP_BY_M0_WDT_INT,
PMU_WKUP_BY_TIMEOUT,
PMU_WKUP_BY_PWM,
PMU_WKUP_BY_PCIE = 13,
};
enum pmu_bus_clr {
PMU_CLR_GPU = 0,
PMU_CLR_PERILP,
PMU_CLR_PERIHP,
PMU_CLR_VCODEC,
PMU_CLR_VDU,
PMU_CLR_RGA,
PMU_CLR_IEP,
PMU_CLR_VOPB,
PMU_CLR_VOPL,
PMU_CLR_ISP0,
PMU_CLR_ISP1,
PMU_CLR_HDCP,
PMU_CLR_USB3,
PMU_CLR_PERILPM0,
PMU_CLR_CENTER,
PMU_CLR_CCIM1,
PMU_CLR_CCIM0,
PMU_CLR_VIO,
PMU_CLR_MSCH0,
PMU_CLR_MSCH1,
PMU_CLR_ALIVE,
PMU_CLR_PMU,
PMU_CLR_EDP,
PMU_CLR_GMAC,
PMU_CLR_EMMC,
PMU_CLR_CENTER1,
PMU_CLR_PMUM0,
PMU_CLR_GIC,
PMU_CLR_SD,
PMU_CLR_SDIOAUDIO,
};
/* PMU bus idle request register */
enum pmu_bus_idle_req {
PMU_IDLE_REQ_GPU = 0,
PMU_IDLE_REQ_PERILP,
PMU_IDLE_REQ_PERIHP,
PMU_IDLE_REQ_VCODEC,
PMU_IDLE_REQ_VDU,
PMU_IDLE_REQ_RGA,
PMU_IDLE_REQ_IEP,
PMU_IDLE_REQ_VOPB,
PMU_IDLE_REQ_VOPL,
PMU_IDLE_REQ_ISP0,
PMU_IDLE_REQ_ISP1,
PMU_IDLE_REQ_HDCP,
PMU_IDLE_REQ_USB3,
PMU_IDLE_REQ_PERILPM0,
PMU_IDLE_REQ_CENTER,
PMU_IDLE_REQ_CCIM0,
PMU_IDLE_REQ_CCIM1,
PMU_IDLE_REQ_VIO,
PMU_IDLE_REQ_MSCH0,
PMU_IDLE_REQ_MSCH1,
PMU_IDLE_REQ_ALIVE,
PMU_IDLE_REQ_PMU,
PMU_IDLE_REQ_EDP,
PMU_IDLE_REQ_GMAC,
PMU_IDLE_REQ_EMMC,
PMU_IDLE_REQ_CENTER1,
PMU_IDLE_REQ_PMUM0,
PMU_IDLE_REQ_GIC,
PMU_IDLE_REQ_SD,
PMU_IDLE_REQ_SDIOAUDIO,
};
/* pmu bus idle status register */
enum pmu_bus_idle_st {
PMU_IDLE_ST_GPU = 0,
PMU_IDLE_ST_PERILP,
PMU_IDLE_ST_PERIHP,
PMU_IDLE_ST_VCODEC,
PMU_IDLE_ST_VDU,
PMU_IDLE_ST_RGA,
PMU_IDLE_ST_IEP,
PMU_IDLE_ST_VOPB,
PMU_IDLE_ST_VOPL,
PMU_IDLE_ST_ISP0,
PMU_IDLE_ST_ISP1,
PMU_IDLE_ST_HDCP,
PMU_IDLE_ST_USB3,
PMU_IDLE_ST_PERILPM0,
PMU_IDLE_ST_CENTER,
PMU_IDLE_ST_CCIM0,
PMU_IDLE_ST_CCIM1,
PMU_IDLE_ST_VIO,
PMU_IDLE_ST_MSCH0,
PMU_IDLE_ST_MSCH1,
PMU_IDLE_ST_ALIVE,
PMU_IDLE_ST_PMU,
PMU_IDLE_ST_EDP,
PMU_IDLE_ST_GMAC,
PMU_IDLE_ST_EMMC,
PMU_IDLE_ST_CENTER1,
PMU_IDLE_ST_PMUM0,
PMU_IDLE_ST_GIC,
PMU_IDLE_ST_SD,
PMU_IDLE_ST_SDIOAUDIO,
};
enum pmu_bus_idle_ack {
PMU_IDLE_ACK_GPU = 0,
PMU_IDLE_ACK_PERILP,
PMU_IDLE_ACK_PERIHP,
PMU_IDLE_ACK_VCODEC,
PMU_IDLE_ACK_VDU,
PMU_IDLE_ACK_RGA,
PMU_IDLE_ACK_IEP,
PMU_IDLE_ACK_VOPB,
PMU_IDLE_ACK_VOPL,
PMU_IDLE_ACK_ISP0,
PMU_IDLE_ACK_ISP1,
PMU_IDLE_ACK_HDCP,
PMU_IDLE_ACK_USB3,
PMU_IDLE_ACK_PERILPM0,
PMU_IDLE_ACK_CENTER,
PMU_IDLE_ACK_CCIM0,
PMU_IDLE_ACK_CCIM1,
PMU_IDLE_ACK_VIO,
PMU_IDLE_ACK_MSCH0,
PMU_IDLE_ACK_MSCH1,
PMU_IDLE_ACK_ALIVE,
PMU_IDLE_ACK_PMU,
PMU_IDLE_ACK_EDP,
PMU_IDLE_ACK_GMAC,
PMU_IDLE_ACK_EMMC,
PMU_IDLE_ACK_CENTER1,
PMU_IDLE_ACK_PMUM0,
PMU_IDLE_ACK_GIC,
PMU_IDLE_ACK_SD,
PMU_IDLE_ACK_SDIOAUDIO,
};
enum pmu_cci500_con {
PMU_PREQ_CCI500_CFG_SW = 0,
PMU_CLR_PREQ_CCI500_HW,
PMU_PSTATE_CCI500_0,
PMU_PSTATE_CCI500_1,
PMU_PSTATE_CCI500_2,
PMU_QREQ_CCI500_CFG_SW,
PMU_CLR_QREQ_CCI500_HW,
PMU_QGATING_CCI500_CFG,
PMU_PREQ_CCI500_CFG_SW_WMSK = 16,
PMU_CLR_PREQ_CCI500_HW_WMSK,
PMU_PSTATE_CCI500_0_WMSK,
PMU_PSTATE_CCI500_1_WMSK,
PMU_PSTATE_CCI500_2_WMSK,
PMU_QREQ_CCI500_CFG_SW_WMSK,
PMU_CLR_QREQ_CCI500_HW_WMSK,
PMU_QGATING_CCI500_CFG_WMSK,
};
enum pmu_adb400_con {
PMU_PWRDWN_REQ_CXCS_SW = 0,
PMU_PWRDWN_REQ_CORE_L_SW,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW,
PMU_PWRDWN_REQ_CORE_B_SW,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW,
PMU_CLR_CXCS_HW = 8,
PMU_CLR_CORE_L_HW,
PMU_CLR_CORE_L_2GIC_HW,
PMU_CLR_GIC2_CORE_L_HW,
PMU_CLR_CORE_B_HW,
PMU_CLR_CORE_B_2GIC_HW,
PMU_CLR_GIC2_CORE_B_HW,
PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16,
PMU_PWRDWN_REQ_CORE_L_SW_WMSK,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK,
PMU_PWRDWN_REQ_CORE_B_SW_WMSK,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK,
PMU_CLR_CXCS_HW_WMSK = 24,
PMU_CLR_CORE_L_HW_WMSK,
PMU_CLR_CORE_L_2GIC_HW_WMSK,
PMU_CLR_GIC2_CORE_L_HW_WMSK,
PMU_CLR_CORE_B_HW_WMSK,
PMU_CLR_CORE_B_2GIC_HW_WMSK,
PMU_CLR_GIC2_CORE_B_HW_WMSK,
};
enum pmu_adb400_st {
PMU_PWRDWN_REQ_CXCS_SW_ST = 0,
PMU_PWRDWN_REQ_CORE_L_SW_ST,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST,
PMU_PWRDWN_REQ_CORE_B_SW_ST,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST,
PMU_CLR_CXCS_HW_ST = 8,
PMU_CLR_CORE_L_HW_ST,
PMU_CLR_CORE_L_2GIC_HW_ST,
PMU_CLR_GIC2_CORE_L_HW_ST,
PMU_CLR_CORE_B_HW_ST,
PMU_CLR_CORE_B_2GIC_HW_ST,
PMU_CLR_GIC2_CORE_B_HW_ST,
};
enum pmu_pwrdn_con1 {
PMU_VD_SCU_L_PWRDN_EN = 0,
PMU_VD_SCU_B_PWRDN_EN,
PMU_VD_CENTER_PWRDN_EN,
};
enum pmu_core_pwr_st {
L2_FLUSHDONE_CLUSTER_L = 0,
STANDBY_BY_WFIL2_CLUSTER_L,
L2_FLUSHDONE_CLUSTER_B = 10,
STANDBY_BY_WFIL2_CLUSTER_B,
};
/* Specific features required */
#define AP_PWROFF 0x0a
......
plat/rockchip/rk3399/drivers/soc/soc.c
View file @ 1830f790
......@@ -42,7 +42,7 @@
/* Table of regions to map using the MMU. */
const mmap_region_t plat_rk_mmap[] = {
MAP_REGION_FLAT(RK3399_DEV_RNG0_BASE, RK3399_DEV_RNG0_SIZE,
MAP_REGION_FLAT(DEV_RNG0_BASE, DEV_RNG0_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(PMUSRAM_BASE, PMUSRAM_SIZE,
MT_MEMORY | MT_RW | MT_SECURE),
......
plat/rockchip/rk3399/include/addressmap.h 0 → 100644
View file @ 1830f790
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ROCKCHIP_RK3399_INCLUDE_ADDRESSMAP_H__
#define __ROCKCHIP_RK3399_INCLUDE_ADDRESSMAP_H__
#include <addressmap_shared.h>
/* Registers base address */
#define MMIO_BASE 0xF8000000
/* Aggregate of all devices in the first GB */
#define DEV_RNG0_BASE MMIO_BASE
#define DEV_RNG0_SIZE SIZE_M(125)
#endif /* __ROCKCHIP_RK3399_INCLUDE_ADDRESSMAP_H__ */
plat/rockchip/rk3399/include/platform_def.h
View file @ 1830f790
......@@ -138,7 +138,7 @@
#define PLAT_RK_G1S_IRQS RK3399_G1S_IRQS
#define PLAT_RK_G0_IRQS RK3399_G0_IRQS
#define PLAT_RK_UART_BASE RK3399_UART2_BASE
#define PLAT_RK_UART_BASE UART2_BASE
#define PLAT_RK_UART_CLOCK RK3399_UART_CLOCK
#define PLAT_RK_UART_BAUDRATE RK3399_BAUDRATE
......
plat/rockchip/rk3399/include/shared/addressmap_shared.h 0 → 100644
View file @ 1830f790
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__
#define __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__
#define SIZE_K(n) ((n) * 1024)
#define SIZE_M(n) ((n) * 1024 * 1024)
/*
* The parts of the shared defined registers address with AP and M0,
* let's note and mark the previous defines like this:
*/
#define GIC500_BASE (MMIO_BASE + 0x06E00000)
#define UART0_BASE (MMIO_BASE + 0x07180000)
#define UART1_BASE (MMIO_BASE + 0x07190000)
#define UART2_BASE (MMIO_BASE + 0x071A0000)
#define UART3_BASE (MMIO_BASE + 0x071B0000)
#define PMU_BASE (MMIO_BASE + 0x07310000)
#define PMUGRF_BASE (MMIO_BASE + 0x07320000)
#define SGRF_BASE (MMIO_BASE + 0x07330000)
#define PMUSRAM_BASE (MMIO_BASE + 0x073B0000)
#define PWM_BASE (MMIO_BASE + 0x07420000)
#define CIC_BASE (MMIO_BASE + 0x07620000)
#define PD_BUS0_BASE (MMIO_BASE + 0x07650000)
#define DCF_BASE (MMIO_BASE + 0x076A0000)
#define GPIO0_BASE (MMIO_BASE + 0x07720000)
#define GPIO1_BASE (MMIO_BASE + 0x07730000)
#define PMUCRU_BASE (MMIO_BASE + 0x07750000)
#define CRU_BASE (MMIO_BASE + 0x07760000)
#define GRF_BASE (MMIO_BASE + 0x07770000)
#define GPIO2_BASE (MMIO_BASE + 0x07780000)
#define GPIO3_BASE (MMIO_BASE + 0x07788000)
#define GPIO4_BASE (MMIO_BASE + 0x07790000)
#define STIME_BASE (MMIO_BASE + 0x07860000)
#define SRAM_BASE (MMIO_BASE + 0x078C0000)
#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x07A50000)
#define DDRC0_BASE (MMIO_BASE + 0x07A80000)
#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x07A84000)
#define DDRC1_BASE (MMIO_BASE + 0x07A88000)
#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x07A8C000)
#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x07A90000)
#define CCI500_BASE (MMIO_BASE + 0x07B00000)
#define COLD_BOOT_BASE (MMIO_BASE + 0x07FF0000)
/* Registers size */
#define GIC500_SIZE SIZE_M(2)
#define UART0_SIZE SIZE_K(64)
#define UART1_SIZE SIZE_K(64)
#define UART2_SIZE SIZE_K(64)
#define UART3_SIZE SIZE_K(64)
#define PMU_SIZE SIZE_K(64)
#define PMUGRF_SIZE SIZE_K(64)
#define SGRF_SIZE SIZE_K(64)
#define PMUSRAM_SIZE SIZE_K(64)
#define PMUSRAM_RSIZE SIZE_K(8)
#define PWM_SIZE SIZE_K(64)
#define CIC_SIZE SIZE_K(4)
#define DCF_SIZE SIZE_K(4)
#define GPIO0_SIZE SIZE_K(64)
#define GPIO1_SIZE SIZE_K(64)
#define PMUCRU_SIZE SIZE_K(64)
#define CRU_SIZE SIZE_K(64)
#define GRF_SIZE SIZE_K(64)
#define GPIO2_SIZE SIZE_K(32)
#define GPIO3_SIZE SIZE_K(32)
#define GPIO4_SIZE SIZE_K(32)
#define STIME_SIZE SIZE_K(64)
#define SRAM_SIZE SIZE_K(192)
#define SERVICE_NOC_0_SIZE SIZE_K(192)
#define DDRC0_SIZE SIZE_K(32)
#define SERVICE_NOC_1_SIZE SIZE_K(16)
#define DDRC1_SIZE SIZE_K(32)
#define SERVICE_NOC_2_SIZE SIZE_K(16)
#define SERVICE_NOC_3_SIZE SIZE_K(448)
#define CCI500_SIZE SIZE_M(1)
#define PD_BUS0_SIZE SIZE_K(448)
/* DDR Registers address */
#define CTL_BASE(ch) (DDRC0_BASE + (ch) * 0x8000)
#define CTL_REG(ch, n) (CTL_BASE(ch) + (n) * 0x4)
#define PI_OFFSET 0x800
#define PI_BASE(ch) (CTL_BASE(ch) + PI_OFFSET)
#define PI_REG(ch, n) (PI_BASE(ch) + (n) * 0x4)
#define PHY_OFFSET 0x2000
#define PHY_BASE(ch) (CTL_BASE(ch) + PHY_OFFSET)
#define PHY_REG(ch, n) (PHY_BASE(ch) + (n) * 0x4)
#define MSCH_BASE(ch) (SERVICE_NOC_1_BASE + (ch) * 0x8000)
#endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_ADDRESSMAP_SHARED_H__ */
plat/rockchip/rk3399/include/shared/dram_regs.h 0 → 100644
View file @ 1830f790
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __DRAM_REGS_H__
#define __DRAM_REGS_H__
#define CTL_REG_NUM 332
#define PHY_REG_NUM 959
#define PI_REG_NUM 200
#define MSCH_ID_COREID 0x0
#define MSCH_ID_REVISIONID 0x4
#define MSCH_DEVICECONF 0x8
#define MSCH_DEVICESIZE 0xc
#define MSCH_DDRTIMINGA0 0x10
#define MSCH_DDRTIMINGB0 0x14
#define MSCH_DDRTIMINGC0 0x18
#define MSCH_DEVTODEV0 0x1c
#define MSCH_DDRMODE 0x110
#define MSCH_AGINGX0 0x1000
#define CIC_CTRL0 0x0
#define CIC_CTRL1 0x4
#define CIC_IDLE_TH 0x8
#define CIC_CG_WAIT_TH 0xc
#define CIC_STATUS0 0x10
#define CIC_STATUS1 0x14
#define CIC_CTRL2 0x18
#define CIC_CTRL3 0x1c
#define CIC_CTRL4 0x20
/* DENALI_CTL_00 */
#define START 1
/* DENALI_CTL_68 */
#define PWRUP_SREFRESH_EXIT (1 << 16)
/* DENALI_CTL_274 */
#define MEM_RST_VALID 1
#define PHY_DRV_ODT_Hi_Z 0x0
#define PHY_DRV_ODT_240 0x1
#define PHY_DRV_ODT_120 0x8
#define PHY_DRV_ODT_80 0x9
#define PHY_DRV_ODT_60 0xc
#define PHY_DRV_ODT_48 0xd
#define PHY_DRV_ODT_40 0xe
#define PHY_DRV_ODT_34_3 0xf
/*
* sys_reg bitfield struct
* [31] row_3_4_ch1
* [30] row_3_4_ch0
* [29:28] chinfo
* [27] rank_ch1
* [26:25] col_ch1
* [24] bk_ch1
* [23:22] cs0_row_ch1
* [21:20] cs1_row_ch1
* [19:18] bw_ch1
* [17:16] dbw_ch1;
* [15:13] ddrtype
* [12] channelnum
* [11] rank_ch0
* [10:9] col_ch0
* [8] bk_ch0
* [7:6] cs0_row_ch0
* [5:4] cs1_row_ch0
* [3:2] bw_ch0
* [1:0] dbw_ch0
*/
#define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
#define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1)
#define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
#define SYS_REG_DEC_CHINFO(n, ch) (((n) >> (28 + (ch))) & 0x1)
#define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
#define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7)
#define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
#define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1))
#define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + (ch) * 16))
#define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + (ch) * 16)) & 0x1))
#define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + (ch) * 16))
#define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << (8 + (ch) * 16))
#define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + (ch) * 16)) & 0x1))
#define SYS_REG_ENC_CS0_ROW(n, ch) (((n) - 13) << (6 + (ch) * 16))
#define SYS_REG_DEC_CS0_ROW(n, ch) (13 + (((n) >> (6 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_CS1_ROW(n, ch) (((n) - 13) << (4 + (ch) * 16))
#define SYS_REG_DEC_CS1_ROW(n, ch) (13 + (((n) >> (4 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + (ch) * 16))
#define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + (ch) * 16)) & 0x3))
#define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + (ch) * 16))
#define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + (ch) * 16)) & 0x3))
#define DDR_STRIDE(n) mmio_write_32(SGRF_BASE + SGRF_SOC_CON3_7(4), \
(0x1f<<(10+16))|((n)<<10))
#endif /* __DRAM_REGS_H__ */
plat/rockchip/rk3399/include/shared/misc_regs.h 0 → 100644
View file @ 1830f790
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__
#define __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__
/* CRU */
#define CRU_DPLL_CON0 0x40
#define CRU_DPLL_CON1 0x44
#define CRU_DPLL_CON2 0x48
#define CRU_DPLL_CON3 0x4c
#define CRU_DPLL_CON4 0x50
#define CRU_DPLL_CON5 0x54
/* CRU_PLL_CON3 */
#define PLL_SLOW_MODE 0
#define PLL_NORMAL_MODE 1
#define PLL_MODE(n) ((0x3 << (8 + 16)) | ((n) << 8))
#define PLL_POWER_DOWN(n) ((0x1 << (0 + 16)) | ((n) << 0))
/* PMU CRU */
#define PMU_CRU_GATEDIS_CON0 0x130
#endif /* __ROCKCHIP_RK3399_INCLUDE_SHARED_MISC_REGS_H__ */
plat/rockchip/rk3399/include/shared/pmu_bits.h 0 → 100644
View file @ 1830f790
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#ifndef __PMU_BITS_H__
#define __PMU_BITS_H__
enum pmu_powerdomain_id {
PD_CPUL0 = 0,
PD_CPUL1,
PD_CPUL2,
PD_CPUL3,
PD_CPUB0,
PD_CPUB1,
PD_SCUL,
PD_SCUB,
PD_TCPD0,
PD_TCPD1,
PD_CCI,
PD_PERILP,
PD_PERIHP,
PD_CENTER,
PD_VIO,
PD_GPU,
PD_VCODEC,
PD_VDU,
PD_RGA,
PD_IEP,
PD_VO,
PD_ISP0 = 22,
PD_ISP1,
PD_HDCP,
PD_GMAC,
PD_EMMC,
PD_USB3,
PD_EDP,
PD_GIC,
PD_SD,
PD_SDIOAUDIO,
PD_END
};
enum powerdomain_state {
PMU_POWER_ON = 0,
PMU_POWER_OFF,
};
enum pmu_bus_id {
BUS_ID_GPU = 0,
BUS_ID_PERILP,
BUS_ID_PERIHP,
BUS_ID_VCODEC,
BUS_ID_VDU,
BUS_ID_RGA,
BUS_ID_IEP,
BUS_ID_VOPB,
BUS_ID_VOPL,
BUS_ID_ISP0,
BUS_ID_ISP1,
BUS_ID_HDCP,
BUS_ID_USB3,
BUS_ID_PERILPM0,
BUS_ID_CENTER,
BUS_ID_CCIM0,
BUS_ID_CCIM1,
BUS_ID_VIO,
BUS_ID_MSCH0,
BUS_ID_MSCH1,
BUS_ID_ALIVE,
BUS_ID_PMU,
BUS_ID_EDP,
BUS_ID_GMAC,
BUS_ID_EMMC,
BUS_ID_CENTER1,
BUS_ID_PMUM0,
BUS_ID_GIC,
BUS_ID_SD,
BUS_ID_SDIOAUDIO,
};
enum pmu_bus_state {
BUS_ACTIVE,
BUS_IDLE,
};
/* pmu_cpuapm bit */
enum pmu_cores_pm_by_wfi {
core_pm_en = 0,
core_pm_int_wakeup_en,
core_pm_resv,
core_pm_sft_wakeup_en
};
enum pmu_wkup_cfg0 {
PMU_GPIO0A_POSE_WKUP_EN = 0,
PMU_GPIO0B_POSE_WKUP_EN = 8,
PMU_GPIO0C_POSE_WKUP_EN = 16,
PMU_GPIO0D_POSE_WKUP_EN = 24,
};
enum pmu_wkup_cfg1 {
PMU_GPIO0A_NEGEDGE_WKUP_EN = 0,
PMU_GPIO0B_NEGEDGE_WKUP_EN = 7,
PMU_GPIO0C_NEGEDGE_WKUP_EN = 16,
PMU_GPIO0D_NEGEDGE_WKUP_EN = 24,
};
enum pmu_wkup_cfg2 {
PMU_GPIO1A_POSE_WKUP_EN = 0,
PMU_GPIO1B_POSE_WKUP_EN = 7,
PMU_GPIO1C_POSE_WKUP_EN = 16,
PMU_GPIO1D_POSE_WKUP_EN = 24,
};
enum pmu_wkup_cfg3 {
PMU_GPIO1A_NEGEDGE_WKUP_EN = 0,
PMU_GPIO1B_NEGEDGE_WKUP_EN = 7,
PMU_GPIO1C_NEGEDGE_WKUP_EN = 16,
PMU_GPIO1D_NEGEDGE_WKUP_EN = 24,
};
/* pmu_wkup_cfg4 */
enum pmu_wkup_cfg4 {
PMU_CLUSTER_L_WKUP_EN = 0,
PMU_CLUSTER_B_WKUP_EN,
PMU_GPIO_WKUP_EN,
PMU_SDIO_WKUP_EN,
PMU_SDMMC_WKUP_EN,
PMU_TIMER_WKUP_EN = 6,
PMU_USBDEV_WKUP_EN,
PMU_SFT_WKUP_EN,
PMU_M0_WDT_WKUP_EN,
PMU_TIMEOUT_WKUP_EN,
PMU_PWM_WKUP_EN,
PMU_PCIE_WKUP_EN = 13,
};
enum pmu_pwrdn_con {
PMU_A53_L0_PWRDWN_EN = 0,
PMU_A53_L1_PWRDWN_EN,
PMU_A53_L2_PWRDWN_EN,
PMU_A53_L3_PWRDWN_EN,
PMU_A72_B0_PWRDWN_EN,
PMU_A72_B1_PWRDWN_EN,
PMU_SCU_L_PWRDWN_EN,
PMU_SCU_B_PWRDWN_EN,
PMU_TCPD0_PWRDWN_EN,
PMU_TCPD1_PWRDWN_EN,
PMU_CCI_PWRDWN_EN,
PMU_PERILP_PWRDWN_EN,
PMU_PERIHP_PWRDWN_EN,
PMU_CENTER_PWRDWN_EN,
PMU_VIO_PWRDWN_EN,
PMU_GPU_PWRDWN_EN,
PMU_VCODEC_PWRDWN_EN,
PMU_VDU_PWRDWN_EN,
PMU_RGA_PWRDWN_EN,
PMU_IEP_PWRDWN_EN,
PMU_VO_PWRDWN_EN,
PMU_ISP0_PWRDWN_EN = 22,
PMU_ISP1_PWRDWN_EN,
PMU_HDCP_PWRDWN_EN,
PMU_GMAC_PWRDWN_EN,
PMU_EMMC_PWRDWN_EN,
PMU_USB3_PWRDWN_EN,
PMU_EDP_PWRDWN_EN,
PMU_GIC_PWRDWN_EN,
PMU_SD_PWRDWN_EN,
PMU_SDIOAUDIO_PWRDWN_EN,
};
enum pmu_pwrdn_st {
PMU_A53_L0_PWRDWN_ST = 0,
PMU_A53_L1_PWRDWN_ST,
PMU_A53_L2_PWRDWN_ST,
PMU_A53_L3_PWRDWN_ST,
PMU_A72_B0_PWRDWN_ST,
PMU_A72_B1_PWRDWN_ST,
PMU_SCU_L_PWRDWN_ST,
PMU_SCU_B_PWRDWN_ST,
PMU_TCPD0_PWRDWN_ST,
PMU_TCPD1_PWRDWN_ST,
PMU_CCI_PWRDWN_ST,
PMU_PERILP_PWRDWN_ST,
PMU_PERIHP_PWRDWN_ST,
PMU_CENTER_PWRDWN_ST,
PMU_VIO_PWRDWN_ST,
PMU_GPU_PWRDWN_ST,
PMU_VCODEC_PWRDWN_ST,
PMU_VDU_PWRDWN_ST,
PMU_RGA_PWRDWN_ST,
PMU_IEP_PWRDWN_ST,
PMU_VO_PWRDWN_ST,
PMU_ISP0_PWRDWN_ST = 22,
PMU_ISP1_PWRDWN_ST,
PMU_HDCP_PWRDWN_ST,
PMU_GMAC_PWRDWN_ST,
PMU_EMMC_PWRDWN_ST,
PMU_USB3_PWRDWN_ST,
PMU_EDP_PWRDWN_ST,
PMU_GIC_PWRDWN_ST,
PMU_SD_PWRDWN_ST,
PMU_SDIOAUDIO_PWRDWN_ST,
};
enum pmu_pll_con {
PMU_PLL_PD_CFG = 0,
PMU_SFT_PLL_PD = 8,
};
enum pmu_pwermode_con {
PMU_PWR_MODE_EN = 0,
PMU_WKUP_RST_EN,
PMU_INPUT_CLAMP_EN,
PMU_OSC_DIS,
PMU_ALIVE_USE_LF,
PMU_PMU_USE_LF,
PMU_POWER_OFF_REQ_CFG,
PMU_CHIP_PD_EN,
PMU_PLL_PD_EN,
PMU_CPU0_PD_EN,
PMU_L2_FLUSH_EN,
PMU_L2_IDLE_EN,
PMU_SCU_PD_EN,
PMU_CCI_PD_EN,
PMU_PERILP_PD_EN,
PMU_CENTER_PD_EN,
PMU_SREF0_ENTER_EN,
PMU_DDRC0_GATING_EN,
PMU_DDRIO0_RET_EN,
PMU_DDRIO0_RET_DE_REQ,
PMU_SREF1_ENTER_EN,
PMU_DDRC1_GATING_EN,
PMU_DDRIO1_RET_EN,
PMU_DDRIO1_RET_DE_REQ,
PMU_CLK_CENTER_SRC_GATE_EN = 26,
PMU_CLK_PERILP_SRC_GATE_EN,
PMU_CLK_CORE_SRC_GATE_EN,
PMU_DDRIO_RET_HW_DE_REQ,
PMU_SLP_OUTPUT_CFG,
PMU_MAIN_CLUSTER,
};
enum pmu_sft_con {
PMU_WKUP_SFT = 0,
PMU_INPUT_CLAMP_CFG,
PMU_OSC_DIS_CFG,
PMU_PMU_LF_EN_CFG,
PMU_ALIVE_LF_EN_CFG,
PMU_24M_EN_CFG,
PMU_DBG_PWRUP_L0_CFG,
PMU_WKUP_SFT_M0,
PMU_DDRCTL0_C_SYSREQ_CFG,
PMU_DDR0_IO_RET_CFG,
PMU_DDRCTL1_C_SYSREQ_CFG = 12,
PMU_DDR1_IO_RET_CFG,
DBG_PWRUP_B0_CFG = 15,
DBG_NOPWERDWN_L0_EN,
DBG_NOPWERDWN_L1_EN,
DBG_NOPWERDWN_L2_EN,
DBG_NOPWERDWN_L3_EN,
DBG_PWRUP_REQ_L_EN = 20,
CLUSTER_L_CLK_SRC_GATING_CFG,
L2_FLUSH_REQ_CLUSTER_L,
ACINACTM_CLUSTER_L_CFG,
DBG_NO_PWERDWN_B0_EN,
DBG_NO_PWERDWN_B1_EN,
DBG_PWRUP_REQ_B_EN = 28,
CLUSTER_B_CLK_SRC_GATING_CFG,
L2_FLUSH_REQ_CLUSTER_B,
ACINACTM_CLUSTER_B_CFG,
};
enum pmu_int_con {
PMU_PMU_INT_EN = 0,
PMU_PWRMD_WKUP_INT_EN,
PMU_WKUP_GPIO0_NEG_INT_EN,
PMU_WKUP_GPIO0_POS_INT_EN,
PMU_WKUP_GPIO1_NEG_INT_EN,
PMU_WKUP_GPIO1_POS_INT_EN,
};
enum pmu_int_st {
PMU_PWRMD_WKUP_INT_ST = 1,
PMU_WKUP_GPIO0_NEG_INT_ST,
PMU_WKUP_GPIO0_POS_INT_ST,
PMU_WKUP_GPIO1_NEG_INT_ST,
PMU_WKUP_GPIO1_POS_INT_ST,
};
enum pmu_gpio0_pos_int_con {
PMU_GPIO0A_POS_INT_EN = 0,
PMU_GPIO0B_POS_INT_EN = 8,
PMU_GPIO0C_POS_INT_EN = 16,
PMU_GPIO0D_POS_INT_EN = 24,
};
enum pmu_gpio0_neg_int_con {
PMU_GPIO0A_NEG_INT_EN = 0,
PMU_GPIO0B_NEG_INT_EN = 8,
PMU_GPIO0C_NEG_INT_EN = 16,
PMU_GPIO0D_NEG_INT_EN = 24,
};
enum pmu_gpio1_pos_int_con {
PMU_GPIO1A_POS_INT_EN = 0,
PMU_GPIO1B_POS_INT_EN = 8,
PMU_GPIO1C_POS_INT_EN = 16,
PMU_GPIO1D_POS_INT_EN = 24,
};
enum pmu_gpio1_neg_int_con {
PMU_GPIO1A_NEG_INT_EN = 0,
PMU_GPIO1B_NEG_INT_EN = 8,
PMU_GPIO1C_NEG_INT_EN = 16,
PMU_GPIO1D_NEG_INT_EN = 24,
};
enum pmu_gpio0_pos_int_st {
PMU_GPIO0A_POS_INT_ST = 0,
PMU_GPIO0B_POS_INT_ST = 8,
PMU_GPIO0C_POS_INT_ST = 16,
PMU_GPIO0D_POS_INT_ST = 24,
};
enum pmu_gpio0_neg_int_st {
PMU_GPIO0A_NEG_INT_ST = 0,
PMU_GPIO0B_NEG_INT_ST = 8,
PMU_GPIO0C_NEG_INT_ST = 16,
PMU_GPIO0D_NEG_INT_ST = 24,
};
enum pmu_gpio1_pos_int_st {
PMU_GPIO1A_POS_INT_ST = 0,
PMU_GPIO1B_POS_INT_ST = 8,
PMU_GPIO1C_POS_INT_ST = 16,
PMU_GPIO1D_POS_INT_ST = 24,
};
enum pmu_gpio1_neg_int_st {
PMU_GPIO1A_NEG_INT_ST = 0,
PMU_GPIO1B_NEG_INT_ST = 8,
PMU_GPIO1C_NEG_INT_ST = 16,
PMU_GPIO1D_NEG_INT_ST = 24,
};
/* pmu power down configure register 0x0050 */
enum pmu_pwrdn_inten {
PMU_A53_L0_PWR_SWITCH_INT_EN = 0,
PMU_A53_L1_PWR_SWITCH_INT_EN,
PMU_A53_L2_PWR_SWITCH_INT_EN,
PMU_A53_L3_PWR_SWITCH_INT_EN,
PMU_A72_B0_PWR_SWITCH_INT_EN,
PMU_A72_B1_PWR_SWITCH_INT_EN,
PMU_SCU_L_PWR_SWITCH_INT_EN,
PMU_SCU_B_PWR_SWITCH_INT_EN,
PMU_TCPD0_PWR_SWITCH_INT_EN,
PMU_TCPD1_PWR_SWITCH_INT_EN,
PMU_CCI_PWR_SWITCH_INT_EN,
PMU_PERILP_PWR_SWITCH_INT_EN,
PMU_PERIHP_PWR_SWITCH_INT_EN,
PMU_CENTER_PWR_SWITCH_INT_EN,
PMU_VIO_PWR_SWITCH_INT_EN,
PMU_GPU_PWR_SWITCH_INT_EN,
PMU_VCODEC_PWR_SWITCH_INT_EN,
PMU_VDU_PWR_SWITCH_INT_EN,
PMU_RGA_PWR_SWITCH_INT_EN,
PMU_IEP_PWR_SWITCH_INT_EN,
PMU_VO_PWR_SWITCH_INT_EN,
PMU_ISP0_PWR_SWITCH_INT_EN = 22,
PMU_ISP1_PWR_SWITCH_INT_EN,
PMU_HDCP_PWR_SWITCH_INT_EN,
PMU_GMAC_PWR_SWITCH_INT_EN,
PMU_EMMC_PWR_SWITCH_INT_EN,
PMU_USB3_PWR_SWITCH_INT_EN,
PMU_EDP_PWR_SWITCH_INT_EN,
PMU_GIC_PWR_SWITCH_INT_EN,
PMU_SD_PWR_SWITCH_INT_EN,
PMU_SDIOAUDIO_PWR_SWITCH_INT_EN,
};
enum pmu_wkup_status {
PMU_WKUP_BY_CLSTER_L_INT = 0,
PMU_WKUP_BY_CLSTER_b_INT,
PMU_WKUP_BY_GPIO_INT,
PMU_WKUP_BY_SDIO_DET,
PMU_WKUP_BY_SDMMC_DET,
PMU_WKUP_BY_TIMER = 6,
PMU_WKUP_BY_USBDEV_DET,
PMU_WKUP_BY_M0_SFT,
PMU_WKUP_BY_M0_WDT_INT,
PMU_WKUP_BY_TIMEOUT,
PMU_WKUP_BY_PWM,
PMU_WKUP_BY_PCIE = 13,
};
enum pmu_bus_clr {
PMU_CLR_GPU = 0,
PMU_CLR_PERILP,
PMU_CLR_PERIHP,
PMU_CLR_VCODEC,
PMU_CLR_VDU,
PMU_CLR_RGA,
PMU_CLR_IEP,
PMU_CLR_VOPB,
PMU_CLR_VOPL,
PMU_CLR_ISP0,
PMU_CLR_ISP1,
PMU_CLR_HDCP,
PMU_CLR_USB3,
PMU_CLR_PERILPM0,
PMU_CLR_CENTER,
PMU_CLR_CCIM1,
PMU_CLR_CCIM0,
PMU_CLR_VIO,
PMU_CLR_MSCH0,
PMU_CLR_MSCH1,
PMU_CLR_ALIVE,
PMU_CLR_PMU,
PMU_CLR_EDP,
PMU_CLR_GMAC,
PMU_CLR_EMMC,
PMU_CLR_CENTER1,
PMU_CLR_PMUM0,
PMU_CLR_GIC,
PMU_CLR_SD,
PMU_CLR_SDIOAUDIO,
};
/* PMU bus idle request register */
enum pmu_bus_idle_req {
PMU_IDLE_REQ_GPU = 0,
PMU_IDLE_REQ_PERILP,
PMU_IDLE_REQ_PERIHP,
PMU_IDLE_REQ_VCODEC,
PMU_IDLE_REQ_VDU,
PMU_IDLE_REQ_RGA,
PMU_IDLE_REQ_IEP,
PMU_IDLE_REQ_VOPB,
PMU_IDLE_REQ_VOPL,
PMU_IDLE_REQ_ISP0,
PMU_IDLE_REQ_ISP1,
PMU_IDLE_REQ_HDCP,
PMU_IDLE_REQ_USB3,
PMU_IDLE_REQ_PERILPM0,
PMU_IDLE_REQ_CENTER,
PMU_IDLE_REQ_CCIM0,
PMU_IDLE_REQ_CCIM1,
PMU_IDLE_REQ_VIO,
PMU_IDLE_REQ_MSCH0,
PMU_IDLE_REQ_MSCH1,
PMU_IDLE_REQ_ALIVE,
PMU_IDLE_REQ_PMU,
PMU_IDLE_REQ_EDP,
PMU_IDLE_REQ_GMAC,
PMU_IDLE_REQ_EMMC,
PMU_IDLE_REQ_CENTER1,
PMU_IDLE_REQ_PMUM0,
PMU_IDLE_REQ_GIC,
PMU_IDLE_REQ_SD,
PMU_IDLE_REQ_SDIOAUDIO,
};
/* pmu bus idle status register */
enum pmu_bus_idle_st {
PMU_IDLE_ST_GPU = 0,
PMU_IDLE_ST_PERILP,
PMU_IDLE_ST_PERIHP,
PMU_IDLE_ST_VCODEC,
PMU_IDLE_ST_VDU,
PMU_IDLE_ST_RGA,
PMU_IDLE_ST_IEP,
PMU_IDLE_ST_VOPB,
PMU_IDLE_ST_VOPL,
PMU_IDLE_ST_ISP0,
PMU_IDLE_ST_ISP1,
PMU_IDLE_ST_HDCP,
PMU_IDLE_ST_USB3,
PMU_IDLE_ST_PERILPM0,
PMU_IDLE_ST_CENTER,
PMU_IDLE_ST_CCIM0,
PMU_IDLE_ST_CCIM1,
PMU_IDLE_ST_VIO,
PMU_IDLE_ST_MSCH0,
PMU_IDLE_ST_MSCH1,
PMU_IDLE_ST_ALIVE,
PMU_IDLE_ST_PMU,
PMU_IDLE_ST_EDP,
PMU_IDLE_ST_GMAC,
PMU_IDLE_ST_EMMC,
PMU_IDLE_ST_CENTER1,
PMU_IDLE_ST_PMUM0,
PMU_IDLE_ST_GIC,
PMU_IDLE_ST_SD,
PMU_IDLE_ST_SDIOAUDIO,
};
enum pmu_bus_idle_ack {
PMU_IDLE_ACK_GPU = 0,
PMU_IDLE_ACK_PERILP,
PMU_IDLE_ACK_PERIHP,
PMU_IDLE_ACK_VCODEC,
PMU_IDLE_ACK_VDU,
PMU_IDLE_ACK_RGA,
PMU_IDLE_ACK_IEP,
PMU_IDLE_ACK_VOPB,
PMU_IDLE_ACK_VOPL,
PMU_IDLE_ACK_ISP0,
PMU_IDLE_ACK_ISP1,
PMU_IDLE_ACK_HDCP,
PMU_IDLE_ACK_USB3,
PMU_IDLE_ACK_PERILPM0,
PMU_IDLE_ACK_CENTER,
PMU_IDLE_ACK_CCIM0,
PMU_IDLE_ACK_CCIM1,
PMU_IDLE_ACK_VIO,
PMU_IDLE_ACK_MSCH0,
PMU_IDLE_ACK_MSCH1,
PMU_IDLE_ACK_ALIVE,
PMU_IDLE_ACK_PMU,
PMU_IDLE_ACK_EDP,
PMU_IDLE_ACK_GMAC,
PMU_IDLE_ACK_EMMC,
PMU_IDLE_ACK_CENTER1,
PMU_IDLE_ACK_PMUM0,
PMU_IDLE_ACK_GIC,
PMU_IDLE_ACK_SD,
PMU_IDLE_ACK_SDIOAUDIO,
};
enum pmu_cci500_con {
PMU_PREQ_CCI500_CFG_SW = 0,
PMU_CLR_PREQ_CCI500_HW,
PMU_PSTATE_CCI500_0,
PMU_PSTATE_CCI500_1,
PMU_PSTATE_CCI500_2,
PMU_QREQ_CCI500_CFG_SW,
PMU_CLR_QREQ_CCI500_HW,
PMU_QGATING_CCI500_CFG,
PMU_PREQ_CCI500_CFG_SW_WMSK = 16,
PMU_CLR_PREQ_CCI500_HW_WMSK,
PMU_PSTATE_CCI500_0_WMSK,
PMU_PSTATE_CCI500_1_WMSK,
PMU_PSTATE_CCI500_2_WMSK,
PMU_QREQ_CCI500_CFG_SW_WMSK,
PMU_CLR_QREQ_CCI500_HW_WMSK,
PMU_QGATING_CCI500_CFG_WMSK,
};
enum pmu_adb400_con {
PMU_PWRDWN_REQ_CXCS_SW = 0,
PMU_PWRDWN_REQ_CORE_L_SW,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW,
PMU_PWRDWN_REQ_CORE_B_SW,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW,
PMU_CLR_CXCS_HW = 8,
PMU_CLR_CORE_L_HW,
PMU_CLR_CORE_L_2GIC_HW,
PMU_CLR_GIC2_CORE_L_HW,
PMU_CLR_CORE_B_HW,
PMU_CLR_CORE_B_2GIC_HW,
PMU_CLR_GIC2_CORE_B_HW,
PMU_PWRDWN_REQ_CXCS_SW_WMSK = 16,
PMU_PWRDWN_REQ_CORE_L_SW_WMSK,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_WMSK,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_WMSK,
PMU_PWRDWN_REQ_CORE_B_SW_WMSK,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_WMSK,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_WMSK,
PMU_CLR_CXCS_HW_WMSK = 24,
PMU_CLR_CORE_L_HW_WMSK,
PMU_CLR_CORE_L_2GIC_HW_WMSK,
PMU_CLR_GIC2_CORE_L_HW_WMSK,
PMU_CLR_CORE_B_HW_WMSK,
PMU_CLR_CORE_B_2GIC_HW_WMSK,
PMU_CLR_GIC2_CORE_B_HW_WMSK,
};
enum pmu_adb400_st {
PMU_PWRDWN_REQ_CXCS_SW_ST = 0,
PMU_PWRDWN_REQ_CORE_L_SW_ST,
PMU_PWRDWN_REQ_CORE_L_2GIC_SW_ST,
PMU_PWRDWN_REQ_GIC2_CORE_L_SW_ST,
PMU_PWRDWN_REQ_CORE_B_SW_ST,
PMU_PWRDWN_REQ_CORE_B_2GIC_SW_ST,
PMU_PWRDWN_REQ_GIC2_CORE_B_SW_ST,
PMU_CLR_CXCS_HW_ST = 8,
PMU_CLR_CORE_L_HW_ST,
PMU_CLR_CORE_L_2GIC_HW_ST,
PMU_CLR_GIC2_CORE_L_HW_ST,
PMU_CLR_CORE_B_HW_ST,
PMU_CLR_CORE_B_2GIC_HW_ST,
PMU_CLR_GIC2_CORE_B_HW_ST,
};
enum pmu_pwrdn_con1 {
PMU_VD_SCU_L_PWRDN_EN = 0,
PMU_VD_SCU_B_PWRDN_EN,
PMU_VD_CENTER_PWRDN_EN,
};
enum pmu_core_pwr_st {
L2_FLUSHDONE_CLUSTER_L = 0,
STANDBY_BY_WFIL2_CLUSTER_L,
L2_FLUSHDONE_CLUSTER_B = 10,
STANDBY_BY_WFIL2_CLUSTER_B,
};
#endif /* __PMU_BITS_H__ */
plat/rockchip/rk3399/rk3399_def.h
View file @ 1830f790
......@@ -31,122 +31,18 @@
#ifndef __PLAT_DEF_H__
#define __PLAT_DEF_H__
#define RK3399_PRIMARY_CPU 0x0
#include <addressmap.h>
/* Special value used to verify platform parameters from BL2 to BL3-1 */
#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
#define SIZE_K(n) ((n) * 1024)
#define SIZE_M(n) ((n) * 1024 * 1024)
/* Register base address and size */
#define MMIO_BASE 0xfe000000
#define GIC500_BASE (MMIO_BASE + 0xe00000)
#define GIC500_SIZE SIZE_M(2)
#define PMU_BASE (MMIO_BASE + 0x1310000)
#define PMU_SIZE SIZE_K(64)
#define PMUGRF_BASE (MMIO_BASE + 0x1320000)
#define PMUGRF_SIZE SIZE_K(64)
#define SGRF_BASE (MMIO_BASE + 0x1330000)
#define SGRF_SIZE SIZE_K(64)
#define PMUSRAM_BASE (MMIO_BASE + 0x13b0000)
#define PMUSRAM_SIZE SIZE_K(64)
#define PMUSRAM_RSIZE SIZE_K(8)
#define PWM_BASE (MMIO_BASE + 0x1420000)
#define PWM_SIZE SIZE_K(64)
#define CIC_BASE (MMIO_BASE + 0x1620000)
#define CIC_SIZE SIZE_K(4)
#define DCF_BASE (MMIO_BASE + 0x16a0000)
#define DCF_SIZE SIZE_K(4)
#define GPIO0_BASE (MMIO_BASE + 0x1720000)
#define GPIO0_SIZE SIZE_K(64)
#define GPIO1_BASE (MMIO_BASE + 0x1730000)
#define GPIO1_SIZE SIZE_K(64)
#define CRUS_BASE (MMIO_BASE + 0x1750000)
#define CRUS_SIZE SIZE_K(128)
#define GRF_BASE (MMIO_BASE + 0x1770000)
#define GRF_SIZE SIZE_K(64)
#define GPIO2_BASE (MMIO_BASE + 0x1780000)
#define GPIO2_SIZE SIZE_K(32)
#define GPIO3_BASE (MMIO_BASE + 0x1788000)
#define GPIO3_SIZE SIZE_K(32)
#define GPIO4_BASE (MMIO_BASE + 0x1790000)
#define GPIO4_SIZE SIZE_K(32)
#define STIME_BASE (MMIO_BASE + 0x1860000)
#define STIME_SIZE SIZE_K(64)
#define RK3399_PRIMARY_CPU 0x0
#define SRAM_BASE (MMIO_BASE + 0x18c0000)
#define SRAM_SIZE SIZE_K(192)
#define SERVICE_NOC_0_BASE (MMIO_BASE + 0x1a50000)
#define NOC_0_SIZE SIZE_K(192)
#define DDRC0_BASE (MMIO_BASE + 0x1a80000)
#define DDRC0_SIZE SIZE_K(32)
#define SERVICE_NOC_1_BASE (MMIO_BASE + 0x1a84000)
#define NOC_1_SIZE SIZE_K(16)
#define DDRC1_BASE (MMIO_BASE + 0x1a88000)
#define DDRC1_SIZE SIZE_K(32)
#define SERVICE_NOC_2_BASE (MMIO_BASE + 0x1a8c000)
#define NOC_2_SIZE SIZE_K(16)
#define SERVICE_NOC_3_BASE (MMIO_BASE + 0x1a90000)
#define NOC_3_SIZE SIZE_K(448)
#define CCI500_BASE (MMIO_BASE + 0x1b00000)
#define CCI500_SIZE SIZE_M(1)
#define DDR_PI_OFFSET 0x800
#define DDR_PHY_OFFSET 0x2000
#define DDRC0_PI_BASE (DDRC0_BASE + DDR_PI_OFFSET)
#define DDRC0_PHY_BASE (DDRC0_BASE + DDR_PHY_OFFSET)
#define DDRC1_PI_BASE (DDRC1_BASE + DDR_PI_OFFSET)
#define DDRC1_PHY_BASE (DDRC1_BASE + DDR_PHY_OFFSET)
/* Aggregate of all devices in the first GB */
#define RK3399_DEV_RNG0_BASE MMIO_BASE
#define RK3399_DEV_RNG0_SIZE 0x1d00000
/*
* include i2c pmu/audio, pwm0-3 rkpwm0-3 uart_dbg,mailbox scr
* 0xff650000 -0xff6c0000
*/
#define PD_BUS0_BASE (MMIO_BASE + 0x1650000)
#define PD_BUS0_SIZE SIZE_K(448)
#define PMUCRU_BASE (MMIO_BASE + 0x1750000)
#define CRU_BASE (MMIO_BASE + 0x1760000)
#define COLD_BOOT_BASE (MMIO_BASE + 0x1ff0000)
/* Special value used to verify platform parameters from BL2 to BL3-1 */
#define RK_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
/**************************************************************************
* UART related constants
**************************************************************************/
#define RK3399_UART2_BASE (0xff1a0000)
#define RK3399_UART2_SIZE SIZE_K(64)
#define RK3399_BAUDRATE (115200)
#define RK3399_UART_CLOCK (24000000)
#define RK3399_BAUDRATE 115200
#define RK3399_UART_CLOCK 24000000
/******************************************************************************
* System counter frequency related constants
......@@ -154,8 +50,8 @@
#define SYS_COUNTER_FREQ_IN_TICKS 24000000
/* Base rockchip_platform compatible GIC memory map */
#define BASE_GICD_BASE (GIC500_BASE)
#define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1))
#define BASE_GICD_BASE (GIC500_BASE)
#define BASE_GICR_BASE (GIC500_BASE + SIZE_M(1))
/*****************************************************************************
* CCI-400 related constants
......@@ -176,6 +72,7 @@
#define ARM_IRQ_SEC_SGI_5 13
#define ARM_IRQ_SEC_SGI_6 14
#define ARM_IRQ_SEC_SGI_7 15
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated
......
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