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adam.huang
Arm Trusted Firmware
Commits
18a17e6a
Commit
18a17e6a
authored
May 08, 2014
by
danh-arm
Browse files
Merge pull request #62 from athoelke/set-little-endian-v2
Set processor endianness immediately after RESET v2
parents
fd6fede5
40fd0725
Changes
3
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bl1/aarch64/bl1_arch_setup.c
View file @
18a17e6a
...
...
@@ -39,10 +39,9 @@ void bl1_arch_setup(void)
{
unsigned
long
tmp_reg
=
0
;
/* Enable alignment checks
and set the exception endianess to LE
*/
/* Enable alignment checks */
tmp_reg
=
read_sctlr_el3
();
tmp_reg
|=
(
SCTLR_A_BIT
|
SCTLR_SA_BIT
);
tmp_reg
&=
~
SCTLR_EE_BIT
;
write_sctlr_el3
(
tmp_reg
);
isb
();
...
...
bl1/aarch64/bl1_entrypoint.S
View file @
18a17e6a
...
...
@@ -42,6 +42,16 @@
*/
func
bl1_entrypoint
/
*
---------------------------------------------
*
Set
the
CPU
endianness
before
doing
anything
*
that
might
involve
memory
reads
or
writes
*
---------------------------------------------
*/
mrs
x0
,
sctlr_el3
bic
x0
,
x0
,
#
SCTLR_EE_BIT
msr
sctlr_el3
,
x0
isb
/
*
---------------------------------------------
*
Perform
any
processor
specific
actions
upon
*
reset
e
.
g
.
cache
,
tlb
invalidations
etc
.
...
...
bl31/aarch64/bl31_arch_setup.c
View file @
18a17e6a
...
...
@@ -45,10 +45,9 @@ void bl31_arch_setup(void)
unsigned
long
tmp_reg
=
0
;
uint64_t
counter_freq
;
/* Enable alignment checks
and set the exception endianness to LE
*/
/* Enable alignment checks */
tmp_reg
=
read_sctlr_el3
();
tmp_reg
|=
(
SCTLR_A_BIT
|
SCTLR_SA_BIT
);
tmp_reg
&=
~
SCTLR_EE_BIT
;
write_sctlr_el3
(
tmp_reg
);
/*
...
...
Write
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