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Commit 1ba2ff7b authored by Antonio Nino Diaz's avatar Antonio Nino Diaz
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qemu: Migrate to new interfaces 



- Remove references to removed build options.
- Remove support for LOAD_IMAGE_V2=0.
- Migrate to sp_min_early_platform_setup2().

Change-Id: I884399139fb8e2554adeded888969f44672d56c0
Co-authored-by: default avatarJens Wiklander <jens.wiklander@linaro.org>
Tested-by: default avatarJens Wiklander <jens.wiklander@linaro.org>
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
parent 99865e0a
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Inline Side-by-side
plat/qemu/platform.mk
View file @ 1ba2ff7b
......@@ -25,12 +25,6 @@ endif
include lib/libfdt/libfdt.mk
# Enable new version of image loading on QEMU platforms
LOAD_IMAGE_V2 := 1
ifneq ($(LOAD_IMAGE_V2),1)
$(error Error: qemu needs LOAD_IMAGE_V2=1)
endif
ifeq ($(NEED_BL32),yes)
$(eval $(call add_define,QEMU_LOAD_BL32))
endif
......@@ -68,8 +62,6 @@ ifneq (${TRUSTED_BOARD_BOOT},0)
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
USE_TBBR_DEFS := 1
AUTH_SOURCES := drivers/auth/auth_mod.c \
drivers/auth/crypto_mod.c \
drivers/auth/img_parser_mod.c \
......@@ -181,9 +173,6 @@ ifeq ($(ARCH),aarch64)
MULTI_CONSOLE_API := 1
endif
# Disable the PSCI platform compatibility layer
ENABLE_PLAT_COMPAT := 0
BL32_RAM_LOCATION := tdram
ifeq (${BL32_RAM_LOCATION}, tsram)
BL32_RAM_LOCATION_ID = SEC_SRAM_ID
......
plat/qemu/qemu_bl1_setup.c
View file @ 1ba2ff7b
......@@ -39,7 +39,7 @@ void bl1_early_platform_setup(void)
* does not do anything platform specific.
*****************************************************************************/
#ifdef AARCH32
#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_secure(__VA_ARGS__)
#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
#else
#define QEMU_CONFIGURE_BL1_MMU(...) qemu_configure_mmu_el3(__VA_ARGS__)
#endif
......
plat/qemu/qemu_bl2_setup.c
View file @ 1ba2ff7b
......@@ -20,103 +20,6 @@
/* Data structure which holds the extents of the trusted SRAM for BL2 */
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
#if !LOAD_IMAGE_V2
/*******************************************************************************
* This structure represents the superset of information that is passed to
* BL3-1, e.g. while passing control to it from BL2, bl31_params
* and other platform specific params
******************************************************************************/
typedef struct bl2_to_bl31_params_mem {
bl31_params_t bl31_params;
image_info_t bl31_image_info;
image_info_t bl32_image_info;
image_info_t bl33_image_info;
entry_point_info_t bl33_ep_info;
entry_point_info_t bl32_ep_info;
entry_point_info_t bl31_ep_info;
} bl2_to_bl31_params_mem_t;
static bl2_to_bl31_params_mem_t bl31_params_mem;
meminfo_t *bl2_plat_sec_mem_layout(void)
{
return &bl2_tzram_layout;
}
/*******************************************************************************
* This function assigns a pointer to the memory that the platform has kept
* aside to pass platform specific and trusted firmware related information
* to BL31. This memory is allocated by allocating memory to
* bl2_to_bl31_params_mem_t structure which is a superset of all the
* structure whose information is passed to BL31
* NOTE: This function should be called only once and should be done
* before generating params to BL31
******************************************************************************/
bl31_params_t *bl2_plat_get_bl31_params(void)
{
bl31_params_t *bl2_to_bl31_params;
/*
* Initialise the memory for all the arguments that needs to
* be passed to BL3-1
*/
zeromem(&bl31_params_mem, sizeof(bl2_to_bl31_params_mem_t));
/* Assign memory for TF related information */
bl2_to_bl31_params = &bl31_params_mem.bl31_params;
SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
/* Fill BL3-1 related information */
bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
VERSION_1, 0);
/* Fill BL3-2 related information */
bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
VERSION_1, 0);
bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
VERSION_1, 0);
/* Fill BL3-3 related information */
bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
PARAM_EP, VERSION_1, 0);
/* BL3-3 expects to receive the primary CPU MPID (through x0) */
bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
VERSION_1, 0);
return bl2_to_bl31_params;
}
/* Flush the TF params and the TF plat params */
void bl2_plat_flush_bl31_params(void)
{
flush_dcache_range((unsigned long)&bl31_params_mem,
sizeof(bl2_to_bl31_params_mem_t));
}
/*******************************************************************************
* This function returns a pointer to the shared memory that the platform
* has kept to point to entry point information of BL31 to BL2
******************************************************************************/
struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
{
#if DEBUG
bl31_params_mem.bl31_ep_info.args.arg1 = QEMU_BL31_PLAT_PARAM_VAL;
#endif
return &bl31_params_mem.bl31_ep_info;
}
#endif /* !LOAD_IMAGE_V2 */
void bl2_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
......@@ -174,7 +77,7 @@ void bl2_platform_setup(void)
}
#ifdef AARCH32
#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_secure(__VA_ARGS__)
#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_svc_mon(__VA_ARGS__)
#else
#define QEMU_CONFIGURE_BL2_MMU(...) qemu_configure_mmu_el1(__VA_ARGS__)
#endif
......@@ -231,7 +134,6 @@ static uint32_t qemu_get_spsr_for_bl33_entry(void)
return spsr;
}
#if LOAD_IMAGE_V2
static int qemu_bl2_handle_post_image_load(unsigned int image_id)
{
int err = 0;
......@@ -305,75 +207,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
return qemu_bl2_handle_post_image_load(image_id);
}
#else /* LOAD_IMAGE_V2 */
/*******************************************************************************
* Before calling this function BL3-1 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL3-1 and set SPSR and security state.
* On ARM standard platforms we only set the security state of the entrypoint
******************************************************************************/
void bl2_plat_set_bl31_ep_info(image_info_t *bl31_image_info,
entry_point_info_t *bl31_ep_info)
{
SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
DISABLE_ALL_EXCEPTIONS);
}
/*******************************************************************************
* Before calling this function BL3-2 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL3-2 and set SPSR and security state.
* On ARM standard platforms we only set the security state of the entrypoint
******************************************************************************/
void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
entry_point_info_t *bl32_ep_info)
{
SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
bl32_ep_info->spsr = qemu_get_spsr_for_bl32_entry();
}
/*******************************************************************************
* Before calling this function BL3-3 is loaded in memory and its entrypoint
* is set by load_image. This is a placeholder for the platform to change
* the entrypoint of BL3-3 and set SPSR and security state.
* On ARM standard platforms we only set the security state of the entrypoint
******************************************************************************/
void bl2_plat_set_bl33_ep_info(image_info_t *image,
entry_point_info_t *bl33_ep_info)
{
SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
bl33_ep_info->spsr = qemu_get_spsr_for_bl33_entry();
}
/*******************************************************************************
* Populate the extents of memory available for loading BL32
******************************************************************************/
void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
{
/*
* Populate the extents of memory available for loading BL32.
*/
bl32_meminfo->total_base = BL32_BASE;
bl32_meminfo->free_base = BL32_BASE;
bl32_meminfo->total_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
bl32_meminfo->free_size = (BL32_MEM_BASE + BL32_MEM_SIZE) - BL32_BASE;
}
/*******************************************************************************
* Populate the extents of memory available for loading BL33
******************************************************************************/
void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
{
bl33_meminfo->total_base = NS_DRAM0_BASE;
bl33_meminfo->total_size = NS_DRAM0_SIZE;
bl33_meminfo->free_base = NS_DRAM0_BASE;
bl33_meminfo->free_size = NS_DRAM0_SIZE;
}
#endif /* !LOAD_IMAGE_V2 */
uintptr_t plat_get_ns_image_entrypoint(void)
{
return NS_IMAGE_OFFSET;
......
plat/qemu/qemu_common.c
View file @ 1ba2ff7b
......@@ -131,7 +131,7 @@ static const mmap_region_t plat_qemu_mmap[] = {
/* Define EL1 and EL3 variants of the function initialising the MMU */
#ifdef AARCH32
DEFINE_CONFIGURE_MMU_EL(secure)
DEFINE_CONFIGURE_MMU_EL(svc_mon)
#else
DEFINE_CONFIGURE_MMU_EL(el1)
DEFINE_CONFIGURE_MMU_EL(el3)
......
plat/qemu/qemu_private.h
View file @ 1ba2ff7b
......@@ -11,7 +11,7 @@
#include "../../bl1/bl1_private.h"
void qemu_configure_mmu_secure(unsigned long total_base,
void qemu_configure_mmu_svc_mon(unsigned long total_base,
unsigned long total_size,
unsigned long code_start, unsigned long code_limit,
unsigned long ro_start, unsigned long ro_limit,
......
plat/qemu/sp_min/sp_min_setup.c
View file @ 1ba2ff7b
......@@ -5,7 +5,6 @@
*/
#include <arch_helpers.h>
#include <arm_gic.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
......@@ -108,9 +107,10 @@ entry_point_info_t *sp_min_plat_get_bl33_ep_info(void)
return NULL;
}
void sp_min_early_platform_setup(void *from_bl2, void *plat_params_from_bl2)
void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
bl_params_t *params_from_bl2 = (bl_params_t *)from_bl2;
bl_params_t *params_from_bl2 = (bl_params_t *)arg0;
/* Initialize the console to provide early debug support */
console_init(PLAT_QEMU_BOOT_UART_BASE, PLAT_QEMU_BOOT_UART_CLK_IN_HZ,
......@@ -142,7 +142,7 @@ void sp_min_early_platform_setup(void *from_bl2, void *plat_params_from_bl2)
void sp_min_plat_arch_setup(void)
{
qemu_configure_mmu_secure(BL32_RO_BASE, BL32_END - BL32_RO_BASE,
qemu_configure_mmu_svc_mon(BL32_RO_BASE, BL32_END - BL32_RO_BASE,
BL32_RO_BASE, BL32_RO_LIMIT,
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
......
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