intel: System Manager refactoring

Refactored system manager driver to be shared across both intel platform
Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: Ic4d056c3d15c3152403dc11641c2452770a6162d

plat/intel/soc/agilex/bl2_plat_setup.c

@@ -18,13 +18,13 @@
 #include "agilex_clock_manager.h"
 #include "agilex_memory_controller.h"
 #include "agilex_pinmux.h"
-#include "agilex_system_manager.h"
 #include "ccu/ncore_ccu.h"
 #include "qspi/cadence_qspi.h"
 #include "socfpga_handoff.h"
 #include "socfpga_mailbox.h"
 #include "socfpga_private.h"
 #include "socfpga_reset_manager.h"
+#include "socfpga_system_manager.h"
 #include "wdt/watchdog.h"
 
 

plat/intel/soc/agilex/include/agilex_system_manager.h

-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef AGX_SYSTEMMANAGER_H
-#define AGX_SYSTEMMANAGER_H
-
-#define AGX_FIREWALL_SOC2FPGA			0xffd21200
-#define AGX_FIREWALL_LWSOC2FPGA			0xffd21300
-
-#define AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER	0xffd21000
-#define AGX_NOC_FW_L4_PER_SCR_NAND_DATA		0xffd21004
-#define AGX_NOC_FW_L4_PER_SCR_USB0_REGISTER	0xffd2100c
-#define AGX_NOC_FW_L4_PER_SCR_USB1_REGISTER	0xffd21010
-#define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER0	0xffd2101c
-#define AGX_NOC_FW_L4_PER_SCR_SPI_MASTER1	0xffd21020
-#define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE0	0xffd21024
-#define AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE1	0xffd21028
-#define AGX_NOC_FW_L4_PER_SCR_EMAC0		0xffd2102c
-#define AGX_NOC_FW_L4_PER_SCR_EMAC1		0xffd21030
-#define AGX_NOC_FW_L4_PER_SCR_EMAC2		0xffd21034
-#define AGX_NOC_FW_L4_PER_SCR_SDMMC		0xffd21040
-#define AGX_NOC_FW_L4_PER_SCR_GPIO0		0xffd21044
-#define AGX_NOC_FW_L4_PER_SCR_GPIO1		0xffd21048
-#define AGX_NOC_FW_L4_PER_SCR_I2C0		0xffd21050
-#define AGX_NOC_FW_L4_PER_SCR_I2C1		0xffd21054
-#define AGX_NOC_FW_L4_PER_SCR_I2C2		0xffd21058
-#define AGX_NOC_FW_L4_PER_SCR_I2C3		0xffd2105c
-#define AGX_NOC_FW_L4_PER_SCR_I2C4		0xffd21060
-#define AGX_NOC_FW_L4_PER_SCR_SP_TIMER0		0xffd21064
-#define AGX_NOC_FW_L4_PER_SCR_SP_TIMER1		0xffd21068
-#define AGX_NOC_FW_L4_PER_SCR_UART0		0xffd2106c
-#define AGX_NOC_FW_L4_PER_SCR_UART1		0xffd21070
-
-#define AGX_NOC_FW_L4_SYS_SCR_DMA_ECC		0xffd21108
-#define AGX_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC	0xffd2110c
-#define AGX_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC	0xffd21110
-#define AGX_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC	0xffd21114
-#define AGX_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC	0xffd21118
-#define AGX_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC	0xffd2111c
-#define AGX_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC	0xffd21120
-#define AGX_NOC_FW_L4_SYS_SCR_NAND_ECC		0xffd2112c
-#define AGX_NOC_FW_L4_SYS_SCR_NAND_READ_ECC	0xffd21130
-#define AGX_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC	0xffd21134
-#define AGX_NOC_FW_L4_SYS_SCR_OCRAM_ECC		0xffd21138
-#define AGX_NOC_FW_L4_SYS_SCR_SDMMC_ECC		0xffd21140
-#define AGX_NOC_FW_L4_SYS_SCR_USB0_ECC		0xffd21144
-#define AGX_NOC_FW_L4_SYS_SCR_USB1_ECC		0xffd21148
-#define AGX_NOC_FW_L4_SYS_SCR_CLK_MGR		0xffd2114c
-#define AGX_NOC_FW_L4_SYS_SCR_IO_MGR		0xffd21154
-#define AGX_NOC_FW_L4_SYS_SCR_RST_MGR		0xffd21158
-#define AGX_NOC_FW_L4_SYS_SCR_SYS_MGR		0xffd2115c
-#define AGX_NOC_FW_L4_SYS_SCR_OSC0_TIMER	0xffd21160
-#define AGX_NOC_FW_L4_SYS_SCR_OSC1_TIMER	0xffd21164
-#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG0		0xffd21168
-#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG1		0xffd2116c
-#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG2		0xffd21170
-#define AGX_NOC_FW_L4_SYS_SCR_WATCHDOG3		0xffd21174
-#define AGX_NOC_FW_L4_SYS_SCR_DAP		0xffd21178
-#define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES	0xffd21190
-#define AGX_NOC_FW_L4_SYS_SCR_L4_NOC_QOS	0xffd21194
-
-#define AGX_CCU_NOC_CPU0_RAMSPACE0_0		0xf7004688
-#define AGX_CCU_NOC_IOM_RAMSPACE0_0		0xf7018628
-
-#define AGX_SYSMGR_CORE(x)                      (0xffd12000 + (x))
-
-#define SYSMGR_NOC_TIMEOUT			0xc0
-#define SYSMGR_NOC_IDLEREQ_SET			0xc4
-#define SYSMGR_NOC_IDLEREQ_CLR			0xc8
-#define SYSMGR_NOC_IDLEREQ_VAL			0xcc
-#define SYSMGR_NOC_IDLEACK			0xd0
-#define SYSMGR_NOC_IDLESTATUS			0xd4
-
-#define IDLE_DATA_LWSOC2FPGA			BIT(0)
-#define IDLE_DATA_SOC2FPGA			BIT(4)
-#define IDLE_DATA_MASK	(IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
-
-#define SYSMGR_BOOT_SCRATCH_COLD_0		0x200
-#define SYSMGR_BOOT_SCRATCH_COLD_1		0x204
-#define SYSMGR_BOOT_SCRATCH_COLD_2		0x208
-
-#define DISABLE_BRIDGE_FIREWALL			0x0ffe0101
-#define DISABLE_L4_FIREWALL	(BIT(0) | BIT(16) | BIT(24))
-
-void enable_nonsecure_access(void);
-void enable_ns_peripheral_access(void);
-void enable_ns_bridge_access(void);
-
-#endif

plat/intel/soc/agilex/include/socfpga_plat_def.h

@@ -15,7 +15,14 @@
 
 /* Register Mapping */
 #define SOCFPGA_MMC_REG_BASE			0xff808000
+
 #define SOCFPGA_RSTMGR_REG_BASE			0xffd11000
+#define SOCFPGA_SYSMGR_REG_BASE			0xffd12000
+
+#define SOCFPGA_L4_PER_SCR_REG_BASE             0xffd21000
+#define SOCFPGA_L4_SYS_SCR_REG_BASE             0xffd21100
+#define SOCFPGA_SOC2FPGA_SCR_REG_BASE           0xffd21200
+#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE         0xffd21300
 
 #endif /* PLAT_SOCFPGA_DEF_H */
 

plat/intel/soc/agilex/platform.mk

@@ -38,7 +38,6 @@ BL2_SOURCES     +=	\
 		plat/intel/soc/agilex/soc/agilex_clock_manager.c	\
 		plat/intel/soc/agilex/soc/agilex_memory_controller.c	\
 		plat/intel/soc/agilex/soc/agilex_pinmux.c		\
-		plat/intel/soc/agilex/soc/agilex_system_manager.c	\
                 plat/intel/soc/common/bl2_plat_mem_params_desc.c	\
 		plat/intel/soc/common/socfpga_delay_timer.c		\
 		plat/intel/soc/common/socfpga_image_load.c		\
@@ -46,6 +45,7 @@ BL2_SOURCES     +=	\
 		plat/intel/soc/common/soc/socfpga_handoff.c		\
 		plat/intel/soc/common/soc/socfpga_mailbox.c		\
 		plat/intel/soc/common/soc/socfpga_reset_manager.c	\
+		plat/intel/soc/common/soc/socfpga_system_manager.c	\
 		plat/intel/soc/common/drivers/qspi/cadence_qspi.c	\
 		plat/intel/soc/common/drivers/wdt/watchdog.c		\
 		plat/intel/soc/common/drivers/ccu/ncore_ccu.c

plat/intel/soc/agilex/soc/agilex_clock_manager.c

@@ -11,8 +11,8 @@
 #include <lib/mmio.h>
 
 #include "agilex_clock_manager.h"
-#include "agilex_system_manager.h"
 #include "socfpga_handoff.h"
+#include "socfpga_system_manager.h"
 
 
 uint32_t wait_pll_lock(void)
@@ -261,9 +261,9 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
 			CLKMGR_PERPLL_EN_RESET);
 
 	/* Pass clock source frequency into scratch register */
-	mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1),
+	mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1),
 		hoff_ptr->hps_osc_clk_h);
-	mmio_write_32(AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2),
+	mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2),
 		hoff_ptr->fpga_clk_hz);
 }
 
@@ -275,14 +275,14 @@ uint32_t get_ref_clk(uint32_t pllglob)
 
 	switch (CLKMGR_PSRC(pllglob)) {
 	case CLKMGR_PLLGLOB_PSRC_EOSC1:
-		scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1);
+		scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1);
 		ref_clk = mmio_read_32(scr_reg);
 		break;
 	case CLKMGR_PLLGLOB_PSRC_INTOSC:
 		ref_clk = CLKMGR_INTOSC_HZ;
 		break;
 	case CLKMGR_PLLGLOB_PSRC_F2S:
-		scr_reg = AGX_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2);
+		scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2);
 		ref_clk = mmio_read_32(scr_reg);
 		break;
 	default:

plat/intel/soc/agilex/soc/agilex_system_manager.c

-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-#include <lib/utils_def.h>
-
-#include "agilex_system_manager.h"
-
-void enable_nonsecure_access(void)
-{
-	enable_ns_peripheral_access();
-	enable_ns_bridge_access();
-}
-
-void enable_ns_peripheral_access(void)
-{
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC,
-		DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL);
-
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL);
-
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL);
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(AGX_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL);
-}
-
-void enable_ns_bridge_access(void)
-{
-	mmio_write_32(AGX_FIREWALL_SOC2FPGA, DISABLE_BRIDGE_FIREWALL);
-	mmio_write_32(AGX_FIREWALL_LWSOC2FPGA, DISABLE_BRIDGE_FIREWALL);
-}

plat/intel/soc/common/include/socfpga_system_manager.h

+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef SOCFPGA_SYSTEMMANAGER_H
+#define SOCFPGA_SYSTEMMANAGER_H
+
+#include "socfpga_plat_def.h"
+
+/* System Manager Register Map */
+
+#define SOCFPGA_SYSMGR_SDMMC				0x28
+
+#define SOCFPGA_SYSMGR_NOC_TIMEOUT			0xc0
+#define SOCFPGA_SYSMGR_NOC_IDLEREQ_SET			0xc4
+#define SOCFPGA_SYSMGR_NOC_IDLEREQ_CLR			0xc8
+#define SOCFPGA_SYSMGR_NOC_IDLEREQ_VAL			0xcc
+#define SOCFPGA_SYSMGR_NOC_IDLEACK			0xd0
+#define SOCFPGA_SYSMGR_NOC_IDLESTATUS			0xd4
+
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_0		0x200
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_1		0x204
+#define SOCFPGA_SYSMGR_BOOT_SCRATCH_COLD_2		0x208
+
+/* Field Masking */
+
+#define SYSMGR_SDMMC_DRVSEL(x)			(((x) & 0x7) << 0)
+
+#define IDLE_DATA_LWSOC2FPGA				BIT(0)
+#define IDLE_DATA_SOC2FPGA				BIT(4)
+#define IDLE_DATA_MASK		(IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
+
+#define SCR_AXI_AP_MASK					BIT(24)
+#define SCR_FPGA2SOC_MASK				BIT(16)
+#define SCR_MPU_MASK					BIT(0)
+#define DISABLE_L4_FIREWALL	(SCR_AXI_AP_MASK | SCR_FPGA2SOC_MASK \
+					| SCR_MPU_MASK)
+#define DISABLE_BRIDGE_FIREWALL				0x0ffe0101
+
+/* Macros */
+
+#define SOCFPGA_SYSMGR(_reg)		(SOCFPGA_SYSMGR_REG_BASE \
+						+ (SOCFPGA_SYSMGR_##_reg))
+
+#define SOCFPGA_L4_PER_SCR(_reg)	(SOCFPGA_L4_PER_SCR_REG_BASE \
+					+ (SOCFPGA_NOC_FW_L4_PER_SCR_##_reg))
+
+#define SOCFPGA_L4_SYS_SCR(_reg)	(SOCFPGA_L4_SYS_SCR_REG_BASE \
+					+ (SOCFPGA_NOC_FW_L4_SYS_SCR_##_reg))
+
+/* L3 Interconnect Register Map */
+#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_REGISTER			0x0000
+#define SOCFPGA_NOC_FW_L4_PER_SCR_NAND_DATA			0x0004
+#define SOCFPGA_NOC_FW_L4_PER_SCR_USB0_REGISTER			0x000c
+#define SOCFPGA_NOC_FW_L4_PER_SCR_USB1_REGISTER			0x0010
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER0			0x001c
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_MASTER1			0x0020
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE0			0x0024
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SPI_SLAVE1			0x0028
+#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC0				0x002c
+#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC1				0x0030
+#define SOCFPGA_NOC_FW_L4_PER_SCR_EMAC2				0x0034
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SDMMC				0x0040
+#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO0				0x0044
+#define SOCFPGA_NOC_FW_L4_PER_SCR_GPIO1				0x0048
+#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C0				0x0050
+#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C1				0x0054
+#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C2				0x0058
+#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C3				0x005c
+#define SOCFPGA_NOC_FW_L4_PER_SCR_I2C4				0x0060
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER0			0x0064
+#define SOCFPGA_NOC_FW_L4_PER_SCR_SP_TIMER1			0x0068
+#define SOCFPGA_NOC_FW_L4_PER_SCR_UART0				0x006c
+#define SOCFPGA_NOC_FW_L4_PER_SCR_UART1				0x0070
+
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_DMA_ECC			0x0008
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC			0x000c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC			0x0010
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC			0x0014
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC			0x0018
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC			0x001c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC			0x0020
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_ECC			0x002c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_READ_ECC			0x0030
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC		0x0034
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_OCRAM_ECC			0x0038
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_SDMMC_ECC			0x0040
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB0_ECC			0x0044
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_USB1_ECC			0x0048
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_CLK_MGR			0x004c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_IO_MGR			0x0054
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_RST_MGR			0x0058
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_SYS_MGR			0x005c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC0_TIMER			0x0060
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_OSC1_TIMER			0x0064
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG0			0x0068
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG1			0x006c
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG2			0x0070
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_WATCHDOG3			0x0074
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_DAP				0x0078
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES			0x0090
+#define SOCFPGA_NOC_FW_L4_SYS_SCR_L4_NOC_QOS			0x0094
+
+#define SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0			0xf7004688
+#define SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0				0xf7018628
+
+void enable_nonsecure_access(void);
+void enable_ns_peripheral_access(void);
+void enable_ns_bridge_access(void);
+
+#endif /* SOCFPGA_SYSTEMMANAGER_H */

plat/intel/soc/common/soc/socfpga_reset_manager.c

@@ -8,9 +8,9 @@
 #include <errno.h>
 #include <lib/mmio.h>
 
-#include "s10_system_manager.h"
 #include "socfpga_mailbox.h"
 #include "socfpga_reset_manager.h"
+#include "socfpga_system_manager.h"
 
 
 void deassert_peripheral_reset(void)
@@ -107,13 +107,13 @@ int socfpga_bridges_enable(void)
 
 	if (!status) {
 		/* Clear idle request */
-		mmio_setbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_CLR), ~0);
+		mmio_setbits_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_CLR), ~0);
 
 		/* De-assert all bridges */
 		mmio_clrbits_32(SOCFPGA_RSTMGR(BRGMODRST), ~0);
 
 		/* Wait until idle ack becomes 0 */
-		poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK);
+		poll_addr = SOCFPGA_SYSMGR(NOC_IDLEACK);
 
 		return poll_idle_status(poll_addr, IDLE_DATA_MASK, 0);
 	}
@@ -125,18 +125,18 @@ int socfpga_bridges_disable(void)
 	uint32_t poll_addr;
 
 	/* Set idle request */
-	mmio_write_32(S10_SYSMGR_CORE(SYSMGR_NOC_IDLEREQ_SET), ~0);
+	mmio_write_32(SOCFPGA_SYSMGR(NOC_IDLEREQ_SET), ~0);
 
 	/* Enable NOC timeout */
-	mmio_setbits_32(SYSMGR_NOC_TIMEOUT, 1);
+	mmio_setbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1);
 
 	/* Wait until each idle ack bit toggle to 1 */
-	poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLEACK);
+	poll_addr = SOCFPGA_SYSMGR(NOC_IDLEACK);
 	if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
 		return -ETIMEDOUT;
 
 	/* Wait until each idle status bit toggle to 1 */
-	poll_addr = S10_SYSMGR_CORE(SYSMGR_NOC_IDLESTATUS);
+	poll_addr = SOCFPGA_SYSMGR(NOC_IDLESTATUS);
 	if (poll_idle_status(poll_addr, IDLE_DATA_MASK, IDLE_DATA_MASK))
 		return -ETIMEDOUT;
 
@@ -150,7 +150,7 @@ int socfpga_bridges_disable(void)
 #endif
 
 	/* Disable NOC timeout */
-	mmio_clrbits_32(S10_SYSMGR_CORE(SYSMGR_NOC_TIMEOUT), 1);
+	mmio_clrbits_32(SOCFPGA_SYSMGR(NOC_TIMEOUT), 1);
 
 	return 0;
 }

plat/intel/soc/common/soc/socfpga_system_manager.c

+/*
+ * Copyright (c) 2019, Intel Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <lib/mmio.h>
+#include <lib/utils_def.h>
+
+#include "socfpga_system_manager.h"
+
+void enable_nonsecure_access(void)
+{
+	enable_ns_peripheral_access();
+	enable_ns_bridge_access();
+}
+
+void enable_ns_peripheral_access(void)
+{
+	mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_REGISTER), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(NAND_DATA), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_ECC), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_READ_ECC), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(NAND_WRITE_ECC),
+		DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_PER_SCR(USB0_REGISTER), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(USB1_REGISTER), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(USB0_ECC), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(USB1_ECC), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_MASTER0), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_MASTER1), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_SLAVE0), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(SPI_SLAVE1), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC0), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC1), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(EMAC2), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC0RX_ECC), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC0TX_ECC), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC1RX_ECC), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC1TX_ECC), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC2RX_ECC), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(EMAC2TX_ECC), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_PER_SCR(SDMMC), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(SDMMC_ECC), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_PER_SCR(GPIO0), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(GPIO1), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_PER_SCR(I2C0), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(I2C1), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(I2C2), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(I2C3), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(I2C4), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_PER_SCR(SP_TIMER1), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_PER_SCR(UART0), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_PER_SCR(UART1), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(DMA_ECC), DISABLE_L4_FIREWALL);
+
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(OCRAM_ECC), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(CLK_MGR), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(IO_MGR), DISABLE_L4_FIREWALL);
+
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(RST_MGR), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(SYS_MGR), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(OSC0_TIMER), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(OSC1_TIMER), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG0), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG1), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG2), DISABLE_L4_FIREWALL);
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(WATCHDOG3), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(DAP), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_PROBES), DISABLE_L4_FIREWALL);
+
+	mmio_write_32(SOCFPGA_L4_SYS_SCR(L4_NOC_QOS), DISABLE_L4_FIREWALL);
+
+#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
+	mmio_clrbits_32(SOCFPGA_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
+	mmio_clrbits_32(SOCFPGA_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
+
+	mmio_write_32(SOCFPGA_SYSMGR(SDMMC), SYSMGR_SDMMC_DRVSEL(3));
+#endif
+
+}
+
+void enable_ns_bridge_access(void)
+{
+	mmio_write_32(SOCFPGA_SOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL);
+	mmio_write_32(SOCFPGA_LWSOC2FPGA_SCR_REG_BASE, DISABLE_BRIDGE_FIREWALL);
+}

plat/intel/soc/stratix10/bl2_plat_setup.c

@@ -20,10 +20,10 @@
 #include "socfpga_mailbox.h"
 #include "socfpga_private.h"
 #include "socfpga_reset_manager.h"
+#include "socfpga_system_manager.h"
 #include "s10_clock_manager.h"
 #include "s10_memory_controller.h"
 #include "s10_pinmux.h"
-#include "s10_system_manager.h"
 #include "wdt/watchdog.h"
 
 

plat/intel/soc/stratix10/bl31_plat_setup.c

@@ -18,10 +18,10 @@
 
 #include "socfpga_private.h"
 #include "socfpga_reset_manager.h"
+#include "socfpga_system_manager.h"
 #include "s10_memory_controller.h"
 #include "s10_pinmux.h"
 #include "s10_clock_manager.h"
-#include "s10_system_manager.h"
 
 
 static entry_point_info_t bl32_image_ep_info;

plat/intel/soc/stratix10/include/s10_system_manager.h

-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#define S10_FIREWALL_SOC2FPGA                   0xffd21200
-#define S10_FIREWALL_LWSOC2FPGA                 0xffd21300
-
-/* L3 Interconnect Register Map */
-#define S10_NOC_FW_L4_PER_SCR_NAND_REGISTER	0xffd21000
-#define S10_NOC_FW_L4_PER_SCR_NAND_DATA		0xffd21004
-#define S10_NOC_FW_L4_PER_SCR_USB0_REGISTER	0xffd2100c
-#define S10_NOC_FW_L4_PER_SCR_USB1_REGISTER	0xffd21010
-#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER0	0xffd2101c
-#define S10_NOC_FW_L4_PER_SCR_SPI_MASTER1	0xffd21020
-#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0	0xffd21024
-#define S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1	0xffd21028
-#define S10_NOC_FW_L4_PER_SCR_EMAC0		0xffd2102c
-#define S10_NOC_FW_L4_PER_SCR_EMAC1		0xffd21030
-#define S10_NOC_FW_L4_PER_SCR_EMAC2		0xffd21034
-#define S10_NOC_FW_L4_PER_SCR_SDMMC		0xffd21040
-#define S10_NOC_FW_L4_PER_SCR_GPIO0		0xffd21044
-#define S10_NOC_FW_L4_PER_SCR_GPIO1		0xffd21048
-#define S10_NOC_FW_L4_PER_SCR_I2C0		0xffd21050
-#define S10_NOC_FW_L4_PER_SCR_I2C1		0xffd21054
-#define S10_NOC_FW_L4_PER_SCR_I2C2		0xffd21058
-#define S10_NOC_FW_L4_PER_SCR_I2C3		0xffd2105c
-#define S10_NOC_FW_L4_PER_SCR_I2C4		0xffd21060
-#define S10_NOC_FW_L4_PER_SCR_SP_TIMER0		0xffd21064
-#define S10_NOC_FW_L4_PER_SCR_SP_TIMER1		0xffd21068
-#define S10_NOC_FW_L4_PER_SCR_UART0		0xffd2106c
-#define S10_NOC_FW_L4_PER_SCR_UART1		0xffd21070
-
-#define S10_NOC_FW_L4_SYS_SCR_DMA_ECC		0xffd21108
-#define S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC	0xffd2110c
-#define S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC	0xffd21110
-#define S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC	0xffd21114
-#define S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC	0xffd21118
-#define S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC	0xffd2111c
-#define S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC	0xffd21120
-#define S10_NOC_FW_L4_SYS_SCR_NAND_ECC		0xffd2112c
-#define S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC	0xffd21130
-#define S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC	0xffd21134
-#define S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC		0xffd21138
-#define S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC		0xffd21140
-#define S10_NOC_FW_L4_SYS_SCR_USB0_ECC		0xffd21144
-#define S10_NOC_FW_L4_SYS_SCR_USB1_ECC		0xffd21148
-#define S10_NOC_FW_L4_SYS_SCR_CLK_MGR		0xffd2114c
-#define S10_NOC_FW_L4_SYS_SCR_IO_MGR		0xffd21154
-#define S10_NOC_FW_L4_SYS_SCR_RST_MGR		0xffd21158
-#define S10_NOC_FW_L4_SYS_SCR_SYS_MGR		0xffd2115c
-#define S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER	0xffd21160
-#define S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER	0xffd21164
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG0		0xffd21168
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG1		0xffd2116c
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG2		0xffd21170
-#define S10_NOC_FW_L4_SYS_SCR_WATCHDOG3		0xffd21174
-#define S10_NOC_FW_L4_SYS_SCR_DAP		0xffd21178
-#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES	0xffd21190
-#define S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS	0xffd21194
-
-#define S10_CCU_NOC_CPU0_RAMSPACE0_0		0xf7004688
-#define S10_CCU_NOC_IOM_RAMSPACE0_0		0xf7018628
-
-/* System Manager Register Map */
-#define S10_SYSMGR_CORE(x)			(0xffd12000 + (x))
-
-#define SYSMGR_MMC				0x28
-#define SYSMGR_MMC_DRVSEL(x)			(((x) & 0x7) << 0)
-
-#define SYSMGR_NOC_TIMEOUT			0xc0
-#define SYSMGR_NOC_IDLEREQ_SET			0xc4
-#define SYSMGR_NOC_IDLEREQ_CLR			0xc8
-#define SYSMGR_NOC_IDLEREQ_VAL			0xcc
-#define SYSMGR_NOC_IDLEACK			0xd0
-#define SYSMGR_NOC_IDLESTATUS			0xd4
-
-#define IDLE_DATA_LWSOC2FPGA			BIT(0)
-#define IDLE_DATA_SOC2FPGA			BIT(4)
-#define IDLE_DATA_MASK	(IDLE_DATA_LWSOC2FPGA | IDLE_DATA_SOC2FPGA)
-
-#define SYSMGR_BOOT_SCRATCH_COLD_0		0x200
-#define SYSMGR_BOOT_SCRATCH_COLD_1		0x204
-#define SYSMGR_BOOT_SCRATCH_COLD_2		0x208
-
-#define DISABLE_BRIDGE_FIREWALL                 0x0ffe0101
-#define DISABLE_L4_FIREWALL	(BIT(0) | BIT(16) | BIT(24))
-
-void enable_nonsecure_access(void);
-void enable_ns_peripheral_access(void);
-void enable_ns_bridge_access(void);

plat/intel/soc/stratix10/include/socfpga_plat_def.h

@@ -14,7 +14,15 @@
 
 /* Register Mapping */
 #define SOCFPGA_MMC_REG_BASE                    0xff808000
+
 #define SOCFPGA_RSTMGR_REG_BASE			0xffd11000
+#define SOCFPGA_SYSMGR_REG_BASE			0xffd12000
+
+#define SOCFPGA_L4_PER_SCR_REG_BASE		0xffd21000
+#define SOCFPGA_L4_SYS_SCR_REG_BASE		0xffd21100
+#define SOCFPGA_SOC2FPGA_SCR_REG_BASE		0xffd21200
+#define SOCFPGA_LWSOC2FPGA_SCR_REG_BASE		0xffd21300
+
 
 #endif /* PLATSOCFPGA_DEF_H */
 

plat/intel/soc/stratix10/platform.mk

@@ -38,7 +38,6 @@ BL2_SOURCES     +=	\
 		plat/intel/soc/stratix10/soc/s10_clock_manager.c	\
 		plat/intel/soc/stratix10/soc/s10_memory_controller.c	\
 		plat/intel/soc/stratix10/soc/s10_pinmux.c		\
-		plat/intel/soc/stratix10/soc/s10_system_manager.c	\
                 plat/intel/soc/common/bl2_plat_mem_params_desc.c	\
 		plat/intel/soc/common/socfpga_delay_timer.c		\
 		plat/intel/soc/common/socfpga_image_load.c		\
@@ -46,6 +45,7 @@ BL2_SOURCES     +=	\
 		plat/intel/soc/common/soc/socfpga_handoff.c		\
 		plat/intel/soc/common/soc/socfpga_mailbox.c		\
 		plat/intel/soc/common/soc/socfpga_reset_manager.c	\
+		plat/intel/soc/common/soc/socfpga_system_manager.c	\
 		plat/intel/soc/common/drivers/qspi/cadence_qspi.c	\
 		plat/intel/soc/common/drivers/wdt/watchdog.c
 

plat/intel/soc/stratix10/soc/s10_clock_manager.c

@@ -12,8 +12,8 @@
 #include <platform_def.h>
 
 #include "s10_clock_manager.h"
-#include "s10_system_manager.h"
 #include "socfpga_handoff.h"
+#include "socfpga_system_manager.h"
 
 
 void wait_pll_lock(void)
@@ -190,9 +190,9 @@ void config_clkmgr_handoff(handoff *hoff_ptr)
 			ALT_CLKMGR_INTRCLR_PERLOCKLOST_SET_MSK);
 
 	/* Pass clock source frequency into scratch register */
-	mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1),
+	mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1),
 			hoff_ptr->hps_osc_clk_h);
-	mmio_write_32(S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2),
+	mmio_write_32(SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2),
 			hoff_ptr->fpga_clk_hz);
 
 }
@@ -205,14 +205,14 @@ uint32_t get_ref_clk(uint32_t pllglob)
 
 	switch (ALT_CLKMGR_PSRC(pllglob)) {
 	case ALT_CLKMGR_PLLGLOB_PSRC_EOSC1:
-		scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_1);
+		scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_1);
 		ref_clk = mmio_read_32(scr_reg);
 		break;
 	case ALT_CLKMGR_PLLGLOB_PSRC_INTOSC:
 		ref_clk = ALT_CLKMGR_INTOSC_HZ;
 		break;
 	case ALT_CLKMGR_PLLGLOB_PSRC_F2S:
-		scr_reg = S10_SYSMGR_CORE(SYSMGR_BOOT_SCRATCH_COLD_2);
+		scr_reg = SOCFPGA_SYSMGR(BOOT_SCRATCH_COLD_2);
 		ref_clk = mmio_read_32(scr_reg);
 		break;
 	default:

plat/intel/soc/stratix10/soc/s10_system_manager.c

-/*
- * Copyright (c) 2019, Intel Corporation. All rights reserved.
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <lib/mmio.h>
-#include <lib/utils_def.h>
-#include "s10_system_manager.h"
-
-void enable_nonsecure_access(void)
-{
-	enable_ns_peripheral_access();
-	enable_ns_bridge_access();
-}
-
-void enable_ns_peripheral_access(void)
-{
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_REGISTER, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_NAND_DATA, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_READ_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_NAND_WRITE_ECC,
-		DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB0_REGISTER, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_USB1_REGISTER, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB0_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_USB1_ECC, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_MASTER1, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_SPI_SLAVE1, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC1, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_EMAC2, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0RX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC0TX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1RX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC1TX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2RX_ECC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_EMAC2TX_ECC, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_SDMMC, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SDMMC_ECC, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_GPIO1, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C1, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C2, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C3, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_I2C4, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_SP_TIMER1, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_PER_SCR_UART1, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DMA_ECC, DISABLE_L4_FIREWALL);
-
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OCRAM_ECC, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_CLK_MGR, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_IO_MGR, DISABLE_L4_FIREWALL);
-
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_RST_MGR, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_SYS_MGR, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC0_TIMER, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_OSC1_TIMER, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG0, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG1, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG2, DISABLE_L4_FIREWALL);
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_WATCHDOG3, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_DAP, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_PROBES, DISABLE_L4_FIREWALL);
-
-	mmio_write_32(S10_NOC_FW_L4_SYS_SCR_L4_NOC_QOS, DISABLE_L4_FIREWALL);
-
-	mmio_clrbits_32(S10_CCU_NOC_CPU0_RAMSPACE0_0, 0x03);
-	mmio_clrbits_32(S10_CCU_NOC_IOM_RAMSPACE0_0, 0x03);
-
-	mmio_write_32(S10_SYSMGR_CORE(SYSMGR_MMC), SYSMGR_MMC_DRVSEL(3));
-
-}
-
-void enable_ns_bridge_access(void)
-{
-	mmio_write_32(S10_FIREWALL_SOC2FPGA, DISABLE_BRIDGE_FIREWALL);
-	mmio_write_32(S10_FIREWALL_LWSOC2FPGA, DISABLE_BRIDGE_FIREWALL);
-}