Merge changes I99a5d96f,I89b950f0 into integration

* changes:
  lib/cpus: update MIDR value for rainier cpu
  fdts: enable virtio-rng component for morello fvp platform

fdts/morello-fvp.dts

@@ -80,6 +80,12 @@
 		interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 	};
 
+	virtio_rng@1c190000 {
+		compatible = "virtio,mmio","virtio-rng";
+		reg = <0x0 0x1c190000 0x0 0x200>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+	};
+
 	ethernet@1d100000 {
 		compatible = "smsc,lan91c111";
 		reg = <0x0 0x1d100000 0x0 0x10000>;

include/lib/cpus/aarch64/rainier.h

@@ -10,7 +10,7 @@
 #include <lib/utils_def.h>
 
 /* RAINIER MIDR for revision 0 */
-#define RAINIER_MIDR			U(0x3f0f4100)
+#define RAINIER_MIDR			U(0x3f0f4120)
 
 /* Exception Syndrome register EC code for IC Trap */
 #define RAINIER_EC_IC_TRAP		U(0x1f)