Merge pull request #112 from danh-arm:dh/refactor-plat-header-v4 into for-v0.4

include/plat/common/platform.h

+/*
+ * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * Redistributions of source code must retain the above copyright notice, this
+ * list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * Neither the name of ARM nor the names of its contributors may be used
+ * to endorse or promote products derived from this software without specific
+ * prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+#include <stdint.h>
+
+
+/*******************************************************************************
+ * Forward declarations
+ ******************************************************************************/
+struct plat_pm_ops;
+struct meminfo;
+struct image_info;
+struct entry_point_info;
+struct bl31_params;
+
+/*******************************************************************************
+ * Function declarations
+ ******************************************************************************/
+/*******************************************************************************
+ * Mandatory common functions
+ ******************************************************************************/
+uint64_t plat_get_syscnt_freq(void);
+int plat_get_image_source(const char *image_name,
+			uintptr_t *dev_handle,
+			uintptr_t *image_spec);
+unsigned long plat_get_ns_image_entrypoint(void);
+
+/*******************************************************************************
+ * Mandatory interrupt management functions
+ ******************************************************************************/
+uint32_t plat_ic_get_pending_interrupt_id(void);
+uint32_t plat_ic_get_pending_interrupt_type(void);
+uint32_t plat_ic_acknowledge_interrupt(void);
+uint32_t plat_ic_get_interrupt_type(uint32_t id);
+void plat_ic_end_of_interrupt(uint32_t id);
+uint32_t plat_interrupt_type_to_line(uint32_t type,
+				     uint32_t security_state);
+
+/*******************************************************************************
+ * Optional common functions (may be overridden)
+ ******************************************************************************/
+unsigned int platform_get_core_pos(unsigned long mpidr);
+unsigned long platform_get_stack(unsigned long mpidr);
+void plat_report_exception(unsigned long);
+
+/*******************************************************************************
+ * Mandatory BL1 functions
+ ******************************************************************************/
+void bl1_plat_arch_setup(void);
+void bl1_platform_setup(void);
+struct meminfo *bl1_plat_sec_mem_layout(void);
+
+/*
+ * This function allows the platform to change the entrypoint information for
+ * BL2, after BL1 has loaded BL2 into memory but before BL2 is executed.
+ */
+void bl1_plat_set_bl2_ep_info(struct image_info *image,
+			      struct entry_point_info *ep);
+
+/*******************************************************************************
+ * Optional BL1 functions (may be overridden)
+ ******************************************************************************/
+void init_bl2_mem_layout(struct meminfo *,
+			struct meminfo *,
+			unsigned int,
+			unsigned long);
+
+/*******************************************************************************
+ * Mandatory BL2 functions
+ ******************************************************************************/
+void bl2_plat_arch_setup(void);
+void bl2_platform_setup(void);
+struct meminfo *bl2_plat_sec_mem_layout(void);
+
+/*
+ * This function returns a pointer to the shared memory that the platform has
+ * kept aside to pass trusted firmware related information that BL3-1
+ * could need
+ */
+struct bl31_params *bl2_plat_get_bl31_params(void);
+
+/*
+ * This function returns a pointer to the shared memory that the platform
+ * has kept to point to entry point information of BL31 to BL2
+ */
+struct entry_point_info *bl2_plat_get_bl31_ep_info(void);
+
+/*
+ * This function flushes to main memory all the params that are
+ * passed to BL3-1
+ */
+void bl2_plat_flush_bl31_params(void);
+
+/*
+ * The next 3 functions allow the platform to change the entrypoint
+ * information for the 3rd level BL images, after BL2 has loaded the 3rd
+ * level BL images into memory but before BL3-1 is executed.
+ */
+void bl2_plat_set_bl31_ep_info(struct image_info *image,
+			       struct entry_point_info *ep);
+
+void bl2_plat_set_bl32_ep_info(struct image_info *image,
+			       struct entry_point_info *ep);
+
+void bl2_plat_set_bl33_ep_info(struct image_info *image,
+			       struct entry_point_info *ep);
+
+/* Gets the memory layout for BL32 */
+void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info);
+
+/* Gets the memory layout for BL33 */
+void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info);
+
+/*******************************************************************************
+ * Optional BL2 functions (may be overridden)
+ ******************************************************************************/
+
+/*******************************************************************************
+ * Mandatory BL3-1 functions
+ ******************************************************************************/
+void bl31_early_platform_setup(struct bl31_params *from_bl2,
+				void *plat_params_from_bl2);
+void bl31_plat_arch_setup(void);
+void bl31_platform_setup(void);
+struct entry_point_info *bl31_plat_get_next_image_ep_info(uint32_t type);
+
+/*******************************************************************************
+ * Mandatory PSCI functions (BL3-1)
+ ******************************************************************************/
+int platform_setup_pm(const struct plat_pm_ops **);
+int plat_get_max_afflvl(void);
+unsigned int plat_get_aff_count(unsigned int, unsigned long);
+unsigned int plat_get_aff_state(unsigned int, unsigned long);
+
+/*******************************************************************************
+ * Optional BL3-1 functions (may be overridden)
+ ******************************************************************************/
+void bl31_plat_enable_mmu();
+
+/*******************************************************************************
+ * Mandatory BL3-2 functions (only if platform contains a BL3-2)
+ ******************************************************************************/
+void bl32_platform_setup(void);
+
+/*******************************************************************************
+ * Optional BL3-2 functions (may be overridden)
+ ******************************************************************************/
+void bl32_plat_enable_mmu();
+
+#endif /* __PLATFORM_H__ */

lib/aarch64/xlat_tables.c

@@ -28,8 +28,10 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include <arch.h>
+#include <arch_helpers.h>
 #include <assert.h>
-#include <platform.h>
+#include <platform_def.h>
 #include <string.h>
 #include <xlat_tables.h>
 
@@ -49,7 +51,7 @@
 
 #define NUM_L1_ENTRIES (ADDR_SPACE_SIZE >> L1_XLAT_ADDRESS_SHIFT)
 
-uint64_t l1_xlation_table[NUM_L1_ENTRIES]
+static uint64_t l1_xlation_table[NUM_L1_ENTRIES]
 __aligned(NUM_L1_ENTRIES * sizeof(uint64_t));
 
 static uint64_t xlat_tables[MAX_XLAT_TABLES][XLAT_TABLE_ENTRIES]
@@ -226,3 +228,62 @@ void init_xlat_tables(void)
 	print_mmap();
 	init_xlation_table(mmap, 0, l1_xlation_table, 1);
 }
+
+/*******************************************************************************
+ * Macro generating the code for the function enabling the MMU in the given
+ * exception level, assuming that the pagetables have already been created.
+ *
+ *   _el:		Exception level at which the function will run
+ *   _tcr_extra:	Extra bits to set in the TCR register. This mask will
+ *			be OR'ed with the default TCR value.
+ *   _tlbi_fct:		Function to invalidate the TLBs at the current
+ *			exception level
+ ******************************************************************************/
+#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct)		\
+	void enable_mmu_el##_el(void)					\
+	{								\
+		uint64_t mair, tcr, ttbr;				\
+		uint32_t sctlr;						\
+									\
+		assert(IS_IN_EL(_el));					\
+		assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0);	\
+									\
+		/* Set attributes in the right indices of the MAIR */	\
+		mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);	\
+		mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,		\
+				ATTR_IWBWA_OWBWA_NTR_INDEX);		\
+		write_mair_el##_el(mair);				\
+									\
+		/* Invalidate TLBs at the current exception level */	\
+		_tlbi_fct();						\
+									\
+		/* Set TCR bits as well. */				\
+		/* Inner & outer WBWA & shareable + T0SZ = 32 */	\
+		tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA |	\
+			TCR_RGN_INNER_WBA | TCR_T0SZ_4GB;		\
+		tcr |= _tcr_extra;					\
+		write_tcr_el##_el(tcr);					\
+									\
+		/* Set TTBR bits as well */				\
+		ttbr = (uint64_t) l1_xlation_table;			\
+		write_ttbr0_el##_el(ttbr);				\
+									\
+		/* Ensure all translation table writes have drained */	\
+		/* into memory, the TLB invalidation is complete, */	\
+		/* and translation register writes are committed */	\
+		/* before enabling the MMU */				\
+		dsb();							\
+		isb();							\
+									\
+		sctlr = read_sctlr_el##_el();				\
+		sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT;	\
+		sctlr |= SCTLR_A_BIT | SCTLR_C_BIT;			\
+		write_sctlr_el##_el(sctlr);				\
+									\
+		/* Ensure the MMU enable takes effect immediately */	\
+		isb();							\
+	}
+
+/* Define EL1 and EL3 variants of the function enabling the MMU */
+DEFINE_ENABLE_MMU_EL(1, 0, tlbivmalle1)
+DEFINE_ENABLE_MMU_EL(3, TCR_EL3_RES1, tlbialle3)

lib/locks/bakery/bakery_lock.c

@@ -31,6 +31,7 @@
 #include <arch_helpers.h>
 #include <assert.h>
 #include <bakery_lock.h>
+#include <platform.h>
 #include <string.h>
 
 /*

lib/semihosting/semihosting.c

@@ -37,8 +37,8 @@
 #define SEMIHOSTING_SUPPORTED  1
 #endif
 
-extern long semihosting_call(unsigned long operation,
-			    void *system_block_address);
+long semihosting_call(unsigned long operation,
+			void *system_block_address);
 
 typedef struct {
 	const char *file_name;

include/bl1/bl1.h → plat/common/aarch64/plat_common.c

 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -28,19 +28,22 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __BL1_H__
-#define __BL1_H__
+#include <xlat_tables.h>
 
+/*
+ * The following 2 platform setup functions are weakly defined. They
+ * provide typical implementations that may be re-used by multiple
+ * platforms but may also be overridden by a platform if required.
+ */
+#pragma weak bl31_plat_enable_mmu
+#pragma weak bl32_plat_enable_mmu
 
-/******************************************
- * Forward declarations
- *****************************************/
-struct meminfo;
-
-/******************************************
- * Function prototypes
- *****************************************/
-extern void bl1_platform_setup(void);
-extern struct meminfo *bl1_plat_sec_mem_layout(void);
+void bl31_plat_enable_mmu()
+{
+	enable_mmu_el3();
+}
 
-#endif /* __BL1_H__ */
+void bl32_plat_enable_mmu()
+{
+	enable_mmu_el1();
+}

plat/common/aarch64/platform_helpers.S

@@ -30,7 +30,7 @@
 
 #include <arch.h>
 #include <asm_macros.S>
-#include <platform.h>
+#include <platform_def.h>
 
 
 	.weak	platform_get_core_pos

plat/common/aarch64/platform_mp_stack.S

@@ -30,7 +30,7 @@
 
 #include <arch.h>
 #include <asm_macros.S>
-#include <platform.h>
+#include <platform_def.h>
 
 
 	.local	pcpu_dv_mem_stack

plat/common/aarch64/platform_up_stack.S

@@ -30,7 +30,7 @@
 
 #include <arch.h>
 #include <asm_macros.S>
-#include <platform.h>
+#include <platform_def.h>
 
 
 	.local	pcpu_dv_mem_stack

plat/fvp/aarch64/plat_common.c → plat/fvp/aarch64/fvp_common.c

@@ -37,6 +37,7 @@
 #include <mmio.h>
 #include <platform.h>
 #include <xlat_tables.h>
+#include "../fvp_def.h"
 
 /*******************************************************************************
  * This array holds the characteristics of the differences between the three
@@ -45,66 +46,7 @@
  * configuration) & used thereafter. Each BL will have its own copy to allow
  * independent operation.
  ******************************************************************************/
-static unsigned long platform_config[CONFIG_LIMIT];
-
-/*******************************************************************************
- * Macro generating the code for the function enabling the MMU in the given
- * exception level, assuming that the pagetables have already been created.
- *
- *   _el:		Exception level at which the function will run
- *   _tcr_extra:	Extra bits to set in the TCR register. This mask will
- *			be OR'ed with the default TCR value.
- *   _tlbi_fct:		Function to invalidate the TLBs at the current
- *			exception level
- ******************************************************************************/
-#define DEFINE_ENABLE_MMU_EL(_el, _tcr_extra, _tlbi_fct)		\
-	void enable_mmu_el##_el(void)					\
-	{								\
-		uint64_t mair, tcr, ttbr;				\
-		uint32_t sctlr;						\
-									\
-		assert(IS_IN_EL(_el));					\
-		assert((read_sctlr_el##_el() & SCTLR_M_BIT) == 0);	\
-									\
-		/* Set attributes in the right indices of the MAIR */	\
-		mair = MAIR_ATTR_SET(ATTR_DEVICE, ATTR_DEVICE_INDEX);	\
-		mair |= MAIR_ATTR_SET(ATTR_IWBWA_OWBWA_NTR,		\
-				ATTR_IWBWA_OWBWA_NTR_INDEX);		\
-		write_mair_el##_el(mair);				\
-									\
-		/* Invalidate TLBs at the current exception level */	\
-		_tlbi_fct();						\
-									\
-		/* Set TCR bits as well. */				\
-		/* Inner & outer WBWA & shareable + T0SZ = 32 */	\
-		tcr = TCR_SH_INNER_SHAREABLE | TCR_RGN_OUTER_WBA |	\
-			TCR_RGN_INNER_WBA | TCR_T0SZ_4GB;		\
-		tcr |= _tcr_extra;					\
-		write_tcr_el##_el(tcr);					\
-									\
-		/* Set TTBR bits as well */				\
-		ttbr = (uint64_t) l1_xlation_table;			\
-		write_ttbr0_el##_el(ttbr);				\
-									\
-		/* Ensure all translation table writes have drained */	\
-		/* into memory, the TLB invalidation is complete, */	\
-		/* and translation register writes are committed */	\
-		/* before enabling the MMU */				\
-		dsb();							\
-		isb();							\
-									\
-		sctlr = read_sctlr_el##_el();				\
-		sctlr |= SCTLR_WXN_BIT | SCTLR_M_BIT | SCTLR_I_BIT;	\
-		sctlr |= SCTLR_A_BIT | SCTLR_C_BIT;			\
-		write_sctlr_el##_el(sctlr);				\
-									\
-		/* Ensure the MMU enable takes effect immediately */	\
-		isb();							\
-	}
-
-/* Define EL1 and EL3 variants of the function enabling the MMU */
-DEFINE_ENABLE_MMU_EL(1, 0, tlbivmalle1)
-DEFINE_ENABLE_MMU_EL(3, TCR_EL3_RES1, tlbialle3)
+static unsigned long fvp_config[CONFIG_LIMIT];
 
 /*
  * Table of regions to map using the MMU.
@@ -131,7 +73,7 @@ const mmap_region_t fvp_mmap[] = {
  * the platform memory map & initialize the mmu, for the given exception level
  ******************************************************************************/
 #define DEFINE_CONFIGURE_MMU_EL(_el)					\
-	void configure_mmu_el##_el(unsigned long total_base,		\
+	void fvp_configure_mmu_el##_el(unsigned long total_base,		\
 				   unsigned long total_size,		\
 				   unsigned long ro_start,		\
 				   unsigned long ro_limit,		\
@@ -156,10 +98,10 @@ DEFINE_CONFIGURE_MMU_EL(1)
 DEFINE_CONFIGURE_MMU_EL(3)
 
 /* Simple routine which returns a configuration variable value */
-unsigned long platform_get_cfgvar(unsigned int var_id)
+unsigned long fvp_get_cfgvar(unsigned int var_id)
 {
 	assert(var_id < CONFIG_LIMIT);
-	return platform_config[var_id];
+	return fvp_config[var_id];
 }
 
 /*******************************************************************************
@@ -169,7 +111,7 @@ unsigned long platform_get_cfgvar(unsigned int var_id)
  * these platforms. This information is stored in a per-BL array to allow the
  * code to take the correct path.Per BL platform configuration.
  ******************************************************************************/
-int platform_config_setup(void)
+int fvp_config_setup(void)
 {
 	unsigned int rev, hbi, bld, arch, sys_id, midr_pn;
 
@@ -188,16 +130,16 @@ int platform_config_setup(void)
 	 */
 	switch (bld) {
 	case BLD_GIC_VE_MMAP:
-		platform_config[CONFIG_GICD_ADDR] = VE_GICD_BASE;
-		platform_config[CONFIG_GICC_ADDR] = VE_GICC_BASE;
-		platform_config[CONFIG_GICH_ADDR] = VE_GICH_BASE;
-		platform_config[CONFIG_GICV_ADDR] = VE_GICV_BASE;
+		fvp_config[CONFIG_GICD_ADDR] = VE_GICD_BASE;
+		fvp_config[CONFIG_GICC_ADDR] = VE_GICC_BASE;
+		fvp_config[CONFIG_GICH_ADDR] = VE_GICH_BASE;
+		fvp_config[CONFIG_GICV_ADDR] = VE_GICV_BASE;
 		break;
 	case BLD_GIC_A53A57_MMAP:
-		platform_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE;
-		platform_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE;
-		platform_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE;
-		platform_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE;
+		fvp_config[CONFIG_GICD_ADDR] = BASE_GICD_BASE;
+		fvp_config[CONFIG_GICC_ADDR] = BASE_GICC_BASE;
+		fvp_config[CONFIG_GICH_ADDR] = BASE_GICH_BASE;
+		fvp_config[CONFIG_GICV_ADDR] = BASE_GICV_BASE;
 		break;
 	default:
 		assert(0);
@@ -209,25 +151,25 @@ int platform_config_setup(void)
 	 */
 	switch (hbi) {
 	case HBI_FOUNDATION:
-		platform_config[CONFIG_MAX_AFF0] = 4;
-		platform_config[CONFIG_MAX_AFF1] = 1;
-		platform_config[CONFIG_CPU_SETUP] = 0;
-		platform_config[CONFIG_BASE_MMAP] = 0;
-		platform_config[CONFIG_HAS_CCI] = 0;
-		platform_config[CONFIG_HAS_TZC] = 0;
+		fvp_config[CONFIG_MAX_AFF0] = 4;
+		fvp_config[CONFIG_MAX_AFF1] = 1;
+		fvp_config[CONFIG_CPU_SETUP] = 0;
+		fvp_config[CONFIG_BASE_MMAP] = 0;
+		fvp_config[CONFIG_HAS_CCI] = 0;
+		fvp_config[CONFIG_HAS_TZC] = 0;
 		break;
 	case HBI_FVP_BASE:
 		midr_pn = (read_midr() >> MIDR_PN_SHIFT) & MIDR_PN_MASK;
 		if ((midr_pn == MIDR_PN_A57) || (midr_pn == MIDR_PN_A53))
-			platform_config[CONFIG_CPU_SETUP] = 1;
+			fvp_config[CONFIG_CPU_SETUP] = 1;
 		else
-			platform_config[CONFIG_CPU_SETUP] = 0;
+			fvp_config[CONFIG_CPU_SETUP] = 0;
 
-		platform_config[CONFIG_MAX_AFF0] = 4;
-		platform_config[CONFIG_MAX_AFF1] = 2;
-		platform_config[CONFIG_BASE_MMAP] = 1;
-		platform_config[CONFIG_HAS_CCI] = 1;
-		platform_config[CONFIG_HAS_TZC] = 1;
+		fvp_config[CONFIG_MAX_AFF0] = 4;
+		fvp_config[CONFIG_MAX_AFF1] = 2;
+		fvp_config[CONFIG_BASE_MMAP] = 1;
+		fvp_config[CONFIG_HAS_CCI] = 1;
+		fvp_config[CONFIG_HAS_TZC] = 1;
 		break;
 	default:
 		assert(0);
@@ -263,7 +205,7 @@ void fvp_cci_setup(void)
 	 * for locks as no other cpu is active at the
 	 * moment
 	 */
-	cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+	cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
 	if (cci_setup)
 		cci_enable_coherency(read_mpidr());
 }

plat/fvp/aarch64/plat_helpers.S → plat/fvp/aarch64/fvp_helpers.S

@@ -32,15 +32,15 @@
 #include <asm_macros.S>
 #include <bl_common.h>
 #include <gic_v2.h>
-#include <platform.h>
 #include "../drivers/pwrc/fvp_pwrc.h"
+#include "../fvp_def.h"
 
 	.globl	platform_get_entrypoint
 	.globl	plat_secondary_cold_boot_setup
 	.globl	platform_mem_init
 	.globl	plat_report_exception
 
-	.macro	platform_choose_gicmmap  param1, param2, x_tmp, w_tmp, res
+	.macro	fvp_choose_gicmmap  param1, param2, x_tmp, w_tmp, res
 	ldr	\x_tmp, =VE_SYSREGS_BASE + V2M_SYS_ID
 	ldr	\w_tmp, [\x_tmp]
 	ubfx	\w_tmp, \w_tmp, #SYS_ID_BLD_SHIFT, #SYS_ID_BLD_LENGTH
@@ -78,7 +78,7 @@ func plat_secondary_cold_boot_setup
 	 */
 	ldr	x0, =VE_GICC_BASE
 	ldr	x1, =BASE_GICC_BASE
-	platform_choose_gicmmap	x0, x1, x2, w2, x1
+	fvp_choose_gicmmap	x0, x1, x2, w2, x1
 	mov	w0, #(IRQ_BYP_DIS_GRP1 | FIQ_BYP_DIS_GRP1)
 	orr	w0, w0, #(IRQ_BYP_DIS_GRP0 | FIQ_BYP_DIS_GRP0)
 	str	w0, [x1, #GICC_CTLR]

plat/fvp/bl1_plat_setup.c → plat/fvp/bl1_fvp_setup.c

@@ -31,10 +31,12 @@
 #include <arch_helpers.h>
 #include <assert.h>
 #include <bl_common.h>
-#include <bl1.h>
 #include <console.h>
 #include <mmio.h>
 #include <platform.h>
+#include <platform_def.h>
+#include "fvp_def.h"
+#include "fvp_private.h"
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
@@ -103,7 +105,7 @@ void bl1_early_platform_setup(void)
 	}
 
 	/* Initialize the platform config for future decision making */
-	platform_config_setup();
+	fvp_config_setup();
 }
 
 /*******************************************************************************
@@ -114,7 +116,7 @@ void bl1_early_platform_setup(void)
 void bl1_platform_setup(void)
 {
 	/* Initialise the IO layer and register platform IO devices */
-	io_setup();
+	fvp_io_setup();
 }
 
 
@@ -127,12 +129,12 @@ void bl1_plat_arch_setup(void)
 {
 	fvp_cci_setup();
 
-	configure_mmu_el3(bl1_tzram_layout.total_base,
-			  bl1_tzram_layout.total_size,
-			  TZROM_BASE,
-			  TZROM_BASE + TZROM_SIZE,
-			  BL1_COHERENT_RAM_BASE,
-			  BL1_COHERENT_RAM_LIMIT);
+	fvp_configure_mmu_el3(bl1_tzram_layout.total_base,
+			      bl1_tzram_layout.total_size,
+			      TZROM_BASE,
+			      TZROM_BASE + TZROM_SIZE,
+			      BL1_COHERENT_RAM_BASE,
+			      BL1_COHERENT_RAM_LIMIT);
 }
 
 

plat/fvp/bl2_plat_setup.c → plat/fvp/bl2_fvp_setup.c

@@ -31,10 +31,12 @@
 #include <arch_helpers.h>
 #include <assert.h>
 #include <bl_common.h>
-#include <bl2.h>
 #include <console.h>
 #include <platform.h>
+#include <platform_def.h>
 #include <string.h>
+#include "fvp_def.h"
+#include "fvp_private.h"
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
@@ -177,7 +179,7 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
 	bl2_tzram_layout.next = 0;
 
 	/* Initialize the platform config for future decision making */
-	platform_config_setup();
+	fvp_config_setup();
 }
 
 /*******************************************************************************
@@ -192,10 +194,10 @@ void bl2_platform_setup(void)
 	 * other platforms might have more programmable security devices
 	 * present.
 	 */
-	plat_security_setup();
+	fvp_security_setup();
 
 	/* Initialise the IO layer and register platform IO devices */
-	io_setup();
+	fvp_io_setup();
 }
 
 /* Flush the TF params and the TF plat params */
@@ -212,12 +214,12 @@ void bl2_plat_flush_bl31_params(void)
  ******************************************************************************/
 void bl2_plat_arch_setup()
 {
-	configure_mmu_el1(bl2_tzram_layout.total_base,
-			  bl2_tzram_layout.total_size,
-			  BL2_RO_BASE,
-			  BL2_RO_LIMIT,
-			  BL2_COHERENT_RAM_BASE,
-			  BL2_COHERENT_RAM_LIMIT);
+	fvp_configure_mmu_el1(bl2_tzram_layout.total_base,
+			      bl2_tzram_layout.total_size,
+			      BL2_RO_BASE,
+			      BL2_RO_LIMIT,
+			      BL2_COHERENT_RAM_BASE,
+			      BL2_COHERENT_RAM_LIMIT);
 }
 
 /*******************************************************************************

plat/fvp/bl31_plat_setup.c → plat/fvp/bl31_fvp_setup.c

@@ -38,6 +38,8 @@
 #include <platform.h>
 #include <stddef.h>
 #include "drivers/pwrc/fvp_pwrc.h"
+#include "fvp_def.h"
+#include "fvp_private.h"
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
@@ -86,16 +88,16 @@ static bl31_params_t *bl2_to_bl31_params;
  * while BL32 corresponds to the secure image type. A NULL pointer is returned
  * if the image does not exist.
  ******************************************************************************/
-entry_point_info_t *bl31_get_next_image_info(uint32_t type)
+entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
 {
 	entry_point_info_t *next_image_info;
 
 #if RESET_TO_BL31
 
 	if (type == NON_SECURE)
-		plat_get_entry_point_info(NON_SECURE, &bl33_entrypoint_info);
+		fvp_get_entry_point_info(NON_SECURE, &bl33_entrypoint_info);
 	else
-		plat_get_entry_point_info(SECURE, &bl32_entrypoint_info);
+		fvp_get_entry_point_info(SECURE, &bl32_entrypoint_info);
 
 	next_image_info = (type == NON_SECURE) ?
 		&bl33_entrypoint_info :
@@ -132,7 +134,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 	console_init(PL011_UART0_BASE);
 
 	/* Initialize the platform config for future decision making */
-	platform_config_setup();
+	fvp_config_setup();
 
 #if RESET_TO_BL31
 	/* There are no parameters from BL2 if BL31 is a reset vector */
@@ -146,7 +148,7 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 	 * other platforms might have more programmable security devices
 	 * present.
 	 */
-	plat_security_setup();
+	fvp_security_setup();
 #else
 	/* Check params passed from BL2 should not be NULL,
 	 * We are not checking plat_params_from_bl2 as NULL as we are not
@@ -197,7 +199,7 @@ void bl31_platform_setup()
 	fvp_pwrc_setup();
 
 	/* Topologies are best known to the platform. */
-	plat_setup_topology();
+	fvp_setup_topology();
 }
 
 /*******************************************************************************
@@ -208,14 +210,14 @@ void bl31_plat_arch_setup()
 {
 #if RESET_TO_BL31
 	fvp_cci_setup();
-#endif
 
-	configure_mmu_el3(BL31_RO_BASE,
-			  (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
-			  BL31_RO_BASE,
-			  BL31_RO_LIMIT,
-			  BL31_COHERENT_RAM_BASE,
-			  BL31_COHERENT_RAM_LIMIT);
+#endif
+	fvp_configure_mmu_el3(BL31_RO_BASE,
+			      (BL31_COHERENT_RAM_LIMIT - BL31_RO_BASE),
+			      BL31_RO_BASE,
+			      BL31_RO_LIMIT,
+			      BL31_COHERENT_RAM_BASE,
+			      BL31_COHERENT_RAM_LIMIT);
 }
 
 #if RESET_TO_BL31
@@ -223,7 +225,7 @@ void bl31_plat_arch_setup()
  * Generate the entry point info for Non Secure and Secure images
  * for transferring control from BL31
  ******************************************************************************/
-void plat_get_entry_point_info(unsigned long target_security,
+void fvp_get_entry_point_info(unsigned long target_security,
 					entry_point_info_t *target_entry_info)
 {
 	if (target_security == NON_SECURE) {

plat/fvp/bl32_plat_setup.c → plat/fvp/bl32_fvp_setup.c

@@ -28,11 +28,11 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include <arch_helpers.h>
 #include <bl_common.h>
-#include <bl32.h>
 #include <console.h>
 #include <platform.h>
+#include "fvp_def.h"
+#include "fvp_private.h"
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
@@ -75,7 +75,7 @@ void bl32_early_platform_setup(void)
 	console_init(PL011_UART1_BASE);
 
 	/* Initialize the platform config for future decision making */
-	platform_config_setup();
+	fvp_config_setup();
 }
 
 /*******************************************************************************
@@ -92,10 +92,10 @@ void bl32_platform_setup()
  ******************************************************************************/
 void bl32_plat_arch_setup()
 {
-	configure_mmu_el1(BL32_RO_BASE,
-			  (BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
-			  BL32_RO_BASE,
-			  BL32_RO_LIMIT,
-			  BL32_COHERENT_RAM_BASE,
-			  BL32_COHERENT_RAM_LIMIT);
+	fvp_configure_mmu_el1(BL32_RO_BASE,
+			      (BL32_COHERENT_RAM_LIMIT - BL32_RO_BASE),
+			      BL32_RO_BASE,
+			      BL32_RO_LIMIT,
+			      BL32_COHERENT_RAM_BASE,
+			      BL32_COHERENT_RAM_LIMIT);
 }

plat/fvp/drivers/pwrc/fvp_pwrc.c

@@ -30,6 +30,7 @@
 
 #include <bakery_lock.h>
 #include <mmio.h>
+#include "../../fvp_def.h"
 #include "fvp_pwrc.h"
 
 /*

plat/fvp/drivers/pwrc/fvp_pwrc.h

@@ -63,14 +63,14 @@
 /*******************************************************************************
  * Function & variable prototypes
  ******************************************************************************/
-extern int fvp_pwrc_setup(void);
-extern void fvp_pwrc_write_pcoffr(unsigned long);
-extern void fvp_pwrc_write_ppoffr(unsigned long);
-extern void fvp_pwrc_write_pponr(unsigned long);
-extern void fvp_pwrc_set_wen(unsigned long);
-extern void fvp_pwrc_clr_wen(unsigned long);
-extern unsigned int fvp_pwrc_read_psysr(unsigned long);
-extern unsigned int fvp_pwrc_get_cpu_wkr(unsigned long);
+int fvp_pwrc_setup(void);
+void fvp_pwrc_write_pcoffr(unsigned long);
+void fvp_pwrc_write_ppoffr(unsigned long);
+void fvp_pwrc_write_pponr(unsigned long);
+void fvp_pwrc_set_wen(unsigned long);
+void fvp_pwrc_clr_wen(unsigned long);
+unsigned int fvp_pwrc_read_psysr(unsigned long);
+unsigned int fvp_pwrc_get_cpu_wkr(unsigned long);
 
 #endif /*__ASSEMBLY__*/
 

plat/fvp/platform.h → plat/fvp/fvp_def.h

 /*
- * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2014, ARM Limited and Contributors. All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions are met:
@@ -28,62 +28,15 @@
  * POSSIBILITY OF SUCH DAMAGE.
  */
 
-#ifndef __PLATFORM_H__
-#define __PLATFORM_H__
+#ifndef __FVP_DEF_H__
+#define __FVP_DEF_H__
 
-#include <arch.h>
-#include <bl_common.h>
+#include <platform_def.h> /* for TZROM_SIZE */
 
 
-/*******************************************************************************
- * Platform binary types for linking
- ******************************************************************************/
-#define PLATFORM_LINKER_FORMAT          "elf64-littleaarch64"
-#define PLATFORM_LINKER_ARCH            aarch64
-
-/*******************************************************************************
- * Generic platform constants
- ******************************************************************************/
-
-/* Size of cacheable stacks */
-#define PLATFORM_STACK_SIZE	0x800
-
-/* Size of coherent stacks for debug and release builds */
-#if DEBUG
-#define PCPU_DV_MEM_STACK_SIZE	0x400
-#else
-#define PCPU_DV_MEM_STACK_SIZE	0x300
-#endif
-
-#define FIRMWARE_WELCOME_STR		"Booting trusted firmware boot loader stage 1\n\r"
-
-/* Trusted Boot Firmware BL2 */
-#define BL2_IMAGE_NAME			"bl2.bin"
-
-/* EL3 Runtime Firmware BL31 */
-#define BL31_IMAGE_NAME			"bl31.bin"
-
-/* Secure Payload BL32 (Trusted OS) */
-#define BL32_IMAGE_NAME			"bl32.bin"
-
-/* Non-Trusted Firmware BL33 and its load address */
-#define BL33_IMAGE_NAME			"bl33.bin" /* e.g. UEFI */
-#define NS_IMAGE_OFFSET			(DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
-
 /* Firmware Image Package */
 #define FIP_IMAGE_NAME			"fip.bin"
 
-#define PLATFORM_CACHE_LINE_SIZE	64
-#define PLATFORM_CLUSTER_COUNT		2ull
-#define PLATFORM_CLUSTER0_CORE_COUNT	4
-#define PLATFORM_CLUSTER1_CORE_COUNT	4
-#define PLATFORM_CORE_COUNT		(PLATFORM_CLUSTER1_CORE_COUNT + \
-						PLATFORM_CLUSTER0_CORE_COUNT)
-#define PLATFORM_MAX_CPUS_PER_CLUSTER	4
-#define PRIMARY_CPU			0x0
-#define MAX_IO_DEVICES			3
-#define MAX_IO_HANDLES			4
-
 /* Constants for accessing platform configuration */
 #define CONFIG_GICD_ADDR		0
 #define CONFIG_GICC_ADDR		1
@@ -100,13 +53,8 @@
 #define CONFIG_LIMIT			10
 
 /*******************************************************************************
- * Platform memory map related constants
+ * FVP memory map related constants
  ******************************************************************************/
-#define TZROM_BASE		0x00000000
-#define TZROM_SIZE		0x04000000
-
-#define TZRAM_BASE		0x04000000
-#define TZRAM_SIZE		0x40000
 
 #define FLASH0_BASE		0x08000000
 #define FLASH0_SIZE		TZROM_SIZE
@@ -130,15 +78,11 @@
 #define NSRAM_BASE		0x2e000000
 #define NSRAM_SIZE		0x10000
 
-/* Location of trusted dram on the base fvp */
-#define TZDRAM_BASE		0x06000000
-#define TZDRAM_SIZE		0x02000000
 #define MBOX_OFF		0x1000
 
 /* Base address where parameters to BL31 are stored */
 #define PARAMS_BASE		TZDRAM_BASE
 
-
 #define DRAM1_BASE		0x80000000ull
 #define DRAM1_SIZE		0x80000000ull
 #define DRAM1_END		(DRAM1_BASE + DRAM1_SIZE - 1)
@@ -161,18 +105,6 @@
 #define SYS_CNTREAD_BASE	0x2a800000
 #define SYS_TIMCTL_BASE		0x2a810000
 
-/* Counter timer module offsets */
-#define CNTNSAR			0x4
-#define CNTNSAR_NS_SHIFT(x)	x
-
-#define CNTACR_BASE(x)		(0x40 + (x << 2))
-#define CNTACR_RPCT_SHIFT	0x0
-#define CNTACR_RVCT_SHIFT	0x1
-#define CNTACR_RFRQ_SHIFT	0x2
-#define CNTACR_RVOFF_SHIFT	0x3
-#define CNTACR_RWVT_SHIFT	0x4
-#define CNTACR_RWPT_SHIFT	0x5
-
 /* V2M motherboard system registers & offsets */
 #define VE_SYSREGS_BASE		0x1c010000
 #define V2M_SYS_ID			0x0
@@ -180,6 +112,9 @@
 #define V2M_SYS_CFGDATA		0xa0
 #define V2M_SYS_CFGCTRL		0xa4
 
+/* Load address of BL33 in the FVP port */
+#define NS_IMAGE_OFFSET		(DRAM1_BASE + 0x8000000) /* DRAM + 128MB */
+
 /*
  * V2M sysled bit definitions. The values written to this
  * register are defined in arch.h & runtime_svc.h. Only
@@ -225,81 +160,6 @@
 /* FVP Power controller base address*/
 #define PWRC_BASE		0x1c100000
 
-/*******************************************************************************
- * Platform specific per affinity states. Distinction between off and suspend
- * is made to allow reporting of a suspended cpu as still being on e.g. in the
- * affinity_info psci call.
- ******************************************************************************/
-#define PLATFORM_MAX_AFF0	4
-#define PLATFORM_MAX_AFF1	2
-#define PLAT_AFF_UNK		0xff
-
-#define PLAT_AFF0_OFF		0x0
-#define PLAT_AFF0_ONPENDING	0x1
-#define PLAT_AFF0_SUSPEND	0x2
-#define PLAT_AFF0_ON		0x3
-
-#define PLAT_AFF1_OFF		0x0
-#define PLAT_AFF1_ONPENDING	0x1
-#define PLAT_AFF1_SUSPEND	0x2
-#define PLAT_AFF1_ON		0x3
-
-/*******************************************************************************
- * BL1 specific defines.
- * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
- * addresses.
- ******************************************************************************/
-#define BL1_RO_BASE			TZROM_BASE
-#define BL1_RO_LIMIT			(TZROM_BASE + TZROM_SIZE)
-#define BL1_RW_BASE			TZRAM_BASE
-#define BL1_RW_LIMIT			BL31_BASE
-
-/*******************************************************************************
- * BL2 specific defines.
- ******************************************************************************/
-#define BL2_BASE			(TZRAM_BASE + TZRAM_SIZE - 0xc000)
-#define BL2_LIMIT			(TZRAM_BASE + TZRAM_SIZE)
-
-/*******************************************************************************
- * BL31 specific defines.
- ******************************************************************************/
-#define BL31_BASE			(TZRAM_BASE + 0x6000)
-#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
-#define BL31_LIMIT			BL32_BASE
-#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
-#define BL31_LIMIT			BL2_BASE
-#endif
-
-/*******************************************************************************
- * BL32 specific defines.
- ******************************************************************************/
-/*
- * On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
- */
-#define TSP_IN_TZRAM			0
-#define TSP_IN_TZDRAM			1
-
-#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
-# define TSP_SEC_MEM_BASE		TZRAM_BASE
-# define TSP_SEC_MEM_SIZE		TZRAM_SIZE
-# define BL32_BASE			(TZRAM_BASE + TZRAM_SIZE - 0x1c000)
-# define BL32_LIMIT			BL2_BASE
-#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
-# define TSP_SEC_MEM_BASE		TZDRAM_BASE
-# define TSP_SEC_MEM_SIZE		TZDRAM_SIZE
-# define BL32_BASE			(TZDRAM_BASE + 0x2000)
-# define BL32_LIMIT			(TZDRAM_BASE + (1 << 21))
-#else
-# error "Unsupported TSP_RAM_LOCATION_ID value"
-#endif
-
-/*******************************************************************************
- * Platform specific page table and MMU setup constants
- ******************************************************************************/
-#define ADDR_SPACE_SIZE			(1ull << 32)
-#define MAX_XLAT_TABLES			3
-#define MAX_MMAP_REGIONS		16
-
 
 /*******************************************************************************
  * CCI-400 related constants
@@ -347,7 +207,6 @@
 #define PL011_UART2_BASE		0x1c0b0000
 #define PL011_UART3_BASE		0x1c0c0000
 
-
 /*******************************************************************************
  * TrustZone address space controller related constants
  ******************************************************************************/
@@ -372,178 +231,4 @@
 #define FVP_NSAID_CLCD			7
 
 
-/*******************************************************************************
- * Declarations and constants to access the mailboxes safely. Each mailbox is
- * aligned on the biggest cache line size in the platform. This is known only
- * to the platform as it might have a combination of integrated and external
- * caches. Such alignment ensures that two maiboxes do not sit on the same cache
- * line at any cache level. They could belong to different cpus/clusters &
- * get written while being protected by different locks causing corruption of
- * a valid mailbox address.
- ******************************************************************************/
-#define CACHE_WRITEBACK_SHIFT   6
-#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
-
-#ifndef __ASSEMBLY__
-
-#include <stdint.h>
-#include <bl_common.h>
-
-typedef volatile struct mailbox {
-	unsigned long value
-	__attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
-} mailbox_t;
-
-/*******************************************************************************
- * Forward declarations
- ******************************************************************************/
-struct plat_pm_ops;
-struct meminfo;
-struct bl31_params;
-struct image_info;
-struct entry_point_info;
-
-
-/*******************************************************************************
- * This structure represents the superset of information that is passed to
- * BL31 e.g. while passing control to it from BL2 which is bl31_params
- * and another platform specific params
- ******************************************************************************/
-typedef struct bl2_to_bl31_params_mem {
-	struct bl31_params bl31_params;
-	struct image_info bl31_image_info;
-	struct image_info bl32_image_info;
-	struct image_info bl33_image_info;
-	struct entry_point_info bl33_ep_info;
-	struct entry_point_info bl32_ep_info;
-	struct entry_point_info bl31_ep_info;
-} bl2_to_bl31_params_mem_t;
-
-
-/*******************************************************************************
- * Function and variable prototypes
- ******************************************************************************/
-extern unsigned long *bl1_normal_ram_base;
-extern unsigned long *bl1_normal_ram_len;
-extern unsigned long *bl1_normal_ram_limit;
-extern unsigned long *bl1_normal_ram_zi_base;
-extern unsigned long *bl1_normal_ram_zi_len;
-
-extern unsigned long *bl1_coherent_ram_base;
-extern unsigned long *bl1_coherent_ram_len;
-extern unsigned long *bl1_coherent_ram_limit;
-extern unsigned long *bl1_coherent_ram_zi_base;
-extern unsigned long *bl1_coherent_ram_zi_len;
-extern unsigned long warm_boot_entrypoint;
-
-extern void bl1_plat_arch_setup(void);
-extern void bl2_plat_arch_setup(void);
-extern void bl31_plat_arch_setup(void);
-extern int platform_setup_pm(const struct plat_pm_ops **);
-extern unsigned int platform_get_core_pos(unsigned long mpidr);
-extern void enable_mmu_el1(void);
-extern void enable_mmu_el3(void);
-extern void configure_mmu_el1(unsigned long total_base,
-			      unsigned long total_size,
-			      unsigned long ro_start,
-			      unsigned long ro_limit,
-			      unsigned long coh_start,
-			      unsigned long coh_limit);
-extern void configure_mmu_el3(unsigned long total_base,
-			      unsigned long total_size,
-			      unsigned long ro_start,
-			      unsigned long ro_limit,
-			      unsigned long coh_start,
-			      unsigned long coh_limit);
-extern unsigned long platform_get_cfgvar(unsigned int);
-extern int platform_config_setup(void);
-extern void plat_report_exception(unsigned long);
-extern unsigned long plat_get_ns_image_entrypoint(void);
-extern unsigned long platform_get_stack(unsigned long mpidr);
-extern uint64_t plat_get_syscnt_freq(void);
-#if RESET_TO_BL31
-extern void plat_get_entry_point_info(unsigned long target_security,
-				struct entry_point_info *target_entry_info);
-#endif
-
-extern void fvp_cci_setup(void);
-
-/* Declarations for plat_gic.c */
-extern uint32_t ic_get_pending_interrupt_id(void);
-extern uint32_t ic_get_pending_interrupt_type(void);
-extern uint32_t ic_acknowledge_interrupt(void);
-extern uint32_t ic_get_interrupt_type(uint32_t id);
-extern void ic_end_of_interrupt(uint32_t id);
-extern void gic_cpuif_deactivate(unsigned int);
-extern void gic_cpuif_setup(unsigned int);
-extern void gic_pcpu_distif_setup(unsigned int);
-extern void gic_setup(void);
-extern uint32_t plat_interrupt_type_to_line(uint32_t type,
-					    uint32_t security_state);
-
-/* Declarations for plat_topology.c */
-extern int plat_setup_topology(void);
-extern int plat_get_max_afflvl(void);
-extern unsigned int plat_get_aff_count(unsigned int, unsigned long);
-extern unsigned int plat_get_aff_state(unsigned int, unsigned long);
-
-/* Declarations for plat_io_storage.c */
-extern void io_setup(void);
-extern int plat_get_image_source(const char *image_name,
-		uintptr_t *dev_handle, uintptr_t *image_spec);
-
-/* Declarations for plat_security.c */
-extern void plat_security_setup(void);
-
-/*
- * Before calling this function BL2 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL2 and set SPSR and security state.
- * On FVP we are only setting the security state, entrypoint
- */
-extern void bl1_plat_set_bl2_ep_info(struct image_info *image,
-					struct entry_point_info *ep);
-
-/*
- * Before calling this function BL31 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL31 and set SPSR and security state.
- * On FVP we are only setting the security state, entrypoint
- */
-extern void bl2_plat_set_bl31_ep_info(struct image_info *image,
-					struct entry_point_info *ep);
-
-/*
- * Before calling this function BL32 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL32 and set SPSR and security state.
- * On FVP we are only setting the security state, entrypoint
- */
-extern void bl2_plat_set_bl32_ep_info(struct image_info *image,
-					struct entry_point_info *ep);
-
-/*
- * Before calling this function BL33 is loaded in memory and its entrypoint
- * is set by load_image. This is a placeholder for the platform to change
- * the entrypoint of BL33 and set SPSR and security state.
- * On FVP we are only setting the security state, entrypoint
- */
-extern void bl2_plat_set_bl33_ep_info(struct image_info *image,
-					struct entry_point_info *ep);
-
-/* Gets the memory layout for BL32 */
-extern void bl2_plat_get_bl32_meminfo(struct meminfo *mem_info);
-
-/* Gets the memory layout for BL33 */
-extern void bl2_plat_get_bl33_meminfo(struct meminfo *mem_info);
-
-/* Sets the entrypoint for BL32 */
-extern void fvp_set_bl32_ep_info(struct entry_point_info *bl32_ep_info);
-
-/* Sets the entrypoint for BL33 */
-extern void fvp_set_bl33_ep_info(struct entry_point_info *bl33_ep_info);
-
-
-#endif /*__ASSEMBLY__*/
-
-#endif /* __PLATFORM_H__ */
+#endif /* __FVP_DEF_H__ */

plat/fvp/plat_gic.c → plat/fvp/fvp_gic.c

@@ -37,6 +37,8 @@
 #include <interrupt_mgmt.h>
 #include <platform.h>
 #include <stdint.h>
+#include "fvp_def.h"
+#include "fvp_private.h"
 
 /*******************************************************************************
  * This function does some minimal GICv3 configuration. The Firmware itself does
@@ -275,8 +277,8 @@ void gic_setup(void)
 {
 	unsigned int gicd_base, gicc_base;
 
-	gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
-	gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+	gicd_base = fvp_get_cfgvar(CONFIG_GICD_ADDR);
+	gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
 
 	gic_cpuif_setup(gicc_base);
 	gic_distif_setup(gicd_base);
@@ -296,7 +298,7 @@ void gic_setup(void)
  ******************************************************************************/
 uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
 {
-	uint32_t gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+	uint32_t gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
 
 	assert(type == INTR_TYPE_S_EL1 ||
 	       type == INTR_TYPE_EL3 ||
@@ -322,11 +324,11 @@ uint32_t plat_interrupt_type_to_line(uint32_t type, uint32_t security_state)
  * the GIC cpu interface. INTR_TYPE_INVAL is returned when there is no
  * interrupt pending.
  ******************************************************************************/
-uint32_t ic_get_pending_interrupt_type()
+uint32_t plat_ic_get_pending_interrupt_type()
 {
 	uint32_t id, gicc_base;
 
-	gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+	gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
 	id = gicc_read_hppir(gicc_base);
 
 	/* Assume that all secure interrupts are S-EL1 interrupts */
@@ -344,11 +346,11 @@ uint32_t ic_get_pending_interrupt_type()
  * the GIC cpu interface. INTR_ID_UNAVAILABLE is returned when there is no
  * interrupt pending.
  ******************************************************************************/
-uint32_t ic_get_pending_interrupt_id()
+uint32_t plat_ic_get_pending_interrupt_id()
 {
 	uint32_t id, gicc_base;
 
-	gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+	gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
 	id = gicc_read_hppir(gicc_base);
 
 	if (id < 1022)
@@ -368,18 +370,18 @@ uint32_t ic_get_pending_interrupt_id()
  * This functions reads the GIC cpu interface Interrupt Acknowledge register
  * to start handling the pending interrupt. It returns the contents of the IAR.
  ******************************************************************************/
-uint32_t ic_acknowledge_interrupt()
+uint32_t plat_ic_acknowledge_interrupt()
 {
-	return gicc_read_IAR(platform_get_cfgvar(CONFIG_GICC_ADDR));
+	return gicc_read_IAR(fvp_get_cfgvar(CONFIG_GICC_ADDR));
 }
 
 /*******************************************************************************
  * This functions writes the GIC cpu interface End Of Interrupt register with
  * the passed value to finish handling the active interrupt
  ******************************************************************************/
-void ic_end_of_interrupt(uint32_t id)
+void plat_ic_end_of_interrupt(uint32_t id)
 {
-	gicc_write_EOIR(platform_get_cfgvar(CONFIG_GICC_ADDR), id);
+	gicc_write_EOIR(fvp_get_cfgvar(CONFIG_GICC_ADDR), id);
 	return;
 }
 
@@ -388,11 +390,11 @@ void ic_end_of_interrupt(uint32_t id)
  * this interrupt has been configured under by the interrupt controller i.e.
  * group0 or group1.
  ******************************************************************************/
-uint32_t ic_get_interrupt_type(uint32_t id)
+uint32_t plat_ic_get_interrupt_type(uint32_t id)
 {
 	uint32_t group;
 
-	group = gicd_get_igroupr(platform_get_cfgvar(CONFIG_GICD_ADDR), id);
+	group = gicd_get_igroupr(fvp_get_cfgvar(CONFIG_GICD_ADDR), id);
 
 	/* Assume that all secure interrupts are S-EL1 interrupts */
 	if (group == GRP0)

plat/fvp/plat_io_storage.c → plat/fvp/fvp_io_storage.c

@@ -35,9 +35,9 @@
 #include <io_memmap.h>
 #include <io_storage.h>
 #include <io_semihosting.h>
-#include <platform.h>
 #include <semihosting.h>	/* For FOPEN_MODE_... */
 #include <string.h>
+#include "fvp_def.h"
 
 /* IO devices */
 static io_plat_data_t io_data;
@@ -168,7 +168,7 @@ static int open_semihosting(const uintptr_t spec)
 	return result;
 }
 
-void io_setup (void)
+void fvp_io_setup (void)
 {
 	int io_result = IO_FAIL;
 

plat/fvp/plat_pm.c → plat/fvp/fvp_pm.c

@@ -34,8 +34,11 @@
 #include <cci400.h>
 #include <mmio.h>
 #include <platform.h>
+#include <platform_def.h>
 #include <psci.h>
 #include "drivers/pwrc/fvp_pwrc.h"
+#include "fvp_def.h"
+#include "fvp_private.h"
 
 /*******************************************************************************
  * FVP handler called when an affinity instance is about to enter standby.
@@ -136,7 +139,7 @@ int fvp_affinst_off(unsigned long mpidr,
 			 * Disable coherency if this cluster is to be
 			 * turned off
 			 */
-			cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+			cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
 			if (cci_setup) {
 				cci_disable_coherency(mpidr);
 			}
@@ -157,7 +160,7 @@ int fvp_affinst_off(unsigned long mpidr,
 			 * Take this cpu out of intra-cluster coherency if
 			 * the FVP flavour supports the SMP bit.
 			 */
-			cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
+			cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
 			if (cpu_setup) {
 				ectlr = read_cpuectlr();
 				ectlr &= ~CPUECTLR_SMP_BIT;
@@ -168,7 +171,7 @@ int fvp_affinst_off(unsigned long mpidr,
 			 * Prevent interrupts from spuriously waking up
 			 * this cpu
 			 */
-			gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+			gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
 			gic_cpuif_deactivate(gicc_base);
 
 			/*
@@ -216,7 +219,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
 			 * Disable coherency if this cluster is to be
 			 * turned off
 			 */
-			cci_setup = platform_get_cfgvar(CONFIG_HAS_CCI);
+			cci_setup = fvp_get_cfgvar(CONFIG_HAS_CCI);
 			if (cci_setup) {
 				cci_disable_coherency(mpidr);
 			}
@@ -236,7 +239,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
 			 * Take this cpu out of intra-cluster coherency if
 			 * the FVP flavour supports the SMP bit.
 			 */
-			cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
+			cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
 			if (cpu_setup) {
 				ectlr = read_cpuectlr();
 				ectlr &= ~CPUECTLR_SMP_BIT;
@@ -254,7 +257,7 @@ int fvp_affinst_suspend(unsigned long mpidr,
 			 * Prevent interrupts from spuriously waking up
 			 * this cpu
 			 */
-			gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+			gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
 			gic_cpuif_deactivate(gicc_base);
 
 			/*
@@ -322,7 +325,7 @@ int fvp_affinst_on_finish(unsigned long mpidr,
 		 * Turn on intra-cluster coherency if the FVP flavour supports
 		 * it.
 		 */
-		cpu_setup = platform_get_cfgvar(CONFIG_CPU_SETUP);
+		cpu_setup = fvp_get_cfgvar(CONFIG_CPU_SETUP);
 		if (cpu_setup) {
 			ectlr = read_cpuectlr();
 			ectlr |= CPUECTLR_SMP_BIT;
@@ -342,8 +345,8 @@ int fvp_affinst_on_finish(unsigned long mpidr,
 		flush_dcache_range((unsigned long) &fvp_mboxes[linear_id],
 				   sizeof(unsigned long));
 
-		gicd_base = platform_get_cfgvar(CONFIG_GICD_ADDR);
-		gicc_base = platform_get_cfgvar(CONFIG_GICC_ADDR);
+		gicd_base = fvp_get_cfgvar(CONFIG_GICD_ADDR);
+		gicc_base = fvp_get_cfgvar(CONFIG_GICC_ADDR);
 
 		/* Enable the gic cpu interface */
 		gic_cpuif_setup(gicc_base);