Commit 2693f1db authored by Varun Wadekar's avatar Varun Wadekar
Browse files

Tegra: implement common handler `plat_get_target_pwr_state()`



This patch adds a platform handler to calculate the proper target power
level at the specified affinity level.

Tegra platforms assign a local state value in order of decreasing depth
of the power state i.e. for two power states X & Y, if X < Y then X
represents a shallower power state than Y. As a result, the coordinated
target local power state for a power domain will be the maximum of the
requested local power state values.

Change-Id: I67360684b7f5b783fcfdd605b96da5375fa05417
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
parent 11bd24be
......@@ -52,7 +52,6 @@ BL31_SOURCES += drivers/arm/gic/gic_v2.c \
drivers/delay_timer/delay_timer.c \
drivers/ti/uart/aarch64/16550_console.S \
plat/common/aarch64/platform_mp_stack.S \
plat/common/plat_psci_common.c \
${COMMON_DIR}/aarch64/tegra_helpers.S \
${COMMON_DIR}/drivers/pmc/pmc.c \
${COMMON_DIR}/tegra_bl31_setup.c \
......
......@@ -318,3 +318,24 @@ int plat_setup_psci_ops(uintptr_t sec_entrypoint,
return 0;
}
/*******************************************************************************
* Platform handler to calculate the proper target power level at the
* specified affinity level
******************************************************************************/
plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
const plat_local_state_t *states,
unsigned int ncpu)
{
plat_local_state_t target = PLAT_MAX_RET_STATE, temp;
assert(ncpu);
do {
temp = *states++;
if ((temp > target) && (temp != PLAT_MAX_OFF_STATE))
target = temp;
} while (--ncpu);
return target;
}
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