Merge changes from topic "stm32mp_corrections_w40" into integration

* changes:
  gpio: stm32_gpio: do not mix error code types
  fdts: stm32mp1: move FDCAN to PLL4_R
  mmc: increase delay between ACMD41 retries
  crypto: stm32_hash: align stm32_hash_update() prototype

drivers/mmc/mmc.c

@@ -361,7 +361,7 @@ static int sd_send_op_cond(void)
 			return 0;
 		}
 
-		mdelay(1);
+		mdelay(10);
 	}
 
 	ERROR("ACMD41 failed after %d retries\n", SEND_OP_COND_MAX_RETRIES);

drivers/st/gpio/stm32_gpio.c

@@ -165,7 +165,7 @@ int dt_set_pinctrl_config(int node)
 	void *fdt;
 
 	if (fdt_get_address(&fdt) == 0) {
-		return -ENOENT;
+		return -FDT_ERR_NOTFOUND;
 	}
 
 	if (status == DT_DISABLED) {

fdts/stm32mp157a-avenger96.dts

@@ -246,7 +246,7 @@
 		CLK_UART6_HSI
 		CLK_UART78_HSI
 		CLK_SPDIF_PLL4P
-		CLK_FDCAN_PLL4Q
+		CLK_FDCAN_PLL4R
 		CLK_SAI1_PLL3Q
 		CLK_SAI2_PLL3Q
 		CLK_SAI3_PLL3Q

fdts/stm32mp157a-dk1.dts

@@ -266,7 +266,7 @@
 		CLK_UART6_HSI
 		CLK_UART78_HSI
 		CLK_SPDIF_PLL4P
-		CLK_FDCAN_PLL4Q
+		CLK_FDCAN_PLL4R
 		CLK_SAI1_PLL3Q
 		CLK_SAI2_PLL3Q
 		CLK_SAI3_PLL3Q

fdts/stm32mp157c-ed1.dts

@@ -272,7 +272,7 @@
 		CLK_UART6_HSI
 		CLK_UART78_HSI
 		CLK_SPDIF_PLL4P
-		CLK_FDCAN_PLL4Q
+		CLK_FDCAN_PLL4R
 		CLK_SAI1_PLL3Q
 		CLK_SAI2_PLL3Q
 		CLK_SAI3_PLL3Q

include/drivers/st/stm32_hash.h

@@ -14,7 +14,7 @@ enum stm32_hash_algo_mode {
 	HASH_SHA256
 };
 
-int stm32_hash_update(const uint8_t *buffer, uint32_t length);
+int stm32_hash_update(const uint8_t *buffer, size_t length);
 int stm32_hash_final(uint8_t *digest);
 int stm32_hash_final_update(const uint8_t *buffer, uint32_t buf_length,
 			    uint8_t *digest);