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adam.huang
Arm Trusted Firmware
Commits
2eedba9a
Unverified
Commit
2eedba9a
authored
Oct 30, 2018
by
Antonio Niño Díaz
Committed by
GitHub
Oct 30, 2018
Browse files
Merge pull request #1651 from antonio-nino-diaz-arm/an/rand-misra
Fix some MISRA defects
parents
392b1d59
195e363f
Changes
30
Show whitespace changes
Inline
Side-by-side
include/lib/cpus/aarch64/cortex_a75.h
View file @
2eedba9a
...
...
@@ -4,11 +4,13 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_A75_H__
#define __CORTEX_A75_H__
#ifndef CORTEX_A75_H
#define CORTEX_A75_H
#include <utils_def.h>
/* Cortex-A75 MIDR */
#define CORTEX_A75_MIDR 0x410fd0a0
#define CORTEX_A75_MIDR
U(
0x410fd0a0
)
/*******************************************************************************
* CPU Extended Control register specific definitions.
...
...
@@ -24,7 +26,7 @@
#define CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE (1 << 35)
/* Definitions of register field mask in CORTEX_A75_CPUPWRCTLR_EL1 */
#define CORTEX_A75_CORE_PWRDN_EN_MASK 0x1
#define CORTEX_A75_CORE_PWRDN_EN_MASK
U(
0x1
)
#define CORTEX_A75_ACTLR_AMEN_BIT (U(1) << 4)
...
...
@@ -50,4 +52,4 @@ void cortex_a75_amu_write_cpuamcntenset_el0(unsigned int mask);
void
cortex_a75_amu_write_cpuamcntenclr_el0
(
unsigned
int
mask
);
#endif
/* __ASSEMBLY__ */
#endif
/*
__
CORTEX_A75_H
__
*/
#endif
/* CORTEX_A75_H */
include/lib/cpus/aarch64/cortex_ares.h
View file @
2eedba9a
...
...
@@ -4,11 +4,13 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __CORTEX_ARES_H__
#define __CORTEX_ARES_H__
#ifndef CORTEX_ARES_H
#define CORTEX_ARES_H
#include <utils_def.h>
/* Cortex-ARES MIDR for revision 0 */
#define CORTEX_ARES_MIDR 0x410fd0c0
#define CORTEX_ARES_MIDR
U(
0x410fd0c0
)
/*******************************************************************************
* CPU Extended Control register specific definitions.
...
...
@@ -17,7 +19,7 @@
#define CORTEX_ARES_CPUECTLR_EL1 S3_0_C15_C1_4
/* Definitions of register field mask in CORTEX_ARES_CPUPWRCTLR_EL1 */
#define CORTEX_ARES_CORE_PWRDN_EN_MASK 0x1
#define CORTEX_ARES_CORE_PWRDN_EN_MASK
U(
0x1
)
#define CORTEX_ARES_ACTLR_AMEN_BIT (U(1) << 4)
...
...
@@ -30,4 +32,4 @@
#define CPUPOR_EL3 S3_6_C15_C8_2
#define CPUPMR_EL3 S3_6_C15_C8_3
#endif
/*
__
CORTEX_ARES_H
__
*/
#endif
/* CORTEX_ARES_H */
include/lib/cpus/aarch64/cpuamu.h
View file @
2eedba9a
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CPUAMU_H
__
#define
__
CPUAMU_H
__
#ifndef CPUAMU_H
#define CPUAMU_H
/*******************************************************************************
* CPU Activity Monitor Unit register specific definitions.
...
...
@@ -32,8 +32,8 @@
#ifndef __ASSEMBLY__
#include <stdint.h>
uint64_t
cpuamu_cnt_read
(
int
idx
);
void
cpuamu_cnt_write
(
int
idx
,
uint64_t
val
);
uint64_t
cpuamu_cnt_read
(
unsigned
int
idx
);
void
cpuamu_cnt_write
(
unsigned
int
idx
,
uint64_t
val
);
unsigned
int
cpuamu_read_cpuamcntenset_el0
(
void
);
unsigned
int
cpuamu_read_cpuamcntenclr_el0
(
void
);
void
cpuamu_write_cpuamcntenset_el0
(
unsigned
int
mask
);
...
...
@@ -45,4 +45,4 @@ void cpuamu_context_restore(unsigned int nr_counters);
#endif
/* __ASSEMBLY__ */
#endif
/*
__
CPUAMU_H
__
*/
#endif
/* CPUAMU_H */
include/lib/cpus/errata_report.h
View file @
2eedba9a
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
ERRATA_
H__
#define
__
ERRATA_
H__
#ifndef ERRATA_
REPORT_H
#define ERRATA_
REPORT_H
#ifndef __ASSEMBLY__
...
...
@@ -30,5 +30,4 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported);
#define ERRATA_APPLIES 1
#define ERRATA_MISSING 2
#endif
/* __ERRATA_H__ */
#endif
/* ERRATA_REPORT_H */
include/lib/cpus/wa_cve_2017_5715.h
View file @
2eedba9a
...
...
@@ -4,9 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
WA_CVE_2017_5715_H
__
#define
__
WA_CVE_2017_5715_H
__
#ifndef WA_CVE_2017_5715_H
#define WA_CVE_2017_5715_H
int
check_wa_cve_2017_5715
(
void
);
#endif
/*
__
WA_CVE_2017_5715_H
__
*/
#endif
/* WA_CVE_2017_5715_H */
include/lib/cpus/wa_cve_2018_3639.h
View file @
2eedba9a
...
...
@@ -4,9 +4,9 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
WA_CVE_2018_3639_H
__
#define
__
WA_CVE_2018_3639_H
__
#ifndef WA_CVE_2018_3639_H
#define WA_CVE_2018_3639_H
void
*
wa_cve_2018_3639_get_disable_ptr
(
void
);
#endif
/*
__
WA_CVE_2018_3639_H
__
*/
#endif
/* WA_CVE_2018_3639_H */
include/lib/el3_runtime/cpu_data.h
View file @
2eedba9a
...
...
@@ -4,8 +4,8 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
CPU_DATA_H
__
#define
__
CPU_DATA_H
__
#ifndef CPU_DATA_H
#define CPU_DATA_H
#include <ehf.h>
#include <platform_def.h>
/* CACHE_WRITEBACK_GRANULE required */
...
...
@@ -161,4 +161,4 @@ void init_cpu_ops(void);
#endif
/* __ASSEMBLY__ */
#endif
/*
__
CPU_DATA_H
__
*/
#endif
/* CPU_DATA_H */
include/lib/extensions/amu.h
View file @
2eedba9a
...
...
@@ -4,33 +4,35 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
AMU_H
__
#define
__
AMU_H
__
#ifndef AMU_H
#define AMU_H
#include <cassert.h>
#include <platform_def.h>
#include <stdbool.h>
#include <stdint.h>
#include <utils_def.h>
/* All group 0 counters */
#define AMU_GROUP0_COUNTERS_MASK 0xf
#define AMU_GROUP0_COUNTERS_MASK
U(
0xf
)
#ifdef PLAT_AMU_GROUP1_COUNTERS_MASK
#define AMU_GROUP1_COUNTERS_MASK PLAT_AMU_GROUP1_COUNTERS_MASK
#else
#define AMU_GROUP1_COUNTERS_MASK
0
#define AMU_GROUP1_COUNTERS_MASK
U(0)
#endif
#ifdef PLAT_AMU_GROUP1_NR_COUNTERS
#define AMU_GROUP1_NR_COUNTERS PLAT_AMU_GROUP1_NR_COUNTERS
#else
#define AMU_GROUP1_NR_COUNTERS
0
#define AMU_GROUP1_NR_COUNTERS
U(0)
#endif
CASSERT
(
AMU_GROUP1_COUNTERS_MASK
<=
0xffff
,
invalid_amu_group1_counters_mask
);
CASSERT
(
AMU_GROUP1_NR_COUNTERS
<=
16
,
invalid_amu_group1_nr_counters
);
int
amu_supported
(
void
);
void
amu_enable
(
int
el2_unused
);
bool
amu_supported
(
void
);
void
amu_enable
(
bool
el2_unused
);
/* Group 0 configuration helpers */
uint64_t
amu_group0_cnt_read
(
int
idx
);
...
...
@@ -41,4 +43,4 @@ uint64_t amu_group1_cnt_read(int idx);
void
amu_group1_cnt_write
(
int
idx
,
uint64_t
val
);
void
amu_group1_set_evtype
(
int
idx
,
unsigned
int
val
);
#endif
/*
__
AMU_H
__
*/
#endif
/* AMU_H */
include/lib/extensions/amu_private.h
View file @
2eedba9a
/*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2017
-2018
, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
AMU_PRIVATE_H
__
#define
__
AMU_PRIVATE_H
__
#ifndef AMU_PRIVATE_H
#define AMU_PRIVATE_H
#include <stdint.h>
uint64_t
amu_group0_cnt_read_internal
(
int
idx
);
void
amu_group0_cnt_write_internal
(
int
idx
,
uint64_t
);
void
amu_group0_cnt_write_internal
(
int
idx
,
uint64_t
val
);
uint64_t
amu_group1_cnt_read_internal
(
int
idx
);
void
amu_group1_cnt_write_internal
(
int
idx
,
uint64_t
);
void
amu_group1_cnt_write_internal
(
int
idx
,
uint64_t
val
);
void
amu_group1_set_evtype_internal
(
int
idx
,
unsigned
int
val
);
#endif
/*
__
AMU_PRIVATE_H
__
*/
#endif
/* AMU_PRIVATE_H */
include/lib/extensions/mpam.h
View file @
2eedba9a
...
...
@@ -10,6 +10,6 @@
#include <stdbool.h>
bool
mpam_supported
(
void
);
void
mpam_enable
(
int
el2_unused
);
void
mpam_enable
(
bool
el2_unused
);
#endif
/* MPAM_H */
include/lib/extensions/spe.h
View file @
2eedba9a
...
...
@@ -4,11 +4,13 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
SPE_H
__
#define
__
SPE_H
__
#ifndef SPE_H
#define SPE_H
int
spe_supported
(
void
);
void
spe_enable
(
int
el2_unused
);
#include <stdbool.h>
bool
spe_supported
(
void
);
void
spe_enable
(
bool
el2_unused
);
void
spe_disable
(
void
);
#endif
/*
__
SPE_H
__
*/
#endif
/* SPE_H */
include/lib/extensions/sve.h
View file @
2eedba9a
...
...
@@ -4,10 +4,12 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
SVE_H
__
#define
__
SVE_H
__
#ifndef SVE_H
#define SVE_H
int
sve_supported
(
void
);
void
sve_enable
(
int
el2_unused
);
#include <stdbool.h>
#endif
/* __SVE_H__ */
bool
sve_supported
(
void
);
void
sve_enable
(
bool
el2_unused
);
#endif
/* SVE_H */
include/lib/pmf/pmf.h
View file @
2eedba9a
...
...
@@ -9,17 +9,18 @@
#include <cassert.h>
#include <pmf_helpers.h>
#include <utils_def.h>
/*
* Constants used for/by PMF services.
*/
#define PMF_ARM_TIF_IMPL_ID 0x41
#define PMF_ARM_TIF_IMPL_ID
U(
0x41
)
#define PMF_TID_SHIFT 0
#define PMF_TID_MASK (0xFF << PMF_TID_SHIFT)
#define PMF_TID_MASK
(U
(0xFF
)
<< PMF_TID_SHIFT)
#define PMF_SVC_ID_SHIFT 10
#define PMF_SVC_ID_MASK (0x3F << PMF_SVC_ID_SHIFT)
#define PMF_SVC_ID_MASK
(U
(0x3F
)
<< PMF_SVC_ID_SHIFT)
#define PMF_IMPL_ID_SHIFT 24
#define PMF_IMPL_ID_MASK (0xFF
U
<< PMF_IMPL_ID_SHIFT)
#define PMF_IMPL_ID_MASK
(U
(0xFF
)
<< PMF_IMPL_ID_SHIFT)
/*
* Flags passed to PMF_REGISTER_SERVICE
...
...
@@ -37,16 +38,16 @@
/*
* Defines for PMF SMC function ids.
*/
#define PMF_SMC_GET_TIMESTAMP_32 0x82000010
u
#define PMF_SMC_GET_TIMESTAMP_64 0xC2000010
u
#define PMF_SMC_GET_TIMESTAMP_32
U(
0x82000010
)
#define PMF_SMC_GET_TIMESTAMP_64
U(
0xC2000010
)
#define PMF_NUM_SMC_CALLS 2
/*
* The macros below are used to identify
* PMF calls from the SMC function ID.
*/
#define PMF_FID_MASK 0xffe0
u
#define PMF_FID_VALUE
0u
#define PMF_FID_MASK
U(
0xffe0
)
#define PMF_FID_VALUE
U(0)
#define is_pmf_fid(_fid) (((_fid) & PMF_FID_MASK) == PMF_FID_VALUE)
/* Following are the supported PMF service IDs */
...
...
include/lib/pmf/pmf_helpers.h
View file @
2eedba9a
...
...
@@ -11,7 +11,6 @@
#include <assert.h>
#include <bl_common.h>
#include <platform.h>
#include <pmf.h>
#include <stddef.h>
#include <stdint.h>
...
...
include/plat/arm/common/arm_sip_svc.h
View file @
2eedba9a
/*
* Copyright (c) 2016-201
7
, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-201
8
, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __ARM_SIP_SVC_H__
#define __ARM_SIP_SVC_H__
#ifndef ARM_SIP_SVC_H
#define ARM_SIP_SVC_H
#include <utils_def.h>
/* SMC function IDs for SiP Service queries */
#define ARM_SIP_SVC_CALL_COUNT 0x8200ff00
#define ARM_SIP_SVC_UID 0x8200ff01
/* 0x8200ff02 is reserved */
#define ARM_SIP_SVC_VERSION 0x8200ff03
#define ARM_SIP_SVC_CALL_COUNT
U(
0x8200ff00
)
#define ARM_SIP_SVC_UID
U(
0x8200ff01
)
/*
U(
0x8200ff02
)
is reserved */
#define ARM_SIP_SVC_VERSION
U(
0x8200ff03
)
/* Function ID for requesting state switch of lower EL */
#define ARM_SIP_SVC_EXE_STATE_SWITCH 0x82000020
#define ARM_SIP_SVC_EXE_STATE_SWITCH
U(
0x82000020
)
/* ARM SiP Service Calls version numbers */
#define ARM_SIP_SVC_VERSION_MAJOR 0x0
#define ARM_SIP_SVC_VERSION_MINOR 0x2
#define ARM_SIP_SVC_VERSION_MAJOR
U(
0x0
)
#define ARM_SIP_SVC_VERSION_MINOR
U(
0x2
)
#endif
/*
__
ARM_SIP_SVC_H
__
*/
#endif
/* ARM_SIP_SVC_H */
include/plat/arm/common/plat_arm.h
View file @
2eedba9a
...
...
@@ -3,8 +3,8 @@
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef
__
PLAT_ARM_H
__
#define
__
PLAT_ARM_H
__
#ifndef PLAT_ARM_H
#define PLAT_ARM_H
#include <bakery_lock.h>
#include <cassert.h>
...
...
@@ -292,4 +292,4 @@ extern plat_psci_ops_t plat_arm_psci_pm_ops;
extern
const
mmap_region_t
plat_arm_mmap
[];
extern
const
unsigned
int
arm_pm_idle_states
[];
#endif
/*
__
PLAT_ARM_H
__
*/
#endif
/* PLAT_ARM_H */
lib/cpus/aarch64/cortex_a75_pubsub.c
View file @
2eedba9a
...
...
@@ -12,14 +12,16 @@ static void *cortex_a75_context_save(const void *arg)
{
if
(
midr_match
(
CORTEX_A75_MIDR
)
!=
0
)
cpuamu_context_save
(
CORTEX_A75_AMU_NR_COUNTERS
);
return
0
;
return
(
void
*
)
0
;
}
static
void
*
cortex_a75_context_restore
(
const
void
*
arg
)
{
if
(
midr_match
(
CORTEX_A75_MIDR
)
!=
0
)
cpuamu_context_restore
(
CORTEX_A75_AMU_NR_COUNTERS
);
return
0
;
return
(
void
*
)
0
;
}
SUBSCRIBE_TO_EVENT
(
psci_suspend_pwrdown_start
,
cortex_a75_context_save
);
...
...
lib/cpus/aarch64/cortex_ares_pubsub.c
View file @
2eedba9a
...
...
@@ -12,14 +12,16 @@ static void *cortex_ares_context_save(const void *arg)
{
if
(
midr_match
(
CORTEX_ARES_MIDR
)
!=
0
)
cpuamu_context_save
(
CORTEX_ARES_AMU_NR_COUNTERS
);
return
0
;
return
(
void
*
)
0
;
}
static
void
*
cortex_ares_context_restore
(
const
void
*
arg
)
{
if
(
midr_match
(
CORTEX_ARES_MIDR
)
!=
0
)
cpuamu_context_restore
(
CORTEX_ARES_AMU_NR_COUNTERS
);
return
0
;
return
(
void
*
)
0
;
}
SUBSCRIBE_TO_EVENT
(
psci_suspend_pwrdown_start
,
cortex_ares_context_save
);
...
...
lib/cpus/aarch64/cpuamu_helpers.S
View file @
2eedba9a
...
...
@@ -16,7 +16,7 @@
.
globl
cpuamu_write_cpuamcntenclr_el0
/*
*
uint64_t
cpuamu_cnt_read
(
int
idx
)
;
*
uint64_t
cpuamu_cnt_read
(
unsigned
int
idx
)
;
*
*
Given
`
idx
`
,
read
the
corresponding
AMU
counter
*
and
return
it
in
`
x0
`
.
...
...
@@ -41,7 +41,7 @@ func cpuamu_cnt_read
endfunc
cpuamu_cnt_read
/*
*
void
cpuamu_cnt_write
(
int
idx
,
uint64_t
val
)
;
*
void
cpuamu_cnt_write
(
unsigned
int
idx
,
uint64_t
val
)
;
*
*
Given
`
idx
`
,
write
`
val
`
to
the
corresponding
AMU
counter
.
*/
...
...
lib/cpus/errata_report.c
View file @
2eedba9a
...
...
@@ -12,6 +12,7 @@
#include <debug.h>
#include <errata_report.h>
#include <spinlock.h>
#include <stdbool.h>
#include <utils.h>
#ifdef IMAGE_BL1
...
...
@@ -35,10 +36,10 @@
*/
int
errata_needs_reporting
(
spinlock_t
*
lock
,
uint32_t
*
reported
)
{
int
report_now
;
bool
report_now
;
/* If already reported, return false. */
if
(
*
reported
)
if
(
*
reported
!=
0U
)
return
0
;
/*
...
...
@@ -46,7 +47,7 @@ int errata_needs_reporting(spinlock_t *lock, uint32_t *reported)
* report status to true.
*/
spin_lock
(
lock
);
report_now
=
!
(
*
reported
);
report_now
=
(
*
reported
==
0U
);
if
(
report_now
)
*
reported
=
1
;
spin_unlock
(
lock
);
...
...
@@ -75,8 +76,8 @@ void errata_print_msg(unsigned int status, const char *cpu, const char *id)
assert
(
status
<
ARRAY_SIZE
(
errata_status_str
));
assert
(
cpu
);
assert
(
id
);
assert
(
cpu
!=
NULL
);
assert
(
id
!=
NULL
);
msg
=
errata_status_str
[
status
];
...
...
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