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Unverified Commit 30490b15 authored by Antonio Niño Díaz's avatar Antonio Niño Díaz Committed by GitHub
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Merge pull request #1785 from vwadekar/tf2.0-tegra-downstream-rebase-1.25.19 

Tf2.0 tegra downstream rebase 1.25.19
parents d636f67e a474d3d7
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plat/nvidia/tegra/include/plat_macros.S
View file @ 30490b15
/* /*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -50,7 +50,7 @@ spacer: ...@@ -50,7 +50,7 @@ spacer:
bl asm_print_hex bl asm_print_hex
adr x4, spacer adr x4, spacer
bl asm_print_str bl asm_print_str
ldr x4, [x7], #8 ldr w4, [x7], #4
bl asm_print_hex bl asm_print_hex
adr x4, newline adr x4, newline
bl asm_print_str bl asm_print_str
......
plat/nvidia/tegra/include/platform_def.h
View file @ 30490b15
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -53,12 +53,6 @@ ...@@ -53,12 +53,6 @@
#define BL32_BASE (TZDRAM_BASE + BL31_SIZE) #define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
#define BL32_LIMIT TZDRAM_END #define BL32_LIMIT TZDRAM_END
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
/******************************************************************************* /*******************************************************************************
* Some data must be aligned on the biggest cache line size in the platform. * Some data must be aligned on the biggest cache line size in the platform.
* This is known only to the platform as it might have a combination of * This is known only to the platform as it might have a combination of
......
plat/nvidia/tegra/include/t132/tegra_def.h
View file @ 30490b15
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -24,6 +24,12 @@ ...@@ -24,6 +24,12 @@
#define PLAT_MAX_RET_STATE U(1) #define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
/*******************************************************************************
* Chip specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
/******************************************************************************* /*******************************************************************************
* GIC memory map * GIC memory map
******************************************************************************/ ******************************************************************************/
...@@ -41,7 +47,9 @@ ...@@ -41,7 +47,9 @@
******************************************************************************/ ******************************************************************************/
#define TEGRA_CAR_RESET_BASE U(0x60006000) #define TEGRA_CAR_RESET_BASE U(0x60006000)
#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
#define GPU_RESET_BIT (U(1) << 24) #define GPU_RESET_BIT (U(1) << 24)
#define GPU_SET_BIT (U(1) << 24)
/******************************************************************************* /*******************************************************************************
* Tegra Flow Controller constants * Tegra Flow Controller constants
......
plat/nvidia/tegra/include/t186/tegra_def.h
View file @ 30490b15
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -57,6 +57,12 @@ ...@@ -57,6 +57,12 @@
#define PLAT_MAX_RET_STATE U(1) #define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE U(8) #define PLAT_MAX_OFF_STATE U(8)
/*******************************************************************************
* Chip specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
/******************************************************************************* /*******************************************************************************
* Secure IRQ definitions * Secure IRQ definitions
******************************************************************************/ ******************************************************************************/
...@@ -210,7 +216,9 @@ ...@@ -210,7 +216,9 @@
******************************************************************************/ ******************************************************************************/
#define TEGRA_CAR_RESET_BASE U(0x05000000) #define TEGRA_CAR_RESET_BASE U(0x05000000)
#define TEGRA_GPU_RESET_REG_OFFSET U(0x30) #define TEGRA_GPU_RESET_REG_OFFSET U(0x30)
#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x34)
#define GPU_RESET_BIT (U(1) << 0) #define GPU_RESET_BIT (U(1) << 0)
#define GPU_SET_BIT (U(1) << 0)
#define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004) #define TEGRA_GPCDMA_RST_SET_REG_OFFSET U(0x6A0004)
#define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008) #define TEGRA_GPCDMA_RST_CLR_REG_OFFSET U(0x6A0008)
......
plat/nvidia/tegra/include/t210/tegra_def.h
View file @ 30490b15
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -14,7 +14,6 @@ ...@@ -14,7 +14,6 @@
******************************************************************************/ ******************************************************************************/
#define PSTATE_ID_CORE_POWERDN U(7) #define PSTATE_ID_CORE_POWERDN U(7)
#define PSTATE_ID_CLUSTER_IDLE U(16) #define PSTATE_ID_CLUSTER_IDLE U(16)
#define PSTATE_ID_CLUSTER_POWERDN U(17)
#define PSTATE_ID_SOC_POWERDN U(27) #define PSTATE_ID_SOC_POWERDN U(27)
/******************************************************************************* /*******************************************************************************
...@@ -32,10 +31,23 @@ ...@@ -32,10 +31,23 @@
#define PLAT_MAX_RET_STATE U(1) #define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1)) #define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + U(1))
/*******************************************************************************
* Chip specific page table and MMU setup constants
******************************************************************************/
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 35)
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 35)
/*******************************************************************************
* SC7 entry firmware's header size
******************************************************************************/
#define SC7ENTRY_FW_HEADER_SIZE_BYTES U(0x400)
/******************************************************************************* /*******************************************************************************
* iRAM memory constants * iRAM memory constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_IRAM_BASE 0x40000000 #define TEGRA_IRAM_BASE U(0x40000000)
#define TEGRA_IRAM_A_SIZE U(0x10000) /* 64KB */
#define TEGRA_IRAM_SIZE U(40000) /* 256KB */
/******************************************************************************* /*******************************************************************************
* GIC memory map * GIC memory map
...@@ -43,6 +55,11 @@ ...@@ -43,6 +55,11 @@
#define TEGRA_GICD_BASE U(0x50041000) #define TEGRA_GICD_BASE U(0x50041000)
#define TEGRA_GICC_BASE U(0x50042000) #define TEGRA_GICC_BASE U(0x50042000)
/*******************************************************************************
* Secure IRQ definitions
******************************************************************************/
#define TEGRA210_WDT_CPU_LEGACY_FIQ U(28)
/******************************************************************************* /*******************************************************************************
* Tegra Memory Select Switch Controller constants * Tegra Memory Select Switch Controller constants
******************************************************************************/ ******************************************************************************/
...@@ -84,21 +101,55 @@ ...@@ -84,21 +101,55 @@
* Tegra Clock and Reset Controller constants * Tegra Clock and Reset Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_CAR_RESET_BASE U(0x60006000) #define TEGRA_CAR_RESET_BASE U(0x60006000)
#define TEGRA_BOND_OUT_H U(0x74)
#define APB_DMA_LOCK_BIT (U(1) << 2)
#define AHB_DMA_LOCK_BIT (U(1) << 1)
#define TEGRA_BOND_OUT_U U(0x78)
#define IRAM_D_LOCK_BIT (U(1) << 23)
#define IRAM_C_LOCK_BIT (U(1) << 22)
#define IRAM_B_LOCK_BIT (U(1) << 21)
#define TEGRA_GPU_RESET_REG_OFFSET U(0x28C) #define TEGRA_GPU_RESET_REG_OFFSET U(0x28C)
#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x290)
#define GPU_RESET_BIT (U(1) << 24) #define GPU_RESET_BIT (U(1) << 24)
#define GPU_SET_BIT (U(1) << 24)
#define TEGRA_RST_DEV_SET_Y U(0x2a8)
#define NVENC_RESET_BIT (U(1) << 27)
#define TSECB_RESET_BIT (U(1) << 14)
#define APE_RESET_BIT (U(1) << 6)
#define NVJPG_RESET_BIT (U(1) << 3)
#define NVDEC_RESET_BIT (U(1) << 2)
#define TEGRA_RST_DEV_SET_L U(0x300)
#define HOST1X_RESET_BIT (U(1) << 28)
#define ISP_RESET_BIT (U(1) << 23)
#define USBD_RESET_BIT (U(1) << 22)
#define VI_RESET_BIT (U(1) << 20)
#define SDMMC4_RESET_BIT (U(1) << 15)
#define SDMMC1_RESET_BIT (U(1) << 14)
#define SDMMC2_RESET_BIT (U(1) << 9)
#define TEGRA_RST_DEV_SET_H U(0x308)
#define USB2_RESET_BIT (U(1) << 26)
#define APBDMA_RESET_BIT (U(1) << 2)
#define AHBDMA_RESET_BIT (U(1) << 1)
#define TEGRA_RST_DEV_SET_U U(0x310)
#define XUSB_DEV_RESET_BIT (U(1) << 31)
#define XUSB_HOST_RESET_BIT (U(1) << 25)
#define TSEC_RESET_BIT (U(1) << 19)
#define PCIE_RESET_BIT (U(1) << 6)
#define SDMMC3_RESET_BIT (U(1) << 5)
#define TEGRA_RST_DEVICES_V U(0x358)
#define TEGRA_RST_DEVICES_W U(0x35C)
#define ENTROPY_CLK_ENB_BIT (U(1) << 21)
#define TEGRA_CLK_OUT_ENB_V U(0x360)
#define SE_CLK_ENB_BIT (U(1) << 31)
#define TEGRA_CLK_OUT_ENB_W U(0x364)
#define ENTROPY_RESET_BIT (U(1) << 21)
#define TEGRA_RST_DEV_SET_V U(0x430)
#define SE_RESET_BIT (U(1) << 31)
#define HDA_RESET_BIT (U(1) << 29)
#define SATA_RESET_BIT (U(1) << 28)
#define TEGRA_RST_DEV_CLR_V U(0x434) #define TEGRA_RST_DEV_CLR_V U(0x434)
#define TEGRA_CLK_ENB_V U(0x440) #define TEGRA_CLK_ENB_V U(0x440)
/* SE Clock Offsets */
#define TEGRA_RST_DEVICES_V 0x358UL
#define SE_RESET_BIT (0x1UL << 31)
#define TEGRA_RST_DEVICES_W 0x35CUL
#define ENTROPY_CLK_ENB_BIT (0x1UL << 21)
#define TEGRA_CLK_OUT_ENB_V 0x360UL
#define SE_CLK_ENB_BIT (0x1UL << 31)
#define TEGRA_CLK_OUT_ENB_W 0x364UL
#define ENTROPY_RESET_BIT (0x1UL << 21)
/******************************************************************************* /*******************************************************************************
* Tegra Flow Controller constants * Tegra Flow Controller constants
******************************************************************************/ ******************************************************************************/
...@@ -124,6 +175,10 @@ ...@@ -124,6 +175,10 @@
******************************************************************************/ ******************************************************************************/
#define TEGRA_MISC_BASE U(0x70000000) #define TEGRA_MISC_BASE U(0x70000000)
#define HARDWARE_REVISION_OFFSET U(0x804) #define HARDWARE_REVISION_OFFSET U(0x804)
#define APB_SLAVE_SECURITY_ENABLE U(0xC00)
#define PMC_SECURITY_EN_BIT (U(1) << 13)
#define PINMUX_AUX_DVFS_PWM U(0x3184)
#define PINMUX_PWM_TRISTATE (U(1) << 4)
/******************************************************************************* /*******************************************************************************
* Tegra UART controller base addresses * Tegra UART controller base addresses
...@@ -148,6 +203,7 @@ ...@@ -148,6 +203,7 @@
* Tegra Power Mgmt Controller constants * Tegra Power Mgmt Controller constants
******************************************************************************/ ******************************************************************************/
#define TEGRA_PMC_BASE U(0x7000E400) #define TEGRA_PMC_BASE U(0x7000E400)
#define TEGRA_PMC_SIZE U(0xC00) /* 3k */
/******************************************************************************* /*******************************************************************************
* Tegra Atomics constants * Tegra Atomics constants
...@@ -180,6 +236,17 @@ ...@@ -180,6 +236,17 @@
#define MC_SMMU_PPCS_ASID_0 0x270U #define MC_SMMU_PPCS_ASID_0 0x270U
#define PPCS_SMMU_ENABLE (0x1U << 31) #define PPCS_SMMU_ENABLE (0x1U << 31)
/*******************************************************************************
* Tegra CLDVFS constants
******************************************************************************/
#define TEGRA_CL_DVFS_BASE U(0x70110000)
#define DVFS_DFLL_CTRL U(0x00)
#define ENABLE_OPEN_LOOP U(1)
#define ENABLE_CLOSED_LOOP U(2)
#define DVFS_DFLL_OUTPUT_CFG U(0x20)
#define DFLL_OUTPUT_CFG_I2C_EN_BIT (U(1) << 30)
#define DFLL_OUTPUT_CFG_CLK_EN_BIT (U(1) << 6)
/******************************************************************************* /*******************************************************************************
* Tegra SE constants * Tegra SE constants
******************************************************************************/ ******************************************************************************/
......
plat/nvidia/tegra/include/tegra_private.h
View file @ 30490b15
...@@ -46,6 +46,10 @@ typedef struct plat_params_from_bl2 { ...@@ -46,6 +46,10 @@ typedef struct plat_params_from_bl2 {
int32_t l2_ecc_parity_prot_dis; int32_t l2_ecc_parity_prot_dis;
/* SHMEM base address for storing the boot logs */ /* SHMEM base address for storing the boot logs */
uint64_t boot_profiler_shmem_base; uint64_t boot_profiler_shmem_base;
/* System Suspend Entry Firmware size */
uint64_t sc7entry_fw_size;
/* System Suspend Entry Firmware base address */
uint64_t sc7entry_fw_base;
} plat_params_from_bl2_t; } plat_params_from_bl2_t;
/******************************************************************************* /*******************************************************************************
...@@ -97,6 +101,7 @@ extern uint8_t tegra_fake_system_suspend; ...@@ -97,6 +101,7 @@ extern uint8_t tegra_fake_system_suspend;
void tegra_pm_system_suspend_entry(void); void tegra_pm_system_suspend_entry(void);
void tegra_pm_system_suspend_exit(void); void tegra_pm_system_suspend_exit(void);
int32_t tegra_system_suspended(void); int32_t tegra_system_suspended(void);
int32_t tegra_soc_cpu_standby(plat_local_state_t cpu_state);
int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state); int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state);
int32_t tegra_soc_pwr_domain_on(u_register_t mpidr); int32_t tegra_soc_pwr_domain_on(u_register_t mpidr);
int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state); int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state);
......
plat/nvidia/tegra/platform.mk
View file @ 30490b15
# #
# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. # Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
# #
...@@ -34,6 +34,9 @@ ENABLE_SVE_FOR_NS := 0 ...@@ -34,6 +34,9 @@ ENABLE_SVE_FOR_NS := 0
# enable D-cache early during CPU warmboot # enable D-cache early during CPU warmboot
WARMBOOT_ENABLE_DCACHE_EARLY := 1 WARMBOOT_ENABLE_DCACHE_EARLY := 1
# remove the standard libc
OVERRIDE_LIBC := 1
include plat/nvidia/tegra/common/tegra_common.mk include plat/nvidia/tegra/common/tegra_common.mk
include ${SOC_DIR}/platform_${TARGET_SOC}.mk include ${SOC_DIR}/platform_${TARGET_SOC}.mk
...@@ -42,3 +45,17 @@ BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_SOC}/${BUILD_TYPE} ...@@ -42,3 +45,17 @@ BUILD_PLAT := ${BUILD_BASE}/${PLAT}/${TARGET_SOC}/${BUILD_TYPE}
# platform cflags (enable signed comparisons, disable stdlib) # platform cflags (enable signed comparisons, disable stdlib)
TF_CFLAGS += -Wsign-compare -nostdlib TF_CFLAGS += -Wsign-compare -nostdlib
# override with necessary libc files for the Tegra platform
override LIBC_SRCS := $(addprefix lib/libc/, \
assert.c \
memcpy.c \
memmove.c \
memset.c \
printf.c \
putchar.c \
strlen.c \
snprintf.c)
INCLUDES += -Iinclude/lib/libc \
-Iinclude/lib/libc/$(ARCH) \
plat/nvidia/tegra/soc/t132/plat_setup.c
View file @ 30490b15
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -101,4 +101,5 @@ uint32_t plat_get_console_from_id(int id) ...@@ -101,4 +101,5 @@ uint32_t plat_get_console_from_id(int id)
void plat_gic_setup(void) void plat_gic_setup(void)
{ {
tegra_gic_setup(NULL, 0); tegra_gic_setup(NULL, 0);
tegra_gic_init();
} }
plat/nvidia/tegra/soc/t186/plat_memctrl.c
View file @ 30490b15
/* /*
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -94,7 +94,7 @@ const static uint32_t tegra186_streamid_override_regs[] = { ...@@ -94,7 +94,7 @@ const static uint32_t tegra186_streamid_override_regs[] = {
* Array to hold the security configs for stream IDs * Array to hold the security configs for stream IDs
******************************************************************************/ ******************************************************************************/
const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = { const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(SCEW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(AFIR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(AFIW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(NVDISPLAYR1, NON_SECURE, OVERRIDE, ENABLE),
...@@ -109,17 +109,17 @@ const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = { ...@@ -109,17 +109,17 @@ const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(SATAW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(UFSHCW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(SDMMCR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(SCEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(UFSHCR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(SDMMCWAA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(SESWR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(MPCORER, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(PTCR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(BPMPW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(ETRW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE), mc_make_sec_cfg(GPUSRD, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(VICSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(SCEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(HDAW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(ISPWA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(EQOSW, NON_SECURE, OVERRIDE, ENABLE),
...@@ -129,20 +129,20 @@ const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = { ...@@ -129,20 +129,20 @@ const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(VIW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE), mc_make_sec_cfg(AXISR, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(SDMMCW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(BPMPDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(ISPRA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(NVDECSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(XUSB_DEVW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(NVDECSRD, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(MPCOREW, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(NVDISPLAYR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(BPMPDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(NVJPGSWR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(NVDECSRD1, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(TSECSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(NVJPGSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(SDMMCWA, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(SCER, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(XUSB_HOSTR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(VICSRD, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(AONDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
...@@ -151,7 +151,7 @@ const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = { ...@@ -151,7 +151,7 @@ const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(HOST1XDMAR, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(EQOSR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(SATAR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(BPMPR, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(HDAR, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(SDMMCRAB, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(ETRR, NON_SECURE, OVERRIDE, ENABLE),
...@@ -162,10 +162,10 @@ const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = { ...@@ -162,10 +162,10 @@ const static mc_streamid_security_cfg_t tegra186_streamid_sec_cfgs[] = {
mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(TSECSWRB, NON_SECURE, NO_OVERRIDE, ENABLE),
mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE), mc_make_sec_cfg(ISPWB, NON_SECURE, OVERRIDE, ENABLE),
mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE), mc_make_sec_cfg(GPUSRD2, SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(APEDMAW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(APER, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(APEW, NON_SECURE, NO_OVERRIDE, DISABLE),
mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, ENABLE), mc_make_sec_cfg(APEDMAR, NON_SECURE, NO_OVERRIDE, DISABLE),
}; };
/******************************************************************************* /*******************************************************************************
...@@ -219,9 +219,7 @@ static void tegra186_memctrl_reconfig_mss_clients(void) ...@@ -219,9 +219,7 @@ static void tegra186_memctrl_reconfig_mss_clients(void)
assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL); assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL);
wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB | wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
#if ENABLE_AFI_DEVICE
MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB | MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
#endif
MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB | MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB | MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB; MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB;
...@@ -271,9 +269,7 @@ static void tegra186_memctrl_reconfig_mss_clients(void) ...@@ -271,9 +269,7 @@ static void tegra186_memctrl_reconfig_mss_clients(void)
* MC clients with default SO_DEV override still enabled at TSA: * MC clients with default SO_DEV override still enabled at TSA:
* AONW, BPMPW, SCEW, APEW * AONW, BPMPW, SCEW, APEW
*/ */
#if ENABLE_AFI_DEVICE
mc_set_tsa_passthrough(AFIW); mc_set_tsa_passthrough(AFIW);
#endif
mc_set_tsa_passthrough(HDAW); mc_set_tsa_passthrough(HDAW);
mc_set_tsa_passthrough(SATAW); mc_set_tsa_passthrough(SATAW);
mc_set_tsa_passthrough(XUSB_HOSTW); mc_set_tsa_passthrough(XUSB_HOSTW);
...@@ -413,9 +409,7 @@ static void tegra186_memctrl_reconfig_mss_clients(void) ...@@ -413,9 +409,7 @@ static void tegra186_memctrl_reconfig_mss_clients(void)
* boot and strongly ordered MSS clients * boot and strongly ordered MSS clients
*/ */
val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL & val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL &
#if ENABLE_AFI_DEVICE
mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) & mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) &
#endif
mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) & mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) &
mc_set_pcfifo_unordered_boot_so_mss(1, SATAW); mc_set_pcfifo_unordered_boot_so_mss(1, SATAW);
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val); tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val);
......
plat/nvidia/tegra/soc/t186/plat_setup.c
View file @ 30490b15
/* /*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -91,6 +91,8 @@ static const mmap_region_t tegra_mmap[] = { ...@@ -91,6 +91,8 @@ static const mmap_region_t tegra_mmap[] = {
MT_DEVICE | MT_RW | MT_SECURE), MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */ MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
MT_DEVICE | MT_RW | MT_SECURE), MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_TMRUS_BASE, 0x1000U, /* 4KB */
MT_DEVICE | MT_RO | MT_SECURE),
MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */ MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE), MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */ MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
...@@ -194,14 +196,13 @@ static const interrupt_prop_t tegra186_interrupt_props[] = { ...@@ -194,14 +196,13 @@ static const interrupt_prop_t tegra186_interrupt_props[] = {
void plat_gic_setup(void) void plat_gic_setup(void)
{ {
tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props)); tegra_gic_setup(tegra186_interrupt_props, ARRAY_SIZE(tegra186_interrupt_props));
tegra_gic_init();
/* /*
* Initialize the FIQ handler only if the platform supports any * Initialize the FIQ handler only if the platform supports any
* FIQ interrupt sources. * FIQ interrupt sources.
*/ */
if (sizeof(tegra186_interrupt_props) > 0U) { tegra_fiq_handler_setup();
tegra_fiq_handler_setup();
}
} }
/******************************************************************************* /*******************************************************************************
......
plat/nvidia/tegra/soc/t186/plat_smmu.c
View file @ 30490b15
...@@ -161,143 +161,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra186_smmu_context[] = { ...@@ -161,143 +161,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra186_smmu_context[] = {
mc_make_sid_override_cfg(UFSHCR), mc_make_sid_override_cfg(UFSHCR),
mc_make_sid_override_cfg(NVENCSWR), mc_make_sid_override_cfg(NVENCSWR),
mc_make_sid_override_cfg(AFIW), mc_make_sid_override_cfg(AFIW),
smmu_make_gnsr0_nsec_cfg(CR0), smmu_make_cfg(TEGRA_SMMU0_BASE),
smmu_make_gnsr0_sec_cfg(IDR0),
smmu_make_gnsr0_sec_cfg(IDR1),
smmu_make_gnsr0_sec_cfg(IDR2),
smmu_make_gnsr0_nsec_cfg(GFSR),
smmu_make_gnsr0_nsec_cfg(GFSYNR0),
smmu_make_gnsr0_nsec_cfg(GFSYNR1),
smmu_make_gnsr0_nsec_cfg(TLBGSTATUS),
smmu_make_gnsr0_nsec_cfg(PIDR2),
smmu_make_smrg_group(0),
smmu_make_smrg_group(1),
smmu_make_smrg_group(2),
smmu_make_smrg_group(3),
smmu_make_smrg_group(4),
smmu_make_smrg_group(5),
smmu_make_smrg_group(6),
smmu_make_smrg_group(7),
smmu_make_smrg_group(8),
smmu_make_smrg_group(9),
smmu_make_smrg_group(10),
smmu_make_smrg_group(11),
smmu_make_smrg_group(12),
smmu_make_smrg_group(13),
smmu_make_smrg_group(14),
smmu_make_smrg_group(15),
smmu_make_smrg_group(16),
smmu_make_smrg_group(17),
smmu_make_smrg_group(18),
smmu_make_smrg_group(19),
smmu_make_smrg_group(20),
smmu_make_smrg_group(21),
smmu_make_smrg_group(22),
smmu_make_smrg_group(23),
smmu_make_smrg_group(24),
smmu_make_smrg_group(25),
smmu_make_smrg_group(26),
smmu_make_smrg_group(27),
smmu_make_smrg_group(28),
smmu_make_smrg_group(29),
smmu_make_smrg_group(30),
smmu_make_smrg_group(31),
smmu_make_smrg_group(32),
smmu_make_smrg_group(33),
smmu_make_smrg_group(34),
smmu_make_smrg_group(35),
smmu_make_smrg_group(36),
smmu_make_smrg_group(37),
smmu_make_smrg_group(38),
smmu_make_smrg_group(39),
smmu_make_smrg_group(40),
smmu_make_smrg_group(41),
smmu_make_smrg_group(42),
smmu_make_smrg_group(43),
smmu_make_smrg_group(44),
smmu_make_smrg_group(45),
smmu_make_smrg_group(46),
smmu_make_smrg_group(47),
smmu_make_smrg_group(48),
smmu_make_smrg_group(49),
smmu_make_smrg_group(50),
smmu_make_smrg_group(51),
smmu_make_smrg_group(52),
smmu_make_smrg_group(53),
smmu_make_smrg_group(54),
smmu_make_smrg_group(55),
smmu_make_smrg_group(56),
smmu_make_smrg_group(57),
smmu_make_smrg_group(58),
smmu_make_smrg_group(59),
smmu_make_smrg_group(60),
smmu_make_smrg_group(61),
smmu_make_smrg_group(62),
smmu_make_smrg_group(63),
smmu_make_cb_group(0),
smmu_make_cb_group(1),
smmu_make_cb_group(2),
smmu_make_cb_group(3),
smmu_make_cb_group(4),
smmu_make_cb_group(5),
smmu_make_cb_group(6),
smmu_make_cb_group(7),
smmu_make_cb_group(8),
smmu_make_cb_group(9),
smmu_make_cb_group(10),
smmu_make_cb_group(11),
smmu_make_cb_group(12),
smmu_make_cb_group(13),
smmu_make_cb_group(14),
smmu_make_cb_group(15),
smmu_make_cb_group(16),
smmu_make_cb_group(17),
smmu_make_cb_group(18),
smmu_make_cb_group(19),
smmu_make_cb_group(20),
smmu_make_cb_group(21),
smmu_make_cb_group(22),
smmu_make_cb_group(23),
smmu_make_cb_group(24),
smmu_make_cb_group(25),
smmu_make_cb_group(26),
smmu_make_cb_group(27),
smmu_make_cb_group(28),
smmu_make_cb_group(29),
smmu_make_cb_group(30),
smmu_make_cb_group(31),
smmu_make_cb_group(32),
smmu_make_cb_group(33),
smmu_make_cb_group(34),
smmu_make_cb_group(35),
smmu_make_cb_group(36),
smmu_make_cb_group(37),
smmu_make_cb_group(38),
smmu_make_cb_group(39),
smmu_make_cb_group(40),
smmu_make_cb_group(41),
smmu_make_cb_group(42),
smmu_make_cb_group(43),
smmu_make_cb_group(44),
smmu_make_cb_group(45),
smmu_make_cb_group(46),
smmu_make_cb_group(47),
smmu_make_cb_group(48),
smmu_make_cb_group(49),
smmu_make_cb_group(50),
smmu_make_cb_group(51),
smmu_make_cb_group(52),
smmu_make_cb_group(53),
smmu_make_cb_group(54),
smmu_make_cb_group(55),
smmu_make_cb_group(56),
smmu_make_cb_group(57),
smmu_make_cb_group(58),
smmu_make_cb_group(59),
smmu_make_cb_group(60),
smmu_make_cb_group(61),
smmu_make_cb_group(62),
smmu_make_cb_group(63),
smmu_bypass_cfg, /* TBU settings */ smmu_bypass_cfg, /* TBU settings */
_END_OF_TABLE_, _END_OF_TABLE_,
}; };
......
plat/nvidia/tegra/soc/t186/platform_t186.mk
View file @ 30490b15
# #
# Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. # Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
# #
# platform configs # platform configs
ENABLE_AFI_DEVICE := 1
$(eval $(call add_define,ENABLE_AFI_DEVICE))
ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 1 ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS := 1
$(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS)) $(eval $(call add_define,ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS))
...@@ -33,7 +30,7 @@ $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) ...@@ -33,7 +30,7 @@ $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
MAX_XLAT_TABLES := 24 MAX_XLAT_TABLES := 24
$(eval $(call add_define,MAX_XLAT_TABLES)) $(eval $(call add_define,MAX_XLAT_TABLES))
MAX_MMAP_REGIONS := 24 MAX_MMAP_REGIONS := 25
$(eval $(call add_define,MAX_MMAP_REGIONS)) $(eval $(call add_define,MAX_MMAP_REGIONS))
# platform files # platform files
......
plat/nvidia/tegra/soc/t210/plat_psci_handlers.c
View file @ 30490b15
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -15,12 +15,14 @@ ...@@ -15,12 +15,14 @@
#include <bpmp.h> #include <bpmp.h>
#include <flowctrl.h> #include <flowctrl.h>
#include <memctrl.h>
#include <pmc.h> #include <pmc.h>
#include <platform_def.h> #include <platform_def.h>
#include <security_engine.h> #include <security_engine.h>
#include <tegra_def.h> #include <tegra_def.h>
#include <tegra_private.h> #include <tegra_private.h>
#include <tegra_platform.h> #include <tegra_platform.h>
#include <utils.h>
/* /*
* Register used to clear CPU reset signals. Each CPU has two reset * Register used to clear CPU reset signals. Each CPU has two reset
...@@ -35,11 +37,13 @@ ...@@ -35,11 +37,13 @@
#define SCLK_BURST_POLICY_DEFAULT 0x10000000 #define SCLK_BURST_POLICY_DEFAULT 0x10000000
static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER]; static int cpu_powergate_mask[PLATFORM_MAX_CPUS_PER_CLUSTER];
static bool tegra_bpmp_available = true;
int32_t tegra_soc_validate_power_state(unsigned int power_state, int32_t tegra_soc_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state) psci_power_state_t *req_state)
{ {
int state_id = psci_get_pstate_id(power_state); int state_id = psci_get_pstate_id(power_state);
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
/* Sanity check the requested state id */ /* Sanity check the requested state id */
switch (state_id) { switch (state_id) {
...@@ -52,16 +56,24 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, ...@@ -52,16 +56,24 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
break; break;
case PSTATE_ID_CLUSTER_IDLE: case PSTATE_ID_CLUSTER_IDLE:
case PSTATE_ID_CLUSTER_POWERDN:
/* /*
* Cluster powerdown/idle request only for afflvl 1 * Cluster idle request for afflvl 0
*/ */
req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN; req_state->pwr_domain_state[MPIDR_AFFLVL0] = PSTATE_ID_CORE_POWERDN;
req_state->pwr_domain_state[MPIDR_AFFLVL1] = state_id;
break; break;
case PSTATE_ID_SOC_POWERDN: case PSTATE_ID_SOC_POWERDN:
/*
* sc7entry-fw must be present in the system when the bpmp
* firmware is not present, for a successful System Suspend
* entry.
*/
if (!tegra_bpmp_init() && !plat_params->sc7entry_fw_base)
return PSCI_E_NOT_SUPPORTED;
/* /*
* System powerdown request only for afflvl 2 * System powerdown request only for afflvl 2
*/ */
...@@ -83,7 +95,7 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state, ...@@ -83,7 +95,7 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
/******************************************************************************* /*******************************************************************************
* Platform handler to calculate the proper target power level at the * Platform handler to calculate the proper target power level at the
* specified affinity level * specified affinity level.
******************************************************************************/ ******************************************************************************/
plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
const plat_local_state_t *states, const plat_local_state_t *states,
...@@ -92,7 +104,7 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, ...@@ -92,7 +104,7 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
plat_local_state_t target = PSCI_LOCAL_STATE_RUN; plat_local_state_t target = PSCI_LOCAL_STATE_RUN;
int cpu = plat_my_core_pos(); int cpu = plat_my_core_pos();
int core_pos = read_mpidr() & MPIDR_CPU_MASK; int core_pos = read_mpidr() & MPIDR_CPU_MASK;
uint32_t bpmp_reply, data[3]; uint32_t bpmp_reply, data[3], val;
int ret; int ret;
/* get the power state at this level */ /* get the power state at this level */
...@@ -107,40 +119,44 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl, ...@@ -107,40 +119,44 @@ plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
ret = tegra_bpmp_init(); ret = tegra_bpmp_init();
if (ret != 0U) { if (ret != 0U) {
/*
* flag to indicate that BPMP firmware is not
* available and the CPU has to handle entry/exit
* for all power states
*/
tegra_bpmp_available = false;
/* Cluster idle not allowed */ /* Cluster idle not allowed */
target = PSCI_LOCAL_STATE_RUN; target = PSCI_LOCAL_STATE_RUN;
} else {
/* Cluster idle */
data[0] = (uint32_t)cpu;
data[1] = TEGRA_PM_CC6;
data[2] = TEGRA_PM_SC1;
ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE,
(void *)&data, (int)sizeof(data),
(void *)&bpmp_reply,
(int)sizeof(bpmp_reply));
/* check if cluster idle entry is allowed */
if ((ret != 0L) || (bpmp_reply != BPMP_CCx_ALLOWED)) {
/* Cluster idle not allowed */ /*******************************************
target = PSCI_LOCAL_STATE_RUN; * BPMP is not present, so handle CC6 entry
* from the CPU
******************************************/
/* check if cluster idle state has been enabled */
val = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL);
if (val == ENABLE_CLOSED_LOOP) {
/*
* Acquire the cluster idle lock to stop
* other CPUs from powering up.
*/
tegra_fc_ccplex_pgexit_lock();
/* Cluster idle only from the last standing CPU */
if (tegra_pmc_is_last_on_cpu() && tegra_fc_is_ccx_allowed()) {
/* Cluster idle allowed */
target = PSTATE_ID_CLUSTER_IDLE;
} else {
/* release cluster idle lock */
tegra_fc_ccplex_pgexit_unlock();
}
} }
}
} else if ((lvl == MPIDR_AFFLVL1) && (target == PSTATE_ID_CLUSTER_POWERDN)) {
/* initialize the bpmp interface */
ret = tegra_bpmp_init();
if (ret != 0U) {
/* Cluster power down not allowed */
target = PSCI_LOCAL_STATE_RUN;
} else { } else {
/* Cluster power-down */ /* Cluster power-down */
data[0] = (uint32_t)cpu; data[0] = (uint32_t)cpu;
data[1] = TEGRA_PM_CC7; data[1] = TEGRA_PM_CC6;
data[2] = TEGRA_PM_SC1; data[2] = TEGRA_PM_SC1;
ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE, ret = tegra_bpmp_send_receive_atomic(MRQ_DO_IDLE,
(void *)&data, (int)sizeof(data), (void *)&data, (int)sizeof(data),
...@@ -176,7 +192,9 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) ...@@ -176,7 +192,9 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2]; unsigned int stateid_afflvl2 = pwr_domain_state[MPIDR_AFFLVL2];
unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1]; unsigned int stateid_afflvl1 = pwr_domain_state[MPIDR_AFFLVL1];
unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0]; unsigned int stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0];
uint32_t cfg;
int ret = PSCI_E_SUCCESS; int ret = PSCI_E_SUCCESS;
uint32_t val;
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
...@@ -197,16 +215,43 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) ...@@ -197,16 +215,43 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN); assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN);
if (!tegra_bpmp_available) {
/*
* When disabled, DFLL loses its state. Enable
* open loop state for the DFLL as we dont want
* garbage values being written to the pmic
* when we enter cluster idle state.
*/
mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL,
ENABLE_OPEN_LOOP);
/* Find if the platform uses OVR2/MAX77621 PMIC */
cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG);
if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) {
/* OVR2 */
/* PWM tristate */
val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);
val |= PINMUX_PWM_TRISTATE;
mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val);
/*
* SCRATCH201[1] is being used to identify CPU
* PMIC in warmboot code.
* 0 : OVR2
* 1 : MAX77621
*/
tegra_pmc_write_32(PMC_SCRATCH201, 0x0);
} else {
/* MAX77621 */
tegra_pmc_write_32(PMC_SCRATCH201, 0x2);
}
}
/* Prepare for cluster idle */ /* Prepare for cluster idle */
tegra_fc_cluster_idle(mpidr); tegra_fc_cluster_idle(mpidr);
} else if (stateid_afflvl1 == PSTATE_ID_CLUSTER_POWERDN) {
assert(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN);
/* Prepare for cluster powerdn */
tegra_fc_cluster_powerdn(mpidr);
} else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) { } else if (stateid_afflvl0 == PSTATE_ID_CORE_POWERDN) {
/* Prepare for cpu powerdn */ /* Prepare for cpu powerdn */
...@@ -221,12 +266,82 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state) ...@@ -221,12 +266,82 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
return ret; return ret;
} }
static void tegra_reset_all_dma_masters(void)
{
uint32_t val, mask;
/*
* Reset all possible DMA masters in the system.
*/
val = GPU_RESET_BIT;
mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET, val);
val = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT |
NVJPG_RESET_BIT | NVDEC_RESET_BIT;
mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y, val);
val = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT |
VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT |
SDMMC2_RESET_BIT;
mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L, val);
val = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT;
mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H, val);
val = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT |
PCIE_RESET_BIT | SDMMC3_RESET_BIT;
mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U, val);
val = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT;
mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V, val);
/*
* If any of the DMA masters are still alive, assume
* that the system has been compromised and reboot.
*/
val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_GPU_RESET_REG_OFFSET);
mask = GPU_RESET_BIT;
if ((val & mask) != mask)
tegra_pmc_system_reset();
mask = NVENC_RESET_BIT | TSECB_RESET_BIT | APE_RESET_BIT |
NVJPG_RESET_BIT | NVDEC_RESET_BIT;
val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_Y);
if ((val & mask) != mask)
tegra_pmc_system_reset();
mask = HOST1X_RESET_BIT | ISP_RESET_BIT | USBD_RESET_BIT |
VI_RESET_BIT | SDMMC4_RESET_BIT | SDMMC1_RESET_BIT |
SDMMC2_RESET_BIT;
val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_L);
if ((val & mask) != mask)
tegra_pmc_system_reset();
mask = USB2_RESET_BIT | APBDMA_RESET_BIT | AHBDMA_RESET_BIT;
val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_H);
if ((val & mask) != mask)
tegra_pmc_system_reset();
mask = XUSB_DEV_RESET_BIT | XUSB_HOST_RESET_BIT | TSEC_RESET_BIT |
PCIE_RESET_BIT | SDMMC3_RESET_BIT;
val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_U);
if ((val & mask) != mask)
tegra_pmc_system_reset();
val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEV_SET_V);
mask = SE_RESET_BIT | HDA_RESET_BIT | SATA_RESET_BIT;
if ((val & mask) != mask)
tegra_pmc_system_reset();
}
int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
{ {
u_register_t mpidr = read_mpidr(); u_register_t mpidr = read_mpidr();
const plat_local_state_t *pwr_domain_state = const plat_local_state_t *pwr_domain_state =
target_state->pwr_domain_state; target_state->pwr_domain_state;
unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL]; unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL];
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
uint32_t val;
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) { if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
...@@ -235,6 +350,61 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) ...@@ -235,6 +350,61 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
tegra_se_save_tzram(); tegra_se_save_tzram();
} }
/* de-init the interface */
tegra_bpmp_suspend();
/*
* The CPU needs to load the System suspend entry firmware
* if nothing is running on the BPMP.
*/
if (!tegra_bpmp_available) {
/*
* BPMP firmware is not running on the co-processor, so
* we need to explicitly load the firmware to enable
* entry/exit to/from System Suspend and set the BPMP
* on its way.
*/
/* Power off BPMP before we proceed */
tegra_fc_bpmp_off();
/* bond out IRAM banks B, C and D */
mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_U,
IRAM_B_LOCK_BIT | IRAM_C_LOCK_BIT |
IRAM_D_LOCK_BIT);
/* bond out APB/AHB DMAs */
mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_BOND_OUT_H,
APB_DMA_LOCK_BIT | AHB_DMA_LOCK_BIT);
/* Power off BPMP before we proceed */
tegra_fc_bpmp_off();
/*
* Reset all the hardware blocks that can act as DMA
* masters on the bus.
*/
tegra_reset_all_dma_masters();
/* clean up IRAM of any cruft */
zeromem((void *)(uintptr_t)TEGRA_IRAM_BASE,
TEGRA_IRAM_A_SIZE);
/* Copy the firmware to BPMP's internal RAM */
(void)memcpy((void *)(uintptr_t)TEGRA_IRAM_BASE,
(const void *)(plat_params->sc7entry_fw_base + SC7ENTRY_FW_HEADER_SIZE_BYTES),
plat_params->sc7entry_fw_size - SC7ENTRY_FW_HEADER_SIZE_BYTES);
/* Power on the BPMP and execute from IRAM base */
tegra_fc_bpmp_on(TEGRA_IRAM_BASE);
/* Wait until BPMP powers up */
do {
val = mmio_read_32(TEGRA_RES_SEMA_BASE + STA_OFFSET);
} while (val != SIGN_OF_LIFE);
}
/* enter system suspend */ /* enter system suspend */
tegra_fc_soc_powerdn(mpidr); tegra_fc_soc_powerdn(mpidr);
} }
...@@ -245,7 +415,9 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state) ...@@ -245,7 +415,9 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
{ {
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params(); const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
uint32_t val; uint32_t cfg;
uint32_t val, entrypoint = 0;
uint64_t offset;
/* platform parameter passed by the previous bootloader */ /* platform parameter passed by the previous bootloader */
if (plat_params->l2_ecc_parity_prot_dis != 1) { if (plat_params->l2_ecc_parity_prot_dis != 1) {
...@@ -284,9 +456,61 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) ...@@ -284,9 +456,61 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
/* /*
* Restore Boot and Power Management Processor (BPMP) reset * Restore Boot and Power Management Processor (BPMP) reset
* address and reset it. * address and reset it, if it is supported by the platform.
*/ */
tegra_fc_reset_bpmp(); if (!tegra_bpmp_available) {
tegra_fc_bpmp_off();
} else {
entrypoint = tegra_pmc_read_32(PMC_SCRATCH39);
tegra_fc_bpmp_on(entrypoint);
/* initialise the interface */
tegra_bpmp_resume();
}
/* sc7entry-fw is part of TZDRAM area */
if (plat_params->sc7entry_fw_base != 0U) {
offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
plat_params->tzdram_size + offset);
/* restrict PMC access to secure world */
val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
val |= PMC_SECURITY_EN_BIT;
mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
}
}
/*
* Check if we are exiting cluster idle state
*/
if (target_state->pwr_domain_state[MPIDR_AFFLVL1] ==
PSTATE_ID_CLUSTER_IDLE) {
if (!tegra_bpmp_available) {
/* PWM un-tristate */
cfg = mmio_read_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_OUTPUT_CFG);
if (cfg & DFLL_OUTPUT_CFG_CLK_EN_BIT) {
val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);
val &= ~PINMUX_PWM_TRISTATE;
mmio_write_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM, val);
/* make sure the setting took effect */
val = mmio_read_32(TEGRA_MISC_BASE + PINMUX_AUX_DVFS_PWM);
assert((val & PINMUX_PWM_TRISTATE) == 0U);
}
/*
* Restore operation mode for the DFLL ring
* oscillator
*/
mmio_write_32(TEGRA_CL_DVFS_BASE + DVFS_DFLL_CTRL,
ENABLE_CLOSED_LOOP);
/* release cluster idle lock */
tegra_fc_ccplex_pgexit_unlock();
}
} }
/* /*
...@@ -296,6 +520,12 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state) ...@@ -296,6 +520,12 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
*/ */
tegra_fc_lock_active_cluster(); tegra_fc_lock_active_cluster();
/*
* Resume PMC hardware block for Tegra210 platforms supporting sc7entry-fw
*/
if (!tegra_chipid_is_t210_b01() && (plat_params->sc7entry_fw_base != 0U))
tegra_pmc_resume();
return PSCI_E_SUCCESS; return PSCI_E_SUCCESS;
} }
......
plat/nvidia/tegra/soc/t210/plat_setup.c
View file @ 30490b15
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
#include <arch_helpers.h> #include <arch_helpers.h>
#include <bpmp.h> #include <assert.h>
#include <cortex_a57.h> #include <cortex_a57.h>
#include <common/bl_common.h> #include <common/bl_common.h>
#include <common/debug.h>
#include <common/interrupt_props.h>
#include <drivers/console.h> #include <drivers/console.h>
#include <lib/xlat_tables/xlat_tables_v2.h> #include <lib/xlat_tables/xlat_tables_v2.h>
#include <drivers/arm/gic_common.h>
#include <drivers/arm/gicv2.h>
#include <bl31/interrupt_mgmt.h>
#include <bpmp.h>
#include <flowctrl.h>
#include <memctrl.h>
#include <platform.h> #include <platform.h>
#include <security_engine.h> #include <security_engine.h>
#include <tegra_def.h> #include <tegra_def.h>
...@@ -137,10 +146,76 @@ void plat_early_platform_setup(void) ...@@ -137,10 +146,76 @@ void plat_early_platform_setup(void)
} }
} }
/* Secure IRQs for Tegra186 */
static const interrupt_prop_t tegra210_interrupt_props[] = {
INTR_PROP_DESC(TEGRA210_WDT_CPU_LEGACY_FIQ, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
};
void plat_late_platform_setup(void)
{
const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
uint64_t sc7entry_end, offset;
int ret;
uint32_t val;
/* memmap TZDRAM area containing the SC7 Entry Firmware */
if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) {
assert(plat_params->sc7entry_fw_size <= TEGRA_IRAM_A_SIZE);
/*
* Verify that the SC7 entry firmware resides inside the TZDRAM
* aperture, _before_ the BL31 code and the start address is
* exactly 1MB from BL31 base.
*/
/* sc7entry-fw must be _before_ BL31 base */
assert(plat_params->tzdram_base > plat_params->sc7entry_fw_base);
sc7entry_end = plat_params->sc7entry_fw_base +
plat_params->sc7entry_fw_size;
assert(sc7entry_end < plat_params->tzdram_base);
/* sc7entry-fw start must be exactly 1MB behind BL31 base */
offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
assert(offset == 0x100000);
/* secure TZDRAM area */
tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
plat_params->tzdram_size + offset);
/* power off BPMP processor until SC7 entry */
tegra_fc_bpmp_off();
/* memmap SC7 entry firmware code */
ret = mmap_add_dynamic_region(plat_params->sc7entry_fw_base,
plat_params->sc7entry_fw_base,
plat_params->sc7entry_fw_size,
MT_SECURE | MT_RO_DATA);
assert(ret == 0);
/* restrict PMC access to secure world */
val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
val |= PMC_SECURITY_EN_BIT;
mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
}
}
/******************************************************************************* /*******************************************************************************
* Initialize the GIC and SGIs * Initialize the GIC and SGIs
******************************************************************************/ ******************************************************************************/
void plat_gic_setup(void) void plat_gic_setup(void)
{ {
tegra_gic_setup(NULL, 0); tegra_gic_setup(tegra210_interrupt_props, ARRAY_SIZE(tegra210_interrupt_props));
tegra_gic_init();
/* Enable handling for FIQs */
tegra_fiq_handler_setup();
/*
* Enable routing watchdog FIQs from the flow controller to
* the GICD.
*/
tegra_fc_enable_fiq_to_ccplex_routing();
} }
plat/nvidia/tegra/soc/t210/plat_sip_calls.c 0 → 100644
View file @ 30490b15
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
#include <assert.h>
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/runtime_svc.h>
#include <errno.h>
#include <mmio.h>
#include <utils_def.h>
#include <memctrl.h>
#include <pmc.h>
#include <tegra_private.h>
#include <tegra_platform.h>
#include <tegra_def.h>
/*******************************************************************************
* PMC parameters
******************************************************************************/
#define PMC_READ U(0xaa)
#define PMC_WRITE U(0xbb)
/*******************************************************************************
* Tegra210 SiP SMCs
******************************************************************************/
#define TEGRA_SIP_PMC_COMMANDS U(0xC2FFFE00)
/*******************************************************************************
* This function is responsible for handling all T210 SiP calls
******************************************************************************/
int plat_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
uint64_t x4,
const void *cookie,
void *handle,
uint64_t flags)
{
uint32_t val, ns;
/* Determine which security state this SMC originated from */
ns = is_caller_non_secure(flags);
if (!ns)
SMC_RET1(handle, SMC_UNK);
switch (smc_fid) {
case TEGRA_SIP_PMC_COMMANDS:
/* check the address is within PMC range and is 4byte aligned */
if ((x2 >= TEGRA_PMC_SIZE) || (x2 & 0x3))
return -EINVAL;
/* pmc_secure_scratch registers are not accessible */
if (((x2 >= PMC_SECURE_SCRATCH0) && (x2 <= PMC_SECURE_SCRATCH5)) ||
((x2 >= PMC_SECURE_SCRATCH6) && (x2 <= PMC_SECURE_SCRATCH7)) ||
((x2 >= PMC_SECURE_SCRATCH8) && (x2 <= PMC_SECURE_SCRATCH79)) ||
((x2 >= PMC_SECURE_SCRATCH80) && (x2 <= PMC_SECURE_SCRATCH119)))
return -EFAULT;
/* PMC secure-only registers are not accessible */
if ((x2 == PMC_DPD_ENABLE_0) || (x2 == PMC_FUSE_CONTROL_0) ||
(x2 == PMC_CRYPTO_OP_0))
return -EFAULT;
/* Perform PMC read/write */
if (x1 == PMC_READ) {
val = mmio_read_32((uint32_t)(TEGRA_PMC_BASE + x2));
write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, val);
} else if (x1 == PMC_WRITE) {
mmio_write_32((uint32_t)(TEGRA_PMC_BASE + x2), (uint32_t)x3);
} else {
return -EINVAL;
}
break;
default:
ERROR("%s: unsupported function ID\n", __func__);
return -ENOTSUP;
}
return 0;
}
plat/nvidia/tegra/soc/t210/platform_t210.mk
View file @ 30490b15
# #
# Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. # Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
# #
# SPDX-License-Identifier: BSD-3-Clause # SPDX-License-Identifier: BSD-3-Clause
# #
...@@ -19,9 +19,12 @@ $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER)) ...@@ -19,9 +19,12 @@ $(eval $(call add_define,PLATFORM_MAX_CPUS_PER_CLUSTER))
MAX_XLAT_TABLES := 10 MAX_XLAT_TABLES := 10
$(eval $(call add_define,MAX_XLAT_TABLES)) $(eval $(call add_define,MAX_XLAT_TABLES))
MAX_MMAP_REGIONS := 15 MAX_MMAP_REGIONS := 16
$(eval $(call add_define,MAX_MMAP_REGIONS)) $(eval $(call add_define,MAX_MMAP_REGIONS))
ENABLE_WDT_LEGACY_FIQ_HANDLING := 1
$(eval $(call add_define,ENABLE_WDT_LEGACY_FIQ_HANDLING))
PLAT_INCLUDES += -I${SOC_DIR}/drivers/se PLAT_INCLUDES += -I${SOC_DIR}/drivers/se
BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
...@@ -33,7 +36,8 @@ BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \ ...@@ -33,7 +36,8 @@ BL31_SOURCES += drivers/ti/uart/aarch64/16550_console.S \
${SOC_DIR}/plat_psci_handlers.c \ ${SOC_DIR}/plat_psci_handlers.c \
${SOC_DIR}/plat_setup.c \ ${SOC_DIR}/plat_setup.c \
${SOC_DIR}/drivers/se/security_engine.c \ ${SOC_DIR}/drivers/se/security_engine.c \
${SOC_DIR}/plat_secondary.c ${SOC_DIR}/plat_secondary.c \
${SOC_DIR}/plat_sip_calls.c
# Enable workarounds for selected Cortex-A57 erratas. # Enable workarounds for selected Cortex-A57 erratas.
A57_DISABLE_NON_TEMPORAL_HINT := 1 A57_DISABLE_NON_TEMPORAL_HINT := 1
...@@ -48,3 +52,6 @@ A53_DISABLE_NON_TEMPORAL_HINT := 1 ...@@ -48,3 +52,6 @@ A53_DISABLE_NON_TEMPORAL_HINT := 1
ERRATA_A53_826319 := 1 ERRATA_A53_826319 := 1
ERRATA_A53_836870 := 1 ERRATA_A53_836870 := 1
ERRATA_A53_855873 := 1 ERRATA_A53_855873 := 1
# Skip L1 $ flush when powering down Cortex-A57 CPUs
SKIP_A57_L1_FLUSH_PWR_DWN := 1
services/spd/tlkd/tlkd_common.c
View file @ 30490b15
...@@ -126,7 +126,6 @@ uint64_t tlkd_synchronous_sp_entry(tlk_context_t *tlk_ctx) ...@@ -126,7 +126,6 @@ uint64_t tlkd_synchronous_sp_entry(tlk_context_t *tlk_ctx)
/* Passing a NULL context is a critical programming error */ /* Passing a NULL context is a critical programming error */
assert(tlk_ctx); assert(tlk_ctx);
assert(tlk_ctx->c_rt_ctx == 0);
/* Apply the Secure EL1 system register context and switch to it */ /* Apply the Secure EL1 system register context and switch to it */
assert(cm_get_context(SECURE) == &tlk_ctx->cpu_ctx); assert(cm_get_context(SECURE) == &tlk_ctx->cpu_ctx);
......
services/spd/tlkd/tlkd_main.c
View file @ 30490b15
...@@ -195,14 +195,18 @@ static uintptr_t tlkd_smc_handler(uint32_t smc_fid, ...@@ -195,14 +195,18 @@ static uintptr_t tlkd_smc_handler(uint32_t smc_fid,
* b. register shared memory with the SP for passing args * b. register shared memory with the SP for passing args
* required for maintaining sessions with the Trusted * required for maintaining sessions with the Trusted
* Applications. * Applications.
* c. register non-secure world's memory map with the OS * c. register shared persistent buffers for secure storage
* d. open/close sessions * d. register NS DRAM ranges passed by Cboot
* e. issue commands to the Trusted Apps * e. register Root of Trust parameters from Cboot for Verified Boot
* f. resume the preempted yielding SMC call. * f. open/close sessions
* g. issue commands to the Trusted Apps
* h. resume the preempted yielding SMC call.
*/ */
case TLK_REGISTER_LOGBUF: case TLK_REGISTER_LOGBUF:
case TLK_REGISTER_REQBUF: case TLK_REGISTER_REQBUF:
case TLK_REGISTER_NS_DRAM: case TLK_SS_REGISTER_HANDLER:
case TLK_REGISTER_NS_DRAM_RANGES:
case TLK_SET_ROOT_OF_TRUST:
case TLK_OPEN_TA_SESSION: case TLK_OPEN_TA_SESSION:
case TLK_CLOSE_TA_SESSION: case TLK_CLOSE_TA_SESSION:
case TLK_TA_LAUNCH_OP: case TLK_TA_LAUNCH_OP:
...@@ -400,6 +404,7 @@ static uintptr_t tlkd_smc_handler(uint32_t smc_fid, ...@@ -400,6 +404,7 @@ static uintptr_t tlkd_smc_handler(uint32_t smc_fid,
SMC_RET2(handle, TLK_VERSION_MAJOR, TLK_VERSION_MINOR); SMC_RET2(handle, TLK_VERSION_MAJOR, TLK_VERSION_MINOR);
default: default:
WARN("%s: Unhandled SMC: 0x%x\n", __func__, smc_fid);
break; break;
} }
......
services/spd/trusty/trusty.c
View file @ 30490b15
...@@ -7,6 +7,7 @@ ...@@ -7,6 +7,7 @@
#include <assert.h> #include <assert.h>
#include <stdbool.h> #include <stdbool.h>
#include <string.h> #include <string.h>
#include <xlat_tables_v2.h>
#include <arch_helpers.h> #include <arch_helpers.h>
#include <bl31/bl31.h> #include <bl31/bl31.h>
...@@ -352,32 +353,32 @@ static void trusty_cpu_resume(uint32_t on) ...@@ -352,32 +353,32 @@ static void trusty_cpu_resume(uint32_t on)
} }
} }
static int32_t trusty_cpu_off_handler(u_register_t unused) static int32_t trusty_cpu_off_handler(u_register_t max_off_lvl)
{ {
trusty_cpu_suspend(1); trusty_cpu_suspend(max_off_lvl);
return 0; return 0;
} }
static void trusty_cpu_on_finish_handler(u_register_t unused) static void trusty_cpu_on_finish_handler(u_register_t max_off_lvl)
{ {
struct trusty_cpu_ctx *ctx = get_trusty_ctx(); struct trusty_cpu_ctx *ctx = get_trusty_ctx();
if (ctx->saved_sp == NULL) { if (ctx->saved_sp == NULL) {
(void)trusty_init(); (void)trusty_init();
} else { } else {
trusty_cpu_resume(1); trusty_cpu_resume(max_off_lvl);
} }
} }
static void trusty_cpu_suspend_handler(u_register_t unused) static void trusty_cpu_suspend_handler(u_register_t max_off_lvl)
{ {
trusty_cpu_suspend(0); trusty_cpu_suspend(max_off_lvl);
} }
static void trusty_cpu_suspend_finish_handler(u_register_t unused) static void trusty_cpu_suspend_finish_handler(u_register_t max_off_lvl)
{ {
trusty_cpu_resume(0); trusty_cpu_resume(max_off_lvl);
} }
static const spd_pm_ops_t trusty_pm = { static const spd_pm_ops_t trusty_pm = {
...@@ -412,6 +413,14 @@ static int32_t trusty_setup(void) ...@@ -412,6 +413,14 @@ static int32_t trusty_setup(void)
return -1; return -1;
} }
/* memmap first page of trusty's code memory before peeking */
ret = mmap_add_dynamic_region(ep_info->pc, /* PA */
ep_info->pc, /* VA */
PAGE_SIZE, /* size */
MT_SECURE | MT_RW_DATA); /* attrs */
assert(ret == 0);
/* peek into trusty's code to see if we have a 32-bit or 64-bit image */
instr = *(uint32_t *)ep_info->pc; instr = *(uint32_t *)ep_info->pc;
if (instr >> 24 == 0xeaU) { if (instr >> 24 == 0xeaU) {
...@@ -424,6 +433,9 @@ static int32_t trusty_setup(void) ...@@ -424,6 +433,9 @@ static int32_t trusty_setup(void)
return -1; return -1;
} }
/* unmap trusty's memory page */
(void)mmap_remove_dynamic_region(ep_info->pc, PAGE_SIZE);
SET_PARAM_HEAD(ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE); SET_PARAM_HEAD(ep_info, PARAM_EP, VERSION_1, SECURE | EP_ST_ENABLE);
if (!aarch32) if (!aarch32)
ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX, ep_info->spsr = SPSR_64(MODE_EL1, MODE_SP_ELX,
......
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