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Commit 328718f2 authored by Hadi Asyrafi's avatar Hadi Asyrafi
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intel: Refactor common platform code [1/5] 


Pull out handoff driver to intel/soc/ common directory as they can be
shared by both Agilex and Stratix10 platform.

Share platform_def header between both Agilex and Stratix10 and store
platform specific definitions in socfpga_plat_def.h
Signed-off-by: default avatarHadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I8eff1afd7ee71704a36a54fad732ede4f557878d
parent d537ee79
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with 145 additions and 405 deletions
+145 -405
plat/intel/soc/agilex/bl2_plat_setup.c
View file @ 328718f2
......@@ -18,7 +18,6 @@
#include <socfpga_private.h>
#include "agilex_clock_manager.h"
#include "agilex_handoff.h"
#include "agilex_mailbox.h"
#include "agilex_memory_controller.h"
#include "agilex_pinmux.h"
......@@ -28,6 +27,7 @@
#include "ccu/ncore_ccu.h"
#include "qspi/cadence_qspi.h"
#include "socfpga_handoff.h"
#include "wdt/watchdog.h"
......@@ -59,7 +59,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
generic_delay_timer_init();
if (agilex_get_handoff(&reverse_handoff_ptr))
if (socfpga_get_handoff(&reverse_handoff_ptr))
return;
config_pinmux(&reverse_handoff_ptr);
boot_source = reverse_handoff_ptr.boot_source;
......
plat/intel/soc/agilex/bl31_plat_setup.c
View file @ 328718f2
......@@ -67,15 +67,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
}
static const interrupt_prop_t s10_interrupt_props[] = {
PLAT_INTEL_AGX_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
PLAT_INTEL_AGX_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
};
static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
static const gicv2_driver_data_t plat_gicv2_gic_data = {
.gicd_base = PLAT_INTEL_AGX_GICD_BASE,
.gicc_base = PLAT_INTEL_AGX_GICC_BASE,
.gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
.gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
.interrupt_props = s10_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
.target_masks = target_mask_array,
......
plat/intel/soc/agilex/include/agilex_clock_manager.h
View file @ 328718f2
......@@ -7,7 +7,7 @@
#ifndef CLOCKMANAGER_H
#define CLOCKMANAGER_H
#include "agilex_handoff.h"
#include "socfpga_handoff.h"
/* Clock Manager Registers */
#define CLKMGR_OFFSET 0xffd10000
......
plat/intel/soc/agilex/include/agilex_pinmux.h
View file @ 328718f2
......@@ -12,7 +12,7 @@
#define AGX_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300
#define AGX_PINMUX_IO0_DELAY 0xffd13400
#include "agilex_handoff.h"
#include "socfpga_handoff.h"
void config_pinmux(handoff *handoff);
......
plat/intel/soc/agilex/include/socfpga_plat_def.h 0 → 100644
View file @ 328718f2
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_SOCFPGA_DEF_H
#define PLAT_SOCFPGA_DEF_H
#include <platform_def.h>
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_AGILEX
/* Register Mapping */
#define SOCFPGA_MMC_REG_BASE 0xff808000
#define SOCFPGA_RSTMGR_OFST 0xffd11000
#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020
#endif /* PLAT_SOCFPGA_DEF_H */
plat/intel/soc/agilex/platform.mk
View file @ 328718f2
......@@ -40,10 +40,10 @@ BL2_SOURCES += \
plat/intel/soc/agilex/socfpga_storage.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/agilex/soc/agilex_reset_manager.c \
plat/intel/soc/agilex/soc/agilex_handoff.c \
plat/intel/soc/agilex/soc/agilex_clock_manager.c \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
plat/intel/soc/agilex/soc/agilex_memory_controller.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/common/socfpga_delay_timer.c \
plat/intel/soc/common/socfpga_image_load.c \
plat/intel/soc/agilex/soc/agilex_system_manager.c \
......@@ -65,7 +65,6 @@ BL31_SOURCES += \
plat/intel/soc/agilex/soc/agilex_reset_manager.c \
plat/intel/soc/agilex/soc/agilex_pinmux.c \
plat/intel/soc/agilex/soc/agilex_clock_manager.c \
plat/intel/soc/agilex/soc/agilex_handoff.c \
plat/intel/soc/agilex/soc/agilex_mailbox.c
PROGRAMMABLE_RESET_ADDRESS := 0
......
plat/intel/soc/agilex/soc/agilex_clock_manager.c
View file @ 328718f2
......@@ -11,8 +11,8 @@
#include <lib/mmio.h>
#include "agilex_clock_manager.h"
#include "agilex_handoff.h"
#include "agilex_system_manager.h"
#include "socfpga_handoff.h"
uint32_t wait_pll_lock(void)
......
plat/intel/soc/agilex/include/platform_def.h → plat/intel/soc/common/include/platform_def.h
View file @ 328718f2
......@@ -13,6 +13,8 @@
#include <common/tbbr/tbbr_img_def.h>
#include <plat/common/common_def.h>
#define PLAT_SOCFPGA_STRATIX10 1
#define PLAT_SOCFPGA_AGILEX 2
#define PLAT_CPUID_RELEASE 0xffe1b000
#define PLAT_SEC_ENTRY 0xffe1b008
......@@ -27,7 +29,7 @@
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
/* Agilex supports up to 124GB RAM */
/* SoCFPGA supports up to 124GB RAM */
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
......@@ -56,18 +58,18 @@
/* Interrupt related constant */
#define INTEL_AGX_IRQ_SEC_PHY_TIMER 29
#define INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER 29
#define INTEL_AGX_IRQ_SEC_SGI_0 8
#define INTEL_AGX_IRQ_SEC_SGI_1 9
#define INTEL_AGX_IRQ_SEC_SGI_2 10
#define INTEL_AGX_IRQ_SEC_SGI_3 11
#define INTEL_AGX_IRQ_SEC_SGI_4 12
#define INTEL_AGX_IRQ_SEC_SGI_5 13
#define INTEL_AGX_IRQ_SEC_SGI_6 14
#define INTEL_AGX_IRQ_SEC_SGI_7 15
#define INTEL_SOCFPGA_IRQ_SEC_SGI_0 8
#define INTEL_SOCFPGA_IRQ_SEC_SGI_1 9
#define INTEL_SOCFPGA_IRQ_SEC_SGI_2 10
#define INTEL_SOCFPGA_IRQ_SEC_SGI_3 11
#define INTEL_SOCFPGA_IRQ_SEC_SGI_4 12
#define INTEL_SOCFPGA_IRQ_SEC_SGI_5 13
#define INTEL_SOCFPGA_IRQ_SEC_SGI_6 14
#define INTEL_SOCFPGA_IRQ_SEC_SGI_7 15
#define TSP_IRQ_SEC_PHY_TIMER INTEL_AGX_IRQ_SEC_PHY_TIMER
#define TSP_IRQ_SEC_PHY_TIMER INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER
#define TSP_SEC_MEM_BASE BL32_BASE
#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
/*******************************************************************************
......@@ -158,35 +160,35 @@
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400)
#define PLAT_INTEL_AGX_GICD_BASE PLAT_GICD_BASE
#define PLAT_INTEL_AGX_GICC_BASE PLAT_GICC_BASE
#define PLAT_INTEL_SOCFPGA_GICD_BASE PLAT_GICD_BASE
#define PLAT_INTEL_SOCFPGA_GICC_BASE PLAT_GICC_BASE
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
*/
#define PLAT_INTEL_AGX_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_AGX_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE)
#define PLAT_INTEL_AGX_G0_IRQ_PROPS(grp)
#define PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_PHY_TIMER, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_0, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_1, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_2, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_3, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_4, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_5, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_6, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_SOCFPGA_IRQ_SEC_SGI_7, \
GIC_HIGHEST_SEC_PRIORITY, grp, GIC_INTR_CFG_EDGE)
#define PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(grp)
#define MAX_IO_HANDLES 4
#define MAX_IO_DEVICES 4
......
plat/intel/soc/agilex/include/agilex_handoff.h → plat/intel/soc/common/include/socfpga_handoff.h
View file @ 328718f2
......@@ -15,6 +15,8 @@
#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
#include <socfpga_plat_def.h>
typedef struct handoff_t {
/* header */
uint32_t header_magic;
......@@ -47,6 +49,44 @@ typedef struct handoff_t {
uint32_t pinmux_iodelay_array[96]; /* offset, value */
/* clock configuration */
#if PLATFORM_MODEL == PLAT_SOCFPGA_STRATIX10
uint32_t clock_magic;
uint32_t clock_length;
uint32_t _pad_0x588_0x590[2];
uint32_t main_pll_mpuclk;
uint32_t main_pll_nocclk;
uint32_t main_pll_cntr2clk;
uint32_t main_pll_cntr3clk;
uint32_t main_pll_cntr4clk;
uint32_t main_pll_cntr5clk;
uint32_t main_pll_cntr6clk;
uint32_t main_pll_cntr7clk;
uint32_t main_pll_cntr8clk;
uint32_t main_pll_cntr9clk;
uint32_t main_pll_nocdiv;
uint32_t main_pll_pllglob;
uint32_t main_pll_fdbck;
uint32_t main_pll_pllc0;
uint32_t main_pll_pllc1;
uint32_t _pad_0x5cc_0x5d0[1];
uint32_t per_pll_cntr2clk;
uint32_t per_pll_cntr3clk;
uint32_t per_pll_cntr4clk;
uint32_t per_pll_cntr5clk;
uint32_t per_pll_cntr6clk;
uint32_t per_pll_cntr7clk;
uint32_t per_pll_cntr8clk;
uint32_t per_pll_cntr9clk;
uint32_t per_pll_emacctl;
uint32_t per_pll_gpiodiv;
uint32_t per_pll_pllglob;
uint32_t per_pll_fdbck;
uint32_t per_pll_pllc0;
uint32_t per_pll_pllc1;
uint32_t hps_osc_clk_h;
uint32_t fpga_clk_hz;
#elif PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX
uint32_t clock_magic;
uint32_t clock_length;
uint32_t _pad_0x588_0x590[2];
......@@ -80,7 +120,7 @@ typedef struct handoff_t {
uint32_t hps_osc_clk_h;
uint32_t fpga_clk_hz;
uint32_t _pad_0x604_0x610[3];
#endif
/* misc configuration */
uint32_t misc_magic;
uint32_t misc_length;
......@@ -89,7 +129,7 @@ typedef struct handoff_t {
} handoff;
int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr);
int agilex_get_handoff(handoff *hoff_ptr);
int socfpga_get_handoff(handoff *hoff_ptr);
#endif
......
plat/intel/soc/agilex/soc/agilex_handoff.c → plat/intel/soc/common/soc/socfpga_handoff.c
View file @ 328718f2
......@@ -4,15 +4,14 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <platform_def.h>
#include <string.h>
#include "agilex_handoff.h"
#include "socfpga_handoff.h"
#define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) | \
(((x) & 0x0000FF00) << 8) | ((x) << 24))
int agilex_get_handoff(handoff *reverse_hoff_ptr)
int socfpga_get_handoff(handoff *reverse_hoff_ptr)
{
int i;
uint32_t *buffer;
......
plat/intel/soc/stratix10/bl2_plat_setup.c
View file @ 328718f2
......@@ -27,11 +27,11 @@
#include "s10_memory_controller.h"
#include "s10_reset_manager.h"
#include "s10_clock_manager.h"
#include "s10_handoff.h"
#include "s10_pinmux.h"
#include "stratix10_private.h"
#include "include/s10_mailbox.h"
#include "qspi/cadence_qspi.h"
#include "socfpga_handoff.h"
#include "wdt/watchdog.h"
......@@ -63,7 +63,7 @@ void bl2_el3_early_platform_setup(u_register_t x0, u_register_t x1,
generic_delay_timer_init();
if (s10_get_handoff(&reverse_handoff_ptr))
if (socfpga_get_handoff(&reverse_handoff_ptr))
return;
config_pinmux(&reverse_handoff_ptr);
boot_source = reverse_handoff_ptr.boot_source;
......
plat/intel/soc/stratix10/bl31_plat_setup.c
View file @ 328718f2
......@@ -23,7 +23,6 @@
#include <platform_def.h>
#include "stratix10_private.h"
#include "s10_handoff.h"
#include "s10_reset_manager.h"
#include "s10_memory_controller.h"
#include "s10_pinmux.h"
......@@ -82,15 +81,15 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
}
static const interrupt_prop_t s10_interrupt_props[] = {
PLAT_INTEL_S10_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
PLAT_INTEL_S10_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
PLAT_INTEL_SOCFPGA_G1S_IRQ_PROPS(GICV2_INTR_GROUP0),
PLAT_INTEL_SOCFPGA_G0_IRQ_PROPS(GICV2_INTR_GROUP0)
};
static unsigned int target_mask_array[PLATFORM_CORE_COUNT];
static const gicv2_driver_data_t plat_gicv2_gic_data = {
.gicd_base = PLAT_INTEL_S10_GICD_BASE,
.gicc_base = PLAT_INTEL_S10_GICC_BASE,
.gicd_base = PLAT_INTEL_SOCFPGA_GICD_BASE,
.gicc_base = PLAT_INTEL_SOCFPGA_GICC_BASE,
.interrupt_props = s10_interrupt_props,
.interrupt_props_num = ARRAY_SIZE(s10_interrupt_props),
.target_masks = target_mask_array,
......
plat/intel/soc/stratix10/include/platform_def.h deleted 100644 → 0
View file @ d537ee79
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __PLATFORM_DEF_H__
#define __PLATFORM_DEF_H__
#include <arch.h>
#include <common/bl_common.h>
#include <common/interrupt_props.h>
#include <common/tbbr/tbbr_img_def.h>
#include <drivers/arm/gic_common.h>
#include <plat/common/common_def.h>
#define PLAT_CPUID_RELEASE 0xffe1b000
#define PLAT_SEC_ENTRY 0xffe1b008
/* Define next boot image name and offset */
#define PLAT_NS_IMAGE_OFFSET 0x50000
#define PLAT_HANDOFF_OFFSET 0xFFE3F000
/*******************************************************************************
* Platform binary types for linking
******************************************************************************/
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
#define PLATFORM_LINKER_ARCH aarch64
/* Stratix 10 supports up to 124GB RAM */
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 39)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 39)
/*******************************************************************************
* Generic platform constants
******************************************************************************/
#define PLAT_PRIMARY_CPU 0
#define PLAT_SECONDARY_ENTRY_BASE 0x01f78bf0
/* Size of cacheable stacks */
#define PLATFORM_STACK_SIZE 0x2000
/* PSCI related constant */
#define PLAT_NUM_POWER_DOMAINS 5
#define PLAT_MAX_PWR_LVL 1
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE 2
#define PLATFORM_SYSTEM_COUNT 1
#define PLATFORM_CLUSTER_COUNT 1
#define PLATFORM_CLUSTER0_CORE_COUNT 4
#define PLATFORM_CLUSTER1_CORE_COUNT 0
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER1_CORE_COUNT + \
PLATFORM_CLUSTER0_CORE_COUNT)
#define PLATFORM_MAX_CPUS_PER_CLUSTER 4
/* Interrupt related constant */
#define INTEL_S10_IRQ_SEC_PHY_TIMER 29
#define INTEL_S10_IRQ_SEC_SGI_0 8
#define INTEL_S10_IRQ_SEC_SGI_1 9
#define INTEL_S10_IRQ_SEC_SGI_2 10
#define INTEL_S10_IRQ_SEC_SGI_3 11
#define INTEL_S10_IRQ_SEC_SGI_4 12
#define INTEL_S10_IRQ_SEC_SGI_5 13
#define INTEL_S10_IRQ_SEC_SGI_6 14
#define INTEL_S10_IRQ_SEC_SGI_7 15
#define TSP_IRQ_SEC_PHY_TIMER INTEL_S10_IRQ_SEC_PHY_TIMER
#define TSP_SEC_MEM_BASE BL32_BASE
#define TSP_SEC_MEM_SIZE (BL32_LIMIT - BL32_BASE + 1)
/*******************************************************************************
* Platform memory map related constants
******************************************************************************/
#define DRAM_BASE (0x0)
#define DRAM_SIZE (0x80000000)
#define OCRAM_BASE (0xFFE00000)
#define OCRAM_SIZE (0x00040000)
#define MEM64_BASE (0x0100000000)
#define MEM64_SIZE (0x1F00000000)
#define DEVICE1_BASE (0x80000000)
#define DEVICE1_SIZE (0x60000000)
#define DEVICE2_BASE (0xF7000000)
#define DEVICE2_SIZE (0x08E00000)
#define DEVICE3_BASE (0xFFFC0000)
#define DEVICE3_SIZE (0x00008000)
#define DEVICE4_BASE (0x2000000000)
#define DEVICE4_SIZE (0x0100000000)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
/*
* Put BL3-1 at the top of the Trusted SRAM (just below the shared memory, if
* present). BL31_BASE is calculated using the current BL3-1 debug size plus a
* little space for growth.
*/
#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
#define BL1_RO_BASE (0xffe00000)
#define BL1_RO_LIMIT (0xffe0f000)
#define BL1_RW_BASE (0xffe10000)
#define BL1_RW_LIMIT (0xffe1ffff)
#define BL1_RW_SIZE (0x14000)
#define BL2_BASE (0xffe00000)
#define BL2_LIMIT (0xffe1b000)
#define BL31_BASE (0xffe1c000)
#define BL31_LIMIT (0xffe3bfff)
/*******************************************************************************
* Platform specific page table and MMU setup constants
******************************************************************************/
#define MAX_XLAT_TABLES 8
#define MAX_MMAP_REGIONS 16
/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is
* aligned on the biggest cache line size in the platform. This is known only
* to the platform as it might have a combination of integrated and external
* caches. Such alignment ensures that two maiboxes do not sit on the same cache
* line at any cache level. They could belong to different cpus/clusters &
* get written while being protected by different locks causing corruption of
* a valid mailbox address.
******************************************************************************/
#define CACHE_WRITEBACK_SHIFT 6
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
#define PLAT_GIC_BASE (0xFFFC0000)
#define PLAT_GICC_BASE (PLAT_GIC_BASE + 0x2000)
#define PLAT_GICD_BASE (PLAT_GIC_BASE + 0x1000)
#define PLAT_GICR_BASE 0
/*******************************************************************************
* UART related constants
******************************************************************************/
#define PLAT_UART0_BASE (0xFFC02000)
#define PLAT_UART1_BASE (0xFFC02100)
#define CRASH_CONSOLE_BASE PLAT_UART0_BASE
#define PLAT_BAUDRATE (115200)
#define PLAT_UART_CLOCK (100000000)
/*******************************************************************************
* System counter frequency related constants
******************************************************************************/
#define PLAT_SYS_COUNTER_FREQ_IN_TICKS (400000000)
#define PLAT_SYS_COUNTER_FREQ_IN_MHZ (400)
#define PLAT_INTEL_S10_GICD_BASE PLAT_GICD_BASE
#define PLAT_INTEL_S10_GICC_BASE PLAT_GICC_BASE
/*
* Define a list of Group 1 Secure and Group 0 interrupts as per GICv3
* terminology. On a GICv2 system or mode, the lists will be merged and treated
* as Group 0 interrupts.
*/
#define PLAT_INTEL_S10_G1S_IRQ_PROPS(grp) \
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, \
grp, GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE), \
INTR_PROP_DESC(INTEL_S10_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, grp, \
GIC_INTR_CFG_EDGE)
#define PLAT_INTEL_S10_G0_IRQ_PROPS(grp)
#define MAX_IO_HANDLES 4
#define MAX_IO_DEVICES 4
#define MAX_IO_BLOCK_DEVICES 2
#endif /* __PLATFORM_DEF_H__ */
plat/intel/soc/stratix10/include/s10_clock_manager.h
View file @ 328718f2
......@@ -7,7 +7,7 @@
#ifndef __CLOCKMANAGER_H__
#define __CLOCKMANAGER_H__
#include "s10_handoff.h"
#include "socfpga_handoff.h"
#define ALT_CLKMGR 0xffd10000
......
plat/intel/soc/stratix10/include/s10_handoff.h deleted 100644 → 0
View file @ d537ee79
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef _HANDOFF_H_
#define _HANDOFF_H_
#define HANDOFF_MAGIC_HEADER 0x424f4f54 /* BOOT */
#define HANDOFF_MAGIC_PINMUX_SEL 0x504d5558 /* PMUX */
#define HANDOFF_MAGIC_IOCTLR 0x494f4354 /* IOCT */
#define HANDOFF_MAGIC_FPGA 0x46504741 /* FPGA */
#define HANDOFF_MAGIC_IODELAY 0x444c4159 /* DLAY */
#define HANDOFF_MAGIC_CLOCK 0x434c4b53 /* CLKS */
#define HANDOFF_MAGIC_MISC 0x4d495343 /* MISC */
typedef struct handoff_t {
/* header */
uint32_t header_magic;
uint32_t header_device;
uint32_t _pad_0x08_0x10[2];
/* pinmux configuration - select */
uint32_t pinmux_sel_magic;
uint32_t pinmux_sel_length;
uint32_t _pad_0x18_0x20[2];
uint32_t pinmux_sel_array[96]; /* offset, value */
/* pinmux configuration - io control */
uint32_t pinmux_io_magic;
uint32_t pinmux_io_length;
uint32_t _pad_0x1a8_0x1b0[2];
uint32_t pinmux_io_array[96]; /* offset, value */
/* pinmux configuration - use fpga switch */
uint32_t pinmux_fpga_magic;
uint32_t pinmux_fpga_length;
uint32_t _pad_0x338_0x340[2];
uint32_t pinmux_fpga_array[42]; /* offset, value */
uint32_t _pad_0x3e8_0x3f0[2];
/* pinmux configuration - io delay */
uint32_t pinmux_delay_magic;
uint32_t pinmux_delay_length;
uint32_t _pad_0x3f8_0x400[2];
uint32_t pinmux_iodelay_array[96]; /* offset, value */
/* clock configuration */
uint32_t clock_magic;
uint32_t clock_length;
uint32_t _pad_0x588_0x590[2];
uint32_t main_pll_mpuclk;
uint32_t main_pll_nocclk;
uint32_t main_pll_cntr2clk;
uint32_t main_pll_cntr3clk;
uint32_t main_pll_cntr4clk;
uint32_t main_pll_cntr5clk;
uint32_t main_pll_cntr6clk;
uint32_t main_pll_cntr7clk;
uint32_t main_pll_cntr8clk;
uint32_t main_pll_cntr9clk;
uint32_t main_pll_nocdiv;
uint32_t main_pll_pllglob;
uint32_t main_pll_fdbck;
uint32_t main_pll_pllc0;
uint32_t main_pll_pllc1;
uint32_t _pad_0x5cc_0x5d0[1];
uint32_t per_pll_cntr2clk;
uint32_t per_pll_cntr3clk;
uint32_t per_pll_cntr4clk;
uint32_t per_pll_cntr5clk;
uint32_t per_pll_cntr6clk;
uint32_t per_pll_cntr7clk;
uint32_t per_pll_cntr8clk;
uint32_t per_pll_cntr9clk;
uint32_t per_pll_emacctl;
uint32_t per_pll_gpiodiv;
uint32_t per_pll_pllglob;
uint32_t per_pll_fdbck;
uint32_t per_pll_pllc0;
uint32_t per_pll_pllc1;
uint32_t hps_osc_clk_h;
uint32_t fpga_clk_hz;
/* misc configuration */
uint32_t misc_magic;
uint32_t misc_length;
uint32_t _pad_0x618_0x620[2];
uint32_t boot_source;
} handoff;
int verify_handoff_image(handoff *hoff_ptr, handoff *reverse_hoff_ptr);
int s10_get_handoff(handoff *hoff_ptr);
#endif
plat/intel/soc/stratix10/include/s10_pinmux.h
View file @ 328718f2
......@@ -12,7 +12,7 @@
#define S10_PINMUX_PINMUX_EMAC0_USEFPGA 0xffd13300
#define S10_PINMUX_IO0_DELAY 0xffd13400
#include "s10_handoff.h"
#include "socfpga_handoff.h"
void config_pinmux(handoff *handoff);
......
plat/intel/soc/stratix10/include/socfpga_plat_def.h 0 → 100644
View file @ 328718f2
/*
* Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef PLAT_SOCFPGA_DEF_H
#define PLAT_SOCFPGA_DEF_H
#include <platform_def.h>
/* Platform Setting */
#define PLATFORM_MODEL PLAT_SOCFPGA_STRATIX10
/* Register Mapping */
#define SOCFPGA_MMC_REG_BASE 0xff808000
#define SOCFPGA_RSTMGR_OFST 0xffd11000
#define SOCFPGA_RSTMGR_MPUMODRST_OFST 0xffd11020
#endif /* PLATSOCFPGA_DEF_H */
plat/intel/soc/stratix10/platform.mk
View file @ 328718f2
......@@ -37,7 +37,7 @@ BL2_SOURCES += \
plat/intel/soc/stratix10/plat_storage.c \
plat/intel/soc/common/bl2_plat_mem_params_desc.c \
plat/intel/soc/stratix10/soc/s10_reset_manager.c \
plat/intel/soc/stratix10/soc/s10_handoff.c \
plat/intel/soc/common/soc/socfpga_handoff.c \
plat/intel/soc/stratix10/soc/s10_clock_manager.c \
plat/intel/soc/stratix10/soc/s10_pinmux.c \
plat/intel/soc/stratix10/soc/s10_memory_controller.c \
......@@ -63,7 +63,6 @@ BL31_SOURCES += drivers/arm/cci/cci.c \
plat/intel/soc/stratix10/soc/s10_reset_manager.c\
plat/intel/soc/stratix10/soc/s10_pinmux.c \
plat/intel/soc/stratix10/soc/s10_clock_manager.c\
plat/intel/soc/stratix10/soc/s10_handoff.c \
plat/intel/soc/stratix10/soc/s10_mailbox.c
PROGRAMMABLE_RESET_ADDRESS := 0
......
plat/intel/soc/stratix10/soc/s10_clock_manager.c
View file @ 328718f2
......@@ -12,8 +12,8 @@
#include <platform_def.h>
#include "s10_clock_manager.h"
#include "s10_handoff.h"
#include "s10_system_manager.h"
#include "socfpga_handoff.h"
void wait_pll_lock(void)
......
plat/intel/soc/stratix10/soc/s10_handoff.c deleted 100644 → 0
View file @ d537ee79
/*
* Copyright (c) 2019, Intel Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <arch_helpers.h>
#include <drivers/arm/gicv2.h>
#include <assert.h>
#include <common/bl_common.h>
#include <lib/mmio.h>
#include <string.h>
#include <plat/common/platform.h>
#include <platform_def.h>
#include "s10_handoff.h"
#define SWAP_UINT32(x) (((x) >> 24) | (((x) & 0x00FF0000) >> 8) | \
(((x) & 0x0000FF00) << 8) | ((x) << 24))
int s10_get_handoff(handoff *reverse_hoff_ptr)
{
int i;
uint32_t *buffer;
handoff *handoff_ptr = (handoff *) PLAT_HANDOFF_OFFSET;
memcpy(reverse_hoff_ptr, handoff_ptr, sizeof(handoff));
buffer = (uint32_t *)reverse_hoff_ptr;
/* convert big indian to little indian */
for (i = 0; i < sizeof(handoff) / 4; i++)
buffer[i] = SWAP_UINT32(buffer[i]);
if (reverse_hoff_ptr->header_magic != HANDOFF_MAGIC_HEADER)
return -1;
if (reverse_hoff_ptr->pinmux_sel_magic != HANDOFF_MAGIC_PINMUX_SEL)
return -1;
if (reverse_hoff_ptr->pinmux_io_magic != HANDOFF_MAGIC_IOCTLR)
return -1;
if (reverse_hoff_ptr->pinmux_fpga_magic != HANDOFF_MAGIC_FPGA)
return -1;
if (reverse_hoff_ptr->pinmux_delay_magic != HANDOFF_MAGIC_IODELAY)
return -1;
return 0;
}
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