qemu: fix holding pen mailbox sequence

Before this change, plat_secondary_cold_boot_setup reads wake up mailbox
as a byte array but through 64bit accesses on unaligned 64bit addresses.
In the other hand qemu_pwr_domain_on wakes secondary cores by writing
into a 64bit array.

This change forces the 64bit mailbox format as PLAT_QEMU_HOLD_ENTRY_SIZE
explicitly specifies it.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>

plat/qemu/aarch64/plat_helpers.S

@@ -63,6 +63,7 @@ endfunc plat_is_my_cpu_primary
 func plat_secondary_cold_boot_setup
 	/* Calculate address of our hold entry */
 	bl	plat_my_core_pos
+	lsl	x0, x0, #PLAT_QEMU_HOLD_ENTRY_SHIFT
 	mov_imm	x2, PLAT_QEMU_HOLD_BASE
 
 	/* Wait until we have a go */

plat/qemu/include/platform_def.h

@@ -90,7 +90,8 @@
 #define PLAT_QEMU_HOLD_BASE		(PLAT_QEMU_TRUSTED_MAILBOX_BASE + 8)
 #define PLAT_QEMU_HOLD_SIZE		(PLATFORM_CORE_COUNT * \
 					 PLAT_QEMU_HOLD_ENTRY_SIZE)
-#define PLAT_QEMU_HOLD_ENTRY_SIZE	8
+#define PLAT_QEMU_HOLD_ENTRY_SHIFT	3
+#define PLAT_QEMU_HOLD_ENTRY_SIZE	(1 << PLAT_QEMU_HOLD_ENTRY_SHIFT)
 #define PLAT_QEMU_HOLD_STATE_WAIT	0
 #define PLAT_QEMU_HOLD_STATE_GO		1