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Unverified Commit 36044baf authored by Dimitris Papastamos's avatar Dimitris Papastamos Committed by GitHub
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Merge pull request #1515 from bryanodonoghue/atf-master+linaro-warp7-squash-v4 

Atf master+linaro warp7 squash v4
parents 05ca7254 622e890d
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plat/imx/common/include/imx_aips.h 0 → 100644
View file @ 36044baf
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __IMX_AIPS_H__
#define __IMX_AIPS_H__
#include <stdint.h>
#define AIPSTZ_OAPCR_COUNT 0x05
struct aipstz_regs {
uint32_t aipstz_mpr;
uint32_t res[15];
uint32_t aipstz_opacr[AIPSTZ_OAPCR_COUNT];
};
void imx_aips_init(void);
#endif /* __IMX_AIPS_H__ */
plat/imx/common/include/imx_caam.h 0 → 100644
View file @ 36044baf
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __IMX_CAAM_H__
#define __IMX_CAAM_H__
#include <stdint.h>
#include <arch.h>
#include <imx_regs.h>
struct caam_job_ring {
uint32_t jrmidr_ms;
uint32_t jrmidr_ls;
};
struct caam_rtic_mid {
uint32_t rticmidr_ms;
uint32_t rticmidr_ls;
};
struct caam_deco {
uint32_t deco_mid_ms;
uint32_t deco_mid_ls;
};
#define JOB_RING_OFFSET 0x10
#define DEBUGCTL_OFFSET 0x58
#define RES2_SIZE (DEBUGCTL_OFFSET - JOB_RING_OFFSET - \
(sizeof(struct caam_job_ring) * CAAM_NUM_JOB_RINGS))
#define RTIC_MID_OFFSET 0x60
#define DECORR_OFFSET 0x9C
#define RES3_SIZE (DECORR_OFFSET - RTIC_MID_OFFSET - \
(sizeof(struct caam_rtic_mid) * CAAM_NUM_RTIC))
#define DECO_MID_OFFSET 0xA0
#define DAR_OFFSET 0x120
#define RES4_SIZE (DAR_OFFSET - DECO_MID_OFFSET - \
(sizeof(struct caam_deco) * CAAM_NUM_DECO))
struct caam_ctrl {
uint32_t res0;
uint32_t mcfgr;
uint32_t res1;
uint32_t scfgr;
struct caam_job_ring jr[CAAM_NUM_JOB_RINGS];
uint8_t res2[RES2_SIZE];
uint32_t debuctl;
uint32_t jrstartr;
struct caam_rtic_mid mid[CAAM_NUM_RTIC];
uint8_t res3[RES3_SIZE];
uint32_t decorr;
struct caam_deco deco[CAAM_NUM_DECO];
uint8_t res4[RES4_SIZE];
uint32_t dar;
uint32_t drr;
} __packed;
/* Job ring control bits */
#define JROWN_NS BIT(3)
#define JROWN_MID 0x01
/* Declare CAAM API */
void imx_caam_init(void);
#endif /* __IMX_CAAM_H__ */
plat/imx/common/include/imx_clock.h 0 → 100644
View file @ 36044baf
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __IMX_CLOCK_H__
#define __IMX_CLOCK_H__
#include <stdint.h>
#include <stdbool.h>
struct ccm_pll_ctrl {
uint32_t ccm_pll_ctrl;
uint32_t ccm_pll_ctrl_set;
uint32_t ccm_pll_ctrl_clr;
uint32_t ccm_pll_ctrl_tog;
};
/* Clock gate control */
struct ccm_clk_gate_ctrl {
uint32_t ccm_ccgr;
uint32_t ccm_ccgr_set;
uint32_t ccm_ccgr_clr;
uint32_t ccm_ccgr_tog;
};
#define CCM_CCGR_SETTING0_DOM_CLK_NONE 0
#define CCM_CCGR_SETTING0_DOM_CLK_RUN BIT(0)
#define CCM_CCGR_SETTING0_DOM_CLK_RUN_WAIT BIT(1)
#define CCM_CCGR_SETTING0_DOM_CLK_ALWAYS (BIT(1) | BIT(0))
#define CCM_CCGR_SETTING1_DOM_CLK_NONE 0
#define CCM_CCGR_SETTING1_DOM_CLK_RUN BIT(4)
#define CCM_CCGR_SETTING1_DOM_CLK_RUN_WAIT BIT(5)
#define CCM_CCGR_SETTING1_DOM_CLK_ALWAYS (BIT(5) | BIT(4))
#define CCM_CCGR_SETTING2_DOM_CLK_NONE 0
#define CCM_CCGR_SETTING2_DOM_CLK_RUN BIT(8)
#define CCM_CCGR_SETTING2_DOM_CLK_RUN_WAIT BIT(9)
#define CCM_CCGR_SETTING2_DOM_CLK_ALWAYS (BIT(9) | BIT(8))
#define CCM_CCGR_SETTING3_DOM_CLK_NONE 0
#define CCM_CCGR_SETTING3_DOM_CLK_RUN BIT(12)
#define CCM_CCGR_SETTING3_DOM_CLK_RUN_WAIT BIT(13)
#define CCM_CCGR_SETTING3_DOM_CLK_ALWAYS (BIT(13) | BIT(12))
enum {
CCM_CCGR_ID_ADC = 32,
CCM_CCGR_ID_AIPS1TZ = 10,
CCM_CCGR_ID_AIPS2TZ = 11,
CCM_CCGR_ID_AIPS3TZ = 12,
CCM_CCGR_ID_APBHDMA = 20,
CCM_CCGR_ID_CAAM = 36,
CCM_CCGR_ID_CM4 = 1,
CCM_CCGR_ID_CSI = 73,
CCM_CCGR_ID_CSU = 45,
CCM_CCGR_ID_DAP = 47,
CCM_CCGR_ID_DBGMON = 46,
CCM_CCGR_ID_DDRC = 19,
CCM_CCGR_ID_ECSPI1 = 120,
CCM_CCGR_ID_ECSPI2 = 121,
CCM_CCGR_ID_ECSPI3 = 122,
CCM_CCGR_ID_ECSPI4 = 123,
CCM_CCGR_ID_EIM = 22,
CCM_CCGR_ID_ENET1 = 112,
CCM_CCGR_ID_ENET2 = 113,
CCM_CCGR_ID_EPDC = 74,
CCM_CCGR_ID_FLEXCAN1 = 116,
CCM_CCGR_ID_FLEXCAN2 = 117,
CCM_CCGR_ID_FLEXTIMER1 = 128,
CCM_CCGR_ID_FLEXTIMER2 = 129,
CCM_CCGR_ID_GPIO1 = 160,
CCM_CCGR_ID_GPIO2 = 161,
CCM_CCGR_ID_GPIO3 = 162,
CCM_CCGR_ID_GPIO4 = 163,
CCM_CCGR_ID_GPIO5 = 164,
CCM_CCGR_ID_GPIO6 = 165,
CCM_CCGR_ID_GPIO7 = 166,
CCM_CCGR_ID_GPT1 = 124,
CCM_CCGR_ID_GPT2 = 125,
CCM_CCGR_ID_GPT3 = 126,
CCM_CCGR_ID_GPT4 = 127,
CCM_CCGR_ID_I2C1 = 136,
CCM_CCGR_ID_I2C2 = 137,
CCM_CCGR_ID_I2C3 = 138,
CCM_CCGR_ID_I2C4 = 139,
CCM_CCGR_ID_IOMUXC1 = 168,
CCM_CCGR_ID_IOMUXC2 = 169,
CCM_CCGR_ID_KPP = 120,
CCM_CCGR_ID_LCDIF = 75,
CCM_CCGR_ID_MIPI_CSI = 100,
CCM_CCGR_ID_MIPI_DSI = 101,
CCM_CCGR_ID_MIPI_PHY = 102,
CCM_CCGR_ID_MU = 39,
CCM_CCGR_ID_OCOTP = 35,
CCM_CCGR_ID_OCRAM = 17,
CCM_CCGR_ID_OCRAM_S = 18,
CCM_CCGR_ID_PCIE = 96,
CCM_CCGR_ID_PCIE_PHY = 96,
CCM_CCGR_ID_PERFMON1 = 68,
CCM_CCGR_ID_PERFMON2 = 69,
CCM_CCGR_ID_PWM1 = 132,
CCM_CCGR_ID_PWM2 = 133,
CCM_CCGR_ID_PWM3 = 134,
CCM_CCGR_ID_PMM4 = 135,
CCM_CCGR_ID_PXP = 76,
CCM_CCGR_ID_QOS1 = 42,
CCM_CCGR_ID_QOS2 = 43,
CCM_CCGR_ID_QOS3 = 44,
CCM_CCGR_ID_QUADSPI = 21,
CCM_CCGR_ID_RDC = 38,
CCM_CCGR_ID_ROMCP = 16,
CCM_CCGR_ID_SAI1 = 140,
CCM_CCGR_ID_SAI2 = 141,
CCM_CCGR_ID_SAI3 = 142,
CCM_CCGR_ID_SCTR = 34,
CCM_CCGR_ID_SDMA = 72,
CCM_CCGR_ID_SEC = 49,
CCM_CCGR_ID_SEMA42_1 = 64,
CCM_CCGR_ID_SEMA42_2 = 65,
CCM_CCGR_ID_SIM_DISPLAY = 5,
CCM_CCGR_ID_SIM_ENET = 6,
CCM_CCGR_ID_SIM_M = 7,
CCM_CCGR_ID_SIM_MAIN = 4,
CCM_CCGR_ID_SIM_S = 8,
CCM_CCGR_ID_SIM_WAKEUP = 9,
CCM_CCGR_ID_SIM1 = 144,
CCM_CCGR_ID_SIM2 = 145,
CCM_CCGR_ID_SIM_NAND = 20,
CCM_CCGR_ID_DISPLAY_CM4 = 1,
CCM_CCGR_ID_DRAM = 19,
CCM_CCGR_ID_SNVS = 37,
CCM_CCGR_ID_SPBA = 12,
CCM_CCGR_ID_TRACE = 48,
CCM_CCGR_ID_TZASC = 19,
CCM_CCGR_ID_UART1 = 148,
CCM_CCGR_ID_UART2 = 149,
CCM_CCGR_ID_UART3 = 150,
CCM_CCGR_ID_UART4 = 151,
CCM_CCGR_ID_UART5 = 152,
CCM_CCGR_ID_UART6 = 153,
CCM_CCGR_ID_UART7 = 154,
CCM_CCGR_ID_USB_HS = 40,
CCM_CCGR_ID_USB_IPG = 104,
CCM_CCGR_ID_USB_PHY_480MCLK = 105,
CCM_CCGR_ID_USB_OTG1_PHY = 106,
CCM_CCGR_ID_USB_OTG2_PHY = 107,
CCM_CCGR_ID_USBHDC1 = 108,
CCM_CCGR_ID_USBHDC2 = 109,
CCM_CCGR_ID_USBHDC3 = 110,
CCM_CCGR_ID_WDOG1 = 156,
CCM_CCGR_ID_WDOG2 = 157,
CCM_CCGR_ID_WDOG3 = 158,
CCM_CCGR_ID_WDOG4 = 159,
};
/* Clock target block */
struct ccm_target_root_ctrl {
uint32_t ccm_target_root;
uint32_t ccm_target_root_set;
uint32_t ccm_target_root_clr;
uint32_t ccm_target_root_tog;
uint32_t ccm_misc;
uint32_t ccm_misc_set;
uint32_t ccm_misc_clr;
uint32_t ccm_misc_tog;
uint32_t ccm_post;
uint32_t ccm_post_set;
uint32_t ccm_post_clr;
uint32_t ccm_post_tog;
uint32_t ccm_pre;
uint32_t ccm_pre_set;
uint32_t ccm_pre_clr;
uint32_t ccm_pre_tog;
uint32_t reserved[0x0c];
uint32_t ccm_access_ctrl;
uint32_t ccm_access_ctrl_set;
uint32_t ccm_access_ctrl_clr;
uint32_t ccm_access_ctrl_tog;
};
#define CCM_TARGET_ROOT_ENABLE BIT(28)
#define CCM_TARGET_MUX(x) (((x) - 1) << 24)
#define CCM_TARGET_PRE_PODF(x) (((x) - 1) << 16)
#define CCM_TARGET_POST_PODF(x) ((x) - 1)
/* Target root MUX values - selects the clock source for a block */
/* ARM_A7_CLK_ROOT */
#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_ARM_PLL BIT(24)
#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_ENET_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_DDR_PLL (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_SYS_PLL BIT(26)
#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_SYS_PLL_PFD0 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_ARM_A7_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* ARM_M4_CLK_ROOT */
#define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_ENET_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_SYS_PLL_PFD2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_DDR_PLL_DIV2 BIT(26)
#define CCM_TRGT_MUX_ARM_M4_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_ARM_M4_CLK_ROOTV_IDEO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_ARM_M4_CLK_ROOTUSB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* MAIN_AXI_CLK_ROOT */
#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_SYS_PLL_PFD1 BIT(24)
#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_ENET_PLL_DIV4 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_SYS_PLL_PFD5 BIT(26)
#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_MAIN_AXI_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
/* DISP_AXI_CLK_ROOT */
#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_SYS_PLL_PFD1 BIT(24)
#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_ENET_PLL_DIV4 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_SYS_PLL_PFD6 BIT(26)
#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_SYS_PLL_PFD7 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_DISP_AXI_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* ENET_AXI_CLK_ROOT */
#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_SYS_PLL_PFD2 BIT(24)
#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_ENET_PLL_DIV4 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_SYS_PLL_DIV2 BIT(26)
#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_ENET_AXI_CLK_ROOT_SYS_PLL_PFD4 ((BIT(26) | BIT(25) | BIT(24))
/* NAND_USDHC_BUS_CLK_ROOT */
#define CM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB BIT(24)
#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_SYS_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(26)
#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AUDIO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* AHB_CLK_ROOT */
#define CCM_TRGT_MUX_AHB_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_AHB_CLK_ROOT_SYS_PLL_PFD2 BIT(24)
#define CCM_TRGT_MUX_AHB_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_AHB_CLK_ROOT_SYS_PLL_PFD0 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_AHB_CLK_ROOT_ENET_PLL_DIV8 BIT(26)
#define CCM_TRGT_MUX_AHB_CLK_ROOT_USB_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_AHB_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_AHB_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* IPG_CLK_ROOT */
#define CCM_TRGT_MUX_IPG_CLK_ROOT_AHB_CLK_ROOT 0
/* DRAM_PHYM_CLK_ROOT */
#define CCM_TRGT_MUX_DRAM_PHYM_CLK_ROOT_DDR_PLL 0
#define CCM_TRGT_MUX_DRAM_PHYM_CLK_ROOT_DRAM_PHYM_ALT_CLK_ROOT BIT(24)
/* DRAM_CLK_ROOT */
#define CCM_TRGT_MUX_DRAM_CLK_ROOT_DDR_PLL 0
#define CCM_TRGT_MUX_DRAM_CLK_ROOT_DRAM_ALT_CLK_ROOT BIT(24)
/* DRAM_PHYM_ALT_CLK_ROOT */
#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_DDR_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_SYS_PLL BIT(25)
#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_USB_PLL BIT(26)
#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_SYS_PLL_PFD7 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_DRAM_PHYM_ALT_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* DRAM_ALT_CLK_ROOT */
#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_DDR_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_SYS_PLL BIT(25)
#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_ENET_PLL_DIV4 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_USB_PLL BIT(26)
#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_SYS_PLL_PFD0 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_DRAM_ALT_CLK_ROOT_SYS_PLL_PFD2 ((BIT(26) | BIT(25) | BIT(24))
/* USB_HSIC_CLK_ROOT */
#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL BIT(24)
#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_USB_PLL BIT(25)
#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD3 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD4 BIT(26)
#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD5 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
/* LCDIF_PIXEL_CLK_ROOT */
#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_SYS_PLL_PFD5 BIT(24)
#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_EXT_CLK3 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_SYS_PLL_PFD4 BIT(26)
#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_LCDIF_PIXEL_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* MIPI_DSI_CLK_ROOT */
#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL_PFD5 BIT(24)
#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL_PFD3 BIT(25)
#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_SYS_PLL_PFD0_DIV2 BIT(26)
#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_DDR_PLL_DIV2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_MIPI_DSI_CLK_ROOT_AUDIO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* MIPI_CSI_CLK_ROOT */
#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL_PFD4 BIT(24)
#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL_PFD3 BIT(25)
#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_SYS_PLL_PFD0_DIV2 BIT(26)
#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_DDR_PLL_DIV2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_MIPI_CSI_CLK_ROOT_AUDIO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* MIPI_DPHY_REF_CLK_ROOT */
#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_SYS_PLL_PFD5 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_REF_1M BIT(26)
#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_MIPI_DPHY_REF_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
/* SAI1_CLK_ROOT */
#define CCM_TRGT_MUX_SAI1_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_SAI1_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
#define CCM_TRGT_MUX_SAI1_CLK_ROOT_AUDIO_PLL BIT(25)
#define CCM_TRGT_MUX_SAI1_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_SAI1_CLK_ROOT_VIDEO_PLL BIT(26)
#define CCM_TRGT_MUX_SAI1_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_SAI1_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_SAI1_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
/* SAI2_CLK_ROOT */
#define CCM_TRGT_MUX_SAI2_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_SAI2_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
#define CCM_TRGT_MUX_SAI2_CLK_ROOT_AUDIO_PLL BIT(25)
#define CCM_TRGT_MUX_SAI2_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_SAI2_CLK_ROOT_VIDEO_PLL BIT(26)
#define CCM_TRGT_MUX_SAI2_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_SAI2_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_SAI2_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
/* SAI3_CLK_ROOT */
#define CCM_TRGT_MUX_SAI3_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_SAI3_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
#define CCM_TRGT_MUX_SAI3_CLK_ROOT_AUDIO_PLL BIT(25)
#define CCM_TRGT_MUX_SAI3_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_SAI3_CLK_ROOT_VIDEO_PLL BIT(26)
#define CCM_TRGT_MUX_SAI3_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_SAI3_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_SAI3_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
/* ENET1_REF_CLK_ROOT */
#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_ENET_PLL_DIV8 BIT(24)
#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_ENET_PLL_DIV20 BIT(25)
#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_ENET_PLL_DIV40 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_SYS_PLL_DIV4 BIT(26)
#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_ENET1_REF_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24))
/* ENET1_TIME_CLK_ROOT */
#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_AUDIO_PLL BIT(25)
#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK1 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK2 BIT(26)
#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_ENET1_TIME_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* ENET_PHY_REF_CLK_ROOT */
#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_ENET_PLL_DIV40 BIT(24)
#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_ENET_PLL_DIV20 BIT(25)
#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_ENET_PLL_DIV8 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_DDR_PLL_DIV2 BIT(26)
#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_ENET_PHY_REF_CLK_ROOT_SYS_PLL_PFD3 ((BIT(26) | BIT(25) | BIT(24))
/* EIM_CLK_ROOT */
#define CCM_TRGT_MUX_EIM_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
#define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_EIM_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_PFD2 BIT(26)
#define CCM_TRGT_MUX_EIM_CLK_ROOT_SYS_PLL_PFD3 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_EIM_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_EIM_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* NAND_CLK_ROOT */
#define CCM_TRGT_MUX_NAND_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_NAND_CLK_ROOT_SYS_PLL BIT(24)
#define CCM_TRGT_MUX_NAND_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_NAND_CLK_ROOT_SYS_PLL_PFD0 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_NAND_CLK_ROOT_SYS_PLL_PFD3 BIT(26)
#define CCM_TRGT_MUX_NAND_CLK_ROOT_ENET_PLL_DIV2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_NAND_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_NAND_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* QSPI_CLK_ROOT */
#define CCM_TRGT_MUX_QSPI_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD4 BIT(24)
#define CCM_TRGT_MUX_QSPI_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_QSPI_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD3 BIT(26)
#define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_QSPI_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
/* USDHC1_CLK_ROOT */
#define CM_TRGT_MUX_USDHC1_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD0 BIT(24)
#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD4 BIT(26)
#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_USDHC1_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
/* USDHC2_CLK_ROOT */
#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD0 BIT(24)
#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD4 BIT(26)
#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_USDHC2_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
/* USDHC3_CLK_ROOT */
#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD0 BIT(24)
#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_ENET_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD4 BIT(26)
#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD6 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_USDHC3_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
/* CAN1_CLK_ROOT */
#define CCM_TRGT_MUX_CAN1_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_CAN1_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
#define CCM_TRGT_MUX_CAN1_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_CAN1_CLK_ROOT_SYS_PLL (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_CAN1_CLK_ROOT_ENET_PLL_DIV25 BIT(26)
#define CCM_TRGT_MUX_CAN1_CLK_ROOT_USB_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK1 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_CAN1_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24))
/* CAN2_CLK_ROOT */
#define CCM_TRGT_MUX_CAN2_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_CAN2_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
#define CCM_TRGT_MUX_CAN2_CLK_ROOT_DDR_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_CAN2_CLK_ROOT_SYS_PLL (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_CAN2_CLK_ROOT_ENET_PLL_DIV25 BIT(26)
#define CCM_TRGT_MUX_CAN2_CLK_ROOT_USB_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_CAN2_CLK_ROOT_EXT_CLK1 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_CAN2_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
/* I2C1_CLK_ROOT */
#define CCM_TRGT_MUX_I2C1_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_I2C1_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
#define CCM_TRGT_MUX_I2C1_CLK_ROOT_ENET_PLL_DIV20 BIT(25)
#define CCM_TRGT_MUX_I2C1_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_I2C1_CLK_ROOT_AUDIO_PLL BIT(26)
#define CCM_TRGT_MUX_I2C1_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_I2C1_CLK_ROOT_USB_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_I2C1_CLK_ROOT_SYS_PLL_PFD2_DIV2 ((BIT(26) | BIT(25) | BIT(24))
/* I2C2_CLK_ROOT */
#define CCM_TRGT_MUX_I2C2_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_I2C2_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
#define CCM_TRGT_MUX_I2C2_CLK_ROOT_ENET_PLL_DIV20 BIT(25)
#define CCM_TRGT_MUX_I2C2_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_I2C2_CLK_ROOT_AUDIO_PLL BIT(26)
#define CCM_TRGT_MUX_I2C2_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_I2C2_CLK_ROOT_USB_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_I2C2_CLK_ROOT_SYS_PLL_PFD2_DIV2 ((BIT(26) | BIT(25) | BIT(24))
/* I2C3_CLK_ROOT */
#define CCM_TRGT_MUX_I2C3_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_I2C3_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
#define CCM_TRGT_MUX_I2C3_CLK_ROOT_ENET_PLL_DIV20 BIT(25)
#define CCM_TRGT_MUX_I2C3_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_I2C3_CLK_ROOT_AUDIO_PLL BIT(26)
#define CCM_TRGT_MUX_I2C3_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_I2C3_CLK_ROOT_USB_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_I2C3_CLK_ROOT_SYS_PLL_PFD2_DIV2 ((BIT(26) | BIT(25) | BIT(24))
/* I2C4_CLK_ROOT */
#define CCM_TRGT_MUX_I2C4_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_I2C4_CLK_ROOT_SYS_PLL_DIV4 BIT(24)
#define CCM_TRGT_MUX_I2C4_CLK_ROOT_ENET_PLL_DIV20 BIT(25)
#define CCM_TRGT_MUX_I2C4_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_I2C4_CLK_ROOT_AUDIO_PLL BIT(26)
#define CCM_TRGT_MUX_I2C4_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_I2C4_CLK_ROOT_USB_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_I2C4_CLK_ROOT_SYS_PLL_PFD2_DIV2 ((BIT(26) | BIT(25) | BIT(24))
/* UART1_CLK_ROOT */
#define CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_UART1_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_UART1_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
#define CCM_TRGT_MUX_UART1_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_UART1_CLK_ROOT_SYS_PLL BIT(26)
#define CCM_TRGT_MUX_UART1_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_UART1_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_UART1_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* UART2_CLK_ROOT */
#define CCM_TRGT_MUX_UART2_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_UART2_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_UART2_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
#define CCM_TRGT_MUX_UART2_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_UART2_CLK_ROOT_SYS_PLL BIT(26)
#define CCM_TRGT_MUX_UART2_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_UART2_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_UART2_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* UART3_CLK_ROOT */
#define CCM_TRGT_MUX_UART3_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_UART3_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_UART3_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
#define CCM_TRGT_MUX_UART3_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_UART3_CLK_ROOT_SYS_PLL BIT(26)
#define CCM_TRGT_MUX_UART3_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_UART3_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_UART3_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* UART4_CLK_ROOT */
#define CCM_TRGT_MUX_UART4_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_UART4_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_UART4_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
#define CCM_TRGT_MUX_UART4_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_UART4_CLK_ROOT_SYS_PLL BIT(26)
#define CCM_TRGT_MUX_UART4_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_UART4_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_UART4_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* UART5_CLK_ROOT */
#define CCM_TRGT_MUX_UART5_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_UART5_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_UART5_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
#define CCM_TRGT_MUX_UART5_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_UART5_CLK_ROOT_SYS_PLL BIT(26)
#define CCM_TRGT_MUX_UART5_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_UART5_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_UART5_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* UART6_CLK_ROOT */
#define CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_UART6_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_UART6_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
#define CCM_TRGT_MUX_UART6_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_UART6_CLK_ROOT_SYS_PLL BIT(26)
#define CCM_TRGT_MUX_UART6_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_UART6_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_UART6_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* UART7_CLK_ROOT */
#define CCM_TRGT_MUX_UART7_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_UART7_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_UART7_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
#define CCM_TRGT_MUX_UART7_CLK_ROOT_ENET_PLL_DIV10 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_UART7_CLK_ROOT_SYS_PLL BIT(26)
#define CCM_TRGT_MUX_UART7_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_UART7_CLK_ROOT_EXT_CLK4 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_UART7_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* ECSPI1_CLK_ROOT */
#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL_DIV4 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL BIT(26)
#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_ECSPI1_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* ECSPI2_CLK_ROOT */
#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL_DIV4 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL BIT(26)
#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_ECSPI2_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* ECSPI3_CLK_ROOT */
#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL_DIV4 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL BIT(26)
#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_ECSPI3_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* ECSPI4_CLK_ROOT */
#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_ENET_PLL_DIV25 BIT(25)
#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL_DIV4 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL BIT(26)
#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_SYS_PLL_PFD4 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_ENET_PLL_DIV4 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_ECSPI4_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* PWM1_CLK_ROOT */
#define CCM_TRGT_MUX_PWM1_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_PWM1_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
#define CCM_TRGT_MUX_PWM1_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_PWM1_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_PWM1_CLK_ROOT_AUDIO_PLL BIT(26)
#define CCM_TRGT_MUX_PWM1_CLK_ROOT_EXT_CLK1 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_PWM1_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_PWM1_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* PWM2_CLK_ROOT */
#define CCM_TRGT_MUX_PWM2_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_PWM2_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
#define CCM_TRGT_MUX_PWM2_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_PWM2_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_PWM2_CLK_ROOT_AUDIO_PLL BIT(26)
#define CCM_TRGT_MUX_PWM2_CLK_ROOT_EXT_CLK1 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_PWM2_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_PWM2_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* PWM3_CLK_ROOT */
#define CCM_TRGT_MUX_PWM3_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_PWM3_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
#define CCM_TRGT_MUX_PWM3_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_PWM3_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_PWM3_CLK_ROOT_AUDIO_PLL BIT(26)
#define CCM_TRGT_MUX_PWM3_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_PWM3_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_PWM3_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* PWM4_CLK_ROOT */
#define CCM_TRGT_MUX_PWM4_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_PWM4_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
#define CCM_TRGT_MUX_PWM4_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_PWM4_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_PWM4_CLK_ROOT_AUDIO_PLL BIT(26)
#define CCM_TRGT_MUX_PWM4_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_PWM4_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_PWM4_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* FLEXTIMER1_CLK_ROOT */
#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_AUDIO_PLL BIT(26)
#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_FLEXTIMER1_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* FLEXTIMER2_CLK_ROOT */
#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_AUDIO_PLL BIT(26)
#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_EXT_CLK3 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_FLEXTIMER2_CLK_ROOT_VIDEO_PLL ((BIT(26) | BIT(25) | BIT(24))
/* Target SIM1_CLK_ROOT */
#define CCM_TRGT_MUX_SIM1_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_SIM1_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
#define CCM_TRGT_MUX_SIM1_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_SIM1_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_SIM1_CLK_ROOT_USB_PLL BIT(26)
#define CCM_TRGT_MUX_SIM1_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_SIM1_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_SIM1_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
/* Target SIM2_CLK_ROOT */
#define CCM_TRGT_MUX_SIM2_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_SIM2_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
#define CCM_TRGT_MUX_SIM2_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_SIM2_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_SIM2_CLK_ROOT_USB_PLL BIT(26)
#define CCM_TRGT_MUX_SIM2_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_SIM2_CLK_ROOT_ENET_PLL_DIV8 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_SIM2_CLK_ROOT_SYS_PLL_PFD7 ((BIT(26) | BIT(25) | BIT(24))
/* Target GPT1_CLK_ROOT */
#define CCM_TRGT_MUX_GPT1_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_GPT1_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
#define CCM_TRGT_MUX_GPT1_CLK_ROOT_SYS_PLL_PFD0 BIT(25)
#define CCM_TRGT_MUX_GPT1_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_GPT1_CLK_ROOT_VIDEO_PLL BIT(26)
#define CCM_TRGT_MUX_GPT1_CLK_ROOT_REF_1M (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_GPT1_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_GPT1_CLK_ROOT_EXT_CLK1 ((BIT(26) | BIT(25) | BIT(24))
/* Target GPT2_CLK_ROOT */
#define CCM_TRGT_MUX_GPT2_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_GPT2_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
#define CCM_TRGT_MUX_GPT2_CLK_ROOT_SYS_PLL_PFD0 BIT(25)
#define CCM_TRGT_MUX_GPT2_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_GPT2_CLK_ROOT_VIDEO_PLL BIT(26)
#define CCM_TRGT_MUX_GPT2_CLK_ROOT_REF_1M (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_GPT2_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_GPT2_CLK_ROOT_EXT_CLK2 ((BIT(26) | BIT(25) | BIT(24))
/* Target GPT3_CLK_ROOT */
#define CCM_TRGT_MUX_GPT3_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_GPT3_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
#define CCM_TRGT_MUX_GPT3_CLK_ROOT_SYS_PLL_PFD0 BIT(25)
#define CCM_TRGT_MUX_GPT3_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_GPT3_CLK_ROOT_VIDEO_PLL BIT(26)
#define CCM_TRGT_MUX_GPT3_CLK_ROOT_REF_1M (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_GPT3_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_GPT3_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
/*Target GPT4_CLK_ROOT */
#define CCM_TRGT_MUX_GPT4_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_GPT4_CLK_ROOT_ENET_PLL_DIV10 BIT(24)
#define CCM_TRGT_MUX_GPT4_CLK_ROOT_SYS_PLL_PFD0 BIT(25)
#define CCM_TRGT_MUX_GPT4_CLK_ROOT_ENET_PLL_DIV25 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_GPT4_CLK_ROOT_VIDEO_PLL BIT(26)
#define CCM_TRGT_MUX_GPT4_CLK_ROOT_REF_1M (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_GPT4_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_GPT4_CLK_ROOT_EXT_CLK4 ((BIT(26) | BIT(25) | BIT(24))
/* Target TRACE_CLK_ROOT */
#define CCM_TRGT_MUX_TRACE_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_TRACE_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
#define CCM_TRGT_MUX_TRACE_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_TRACE_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_TRACE_CLK_ROOT_ENET_PLL_DIV8 BIT(26)
#define CCM_TRGT_MUX_TRACE_CLK_ROOT_USB_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_TRACE_CLK_ROOT_EXT_CLK2 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_TRACE_CLK_ROOT_EXT_CLK3 ((BIT(26) | BIT(25) | BIT(24))
/* Target WDOG_CLK_ROOT */
#define CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
#define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_WDOG_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_WDOG_CLK_ROOT_ENET_PLL_DIV8 BIT(26)
#define CCM_TRGT_MUX_WDOG_CLK_ROOT_USB_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_WDOG_CLK_ROOT_REF_1M (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_WDOG_CLK_ROOT_SYS_PLL_PFD1_DIV2 ((BIT(26) | BIT(25) | BIT(24))
/* Target CSI_MCLK_CLK_ROOT */
#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_ENET_PLL_DIV8 BIT(26)
#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_CSI_MCLK_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* Target AUDIO_MCLK_CLK_ROOT */
#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_OSC_24M 0
#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_SYS_PLL_PFD2_DIV2 BIT(24)
#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_SYS_PLL_DIV4 BIT(25)
#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_DDR_PLL_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_ENET_PLL_DIV8 BIT(26)
#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_AUDIO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_VIDEO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_AUDIO_MCLK_CLK_ROOT_USB_PLL ((BIT(26) | BIT(25) | BIT(24))
/* Target CCM_CLKO1 */
#define CCM_TRGT_MUX_CCM_CLKO1_OSC_24M 0
#define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL BIT(24)
#define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL_DIV2 BIT(25)
#define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL_PFD0_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_CCM_CLKO1_SYS_PLL_PFD3 BIT(26)
#define CCM_TRGT_MUX_CCM_CLKO1_ENET_PLL_DIV2 (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_CCM_CLKO1_DDR_PLL_DIV2 (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_CCM_CLKO1_REF_1M ((BIT(26) | BIT(25) | BIT(24))
/* Target CCM_CLKO2 */
#define CCM_TRGT_MUX_CCM_CLKO2_OSC_24M 0
#define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_DIV2 BIT(24)
#define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_PFD0 BIT(25)
#define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_PFD1_DIV2 (BIT(25) | BIT(24))
#define CCM_TRGT_MUX_CCM_CLKO2_SYS_PLL_PFD4 BIT(26)
#define CCM_TRGT_MUX_CCM_CLKO2_AUDIO_PLL (BIT(26) | BIT(24))
#define CCM_TRGT_MUX_CCM_CLKO2_VIDEO_PLL (BIT(26) | BIT(25))
#define CCM_TRGT_MUX_CCM_CLKO2_OSC_32K ((BIT(26) | BIT(25) | BIT(24))
/*
* See Table 5-11 in i.MX7 Solo Reference manual rev 0.1
* The indices must be calculated by dividing the offset by
* sizeof (struct ccm_target_root_ctrl) => 0x80 bytes for each index
*/
enum {
CCM_TRT_ID_ARM_A7_CLK_ROOT = 0,
CCM_TRT_ID_ARM_M4_CLK_ROOT = 1,
CCM_TRT_ID_MAIN_AXI_CLK_ROOT = 16,
CCM_TRT_ID_DISP_AXI_CLK_ROOT = 17,
CCM_TRT_ID_ENET_AXI_CLK_ROOT = 18,
CCM_TRT_ID_NAND_USDHC_BUS_CLK_ROOT = 19,
CCM_TRT_ID_AHB_CLK_ROOT = 32,
CCM_TRT_ID_IPG_CLK_ROOT = 33,
CCM_TRT_ID_DRAM_PHYM_CLK_ROOT = 48,
CCM_TRT_ID_DRAM_CLK_ROOT = 49,
CCM_TRT_ID_DRAM_PHYM_ALT_CLK_ROOT = 64,
CCM_TRT_ID_DRAM_ALT_CLK_ROOT = 65,
CCM_TRT_ID_USB_HSIC_CLK_ROOT = 66,
CCM_TRT_ID_LCDIF_PIXEL_CLK_ROOT = 70,
CCM_TRT_ID_MIPI_DSI_CLK_ROOT = 71,
CCM_TRT_ID_MIPI_CSI_CLK_ROOT = 72,
CCM_TRT_ID_MIPI_DPHY_REF_CLK_ROOT = 73,
CCM_TRT_ID_SAI1_CLK_ROOT = 74,
CCM_TRT_ID_SAI2_CLK_ROOT = 75,
CCM_TRT_ID_SAI3_CLK_ROOT = 76,
CCM_TRT_ID_ENET1_REF_CLK_ROOT = 78,
CCM_TRT_ID_ENET1_TIME_CLK_ROOT = 79,
CCM_TRT_ID_ENET_PHY_REF_CLK_ROOT = 82,
CCM_TRT_ID_EIM_CLK_ROOT = 83,
CCM_TRT_ID_NAND_CLK_ROOT = 84,
CCM_TRT_ID_QSPI_CLK_ROOT = 85,
CCM_TRT_ID_USDHC1_CLK_ROOT = 86,
CCM_TRT_ID_USDHC2_CLK_ROOT = 87,
CCM_TRT_ID_USDHC3_CLK_ROOT = 88,
CCM_TRT_ID_CAN1_CLK_ROOT = 89,
CCM_TRT_ID_CAN2_CLK_ROOT = 90,
CCM_TRT_ID_I2C1_CLK_ROOT = 91,
CCM_TRT_ID_I2C2_CLK_ROOT = 92,
CCM_TRT_ID_I2C3_CLK_ROOT = 93,
CCM_TRT_ID_I2C4_CLK_ROOT = 94,
CCM_TRT_ID_UART1_CLK_ROOT = 95,
CCM_TRT_ID_UART2_CLK_ROOT = 96,
CCM_TRT_ID_UART3_CLK_ROOT = 97,
CCM_TRT_ID_UART4_CLK_ROOT = 98,
CCM_TRT_ID_UART5_CLK_ROOT = 99,
CCM_TRT_ID_UART6_CLK_ROOT = 100,
CCM_TRT_ID_UART7_CLK_ROOT = 101,
CCM_TRT_ID_ECSPI1_CLK_ROOT = 102,
CCM_TRT_ID_ECSPI2_CLK_ROOT = 103,
CCM_TRT_ID_ECSPI3_CLK_ROOT = 104,
CCM_TRT_ID_ECSPI4_CLK_ROOT = 105,
CCM_TRT_ID_PWM1_CLK_ROOT = 106,
CCM_TRT_ID_PWM2_CLK_ROOT = 107,
CCM_TRT_ID_PWM3_CLK_ROOT = 108,
CCM_TRT_ID_PWM4_CLK_ROOT = 109,
CCM_TRT_ID_FLEXTIMER1_CLK_ROOT = 110,
CCM_TRT_ID_FLEXTIMER2_CLK_ROOT = 111,
CCM_TRT_ID_SIM1_CLK_ROOT = 112,
CCM_TRT_ID_SIM2_CLK_ROOT = 113,
CCM_TRT_ID_GPT1_CLK_ROOT = 114,
CCM_TRT_ID_GPT2_CLK_ROOT = 115,
CCM_TRT_ID_GPT3_CLK_ROOT = 116,
CCM_TRT_ID_GPT4_CLK_ROOT = 117,
CCM_TRT_ID_TRACE_CLK_ROOT = 118,
CCM_TRT_ID_WDOG_CLK_ROOT = 119,
CCM_TRT_ID_CSI_MCLK_CLK_ROOT = 120,
CCM_TRT_ID_AUDIO_MCLK_CLK_ROOT = 121,
CCM_TRT_ID_CCM_CLKO1 = 123,
CCM_TRT_ID_CCM_CLKO2 = 124,
};
#define CCM_MISC_VIOLATE BIT(8)
#define CCM_MISC_TIMEOUT BIT(4)
#define CCM_MISC_AUTHEN_FAIL BIT(0)
#define CCM_POST_BUSY2 BIT(31)
#define CCM_POST_SELECT_BRANCH_A BIT(28)
#define CCM_POST_BUSY1 BIT(7)
#define CCM_POST_POST_PODF(x) ((x) - 1)
#define CCM_PRE_BUSY4 BIT(31)
#define CCM_PRE_ENABLE_A BIT(28)
#define CCM_PRE_MUX_A(x) (((x) - 1) << 24)
#define CCM_PRE_BUSY3 BIT(19)
#define CCM_PRE_PODF_A(x) (((x) - 1) << 16)
#define CCM_PRE_BUSY1 BIT(15)
#define CCM_PRE_ENABLE_B BIT(12)
#define CCM_PRE_MUX_B(x) (((x) - 1) << 8)
#define CCM_PRE_BUSY0 BIT(3)
#define CCM_PRE_POST_PODF(x) ((x) - 1)
#define CCM_ACCESS_CTRL_LOCK BIT(31)
#define CCM_ACCESS_SEMA_ENABLE BIT(28)
#define CCM_ACCESS_DOM3_WHITELIST BIT(27)
#define CCM_ACCESS_DOM2_WHITELIST BIT(26)
#define CCM_ACCESS_DOM1_WHITELIST BIT(25)
#define CCM_ACCESS_DOM0_WHITELIST BIT(24)
#define CCM_ACCESS_MUTEX BIT(20)
#define CCM_ACCESS_OWNER_ID(x) ((x) << 16)
#define CCM_ACCESS_DOM3_INFO(x) ((x) << 12)
#define CCM_ACCESS_DOM2_INFO(x) ((x) << 8)
#define CCM_ACCESS_DOM1_INFO(x) ((x) << 4)
#define CCM_ACCESS_DOM0_INFO(x) (x)
#define CCM_PLL_CTRL_NUM 0x21
#define CCM_CLK_GATE_CTRL_NUM 0xbf
#define CCM_ROOT_CTRL_NUM 0x79
struct ccm {
uint32_t ccm_gpr0;
uint32_t ccm_gpr0_set;
uint32_t ccm_gpr0_clr;
uint32_t ccm_grp0_tog;
uint32_t reserved[0x1fc];
struct ccm_pll_ctrl ccm_pll_ctrl[CCM_PLL_CTRL_NUM];
uint32_t reserved1[0xd7c];
struct ccm_clk_gate_ctrl ccm_clk_gate_ctrl[CCM_CLK_GATE_CTRL_NUM];
uint32_t reserved2[0xd04];
struct ccm_target_root_ctrl ccm_root_ctrl[CCM_ROOT_CTRL_NUM];
};
void imx_clock_target_set(unsigned int id, uint32_t val);
void imx_clock_target_clr(unsigned int id, uint32_t val);
void imx_clock_gate_enable(unsigned int id, bool enable);
void imx_clock_init(void);
void imx_clock_enable_uart(unsigned int uart_id, uint32_t uart_clk_en_bits);
void imx_clock_disable_uart(unsigned int uart_id);
void imx_clock_enable_usdhc(unsigned int usdhc_id, uint32_t usdhc_clk_en_bits);
void imx_clock_set_wdog_clk_root_bits(uint32_t wdog_clk_root_en_bits);
void imx_clock_enable_wdog(unsigned int wdog_id);
void imx_clock_disable_wdog(unsigned int wdog_id);
void imx_clock_enable_usb(unsigned int usb_id);
void imx_clock_disable_usb(unsigned int usb_id);
void imx_clock_set_usb_clk_root_bits(uint32_t usb_clk_root_en_bits);
#endif /* __IMX_CLOCK_H__ */
plat/imx/common/include/imx_csu.h 0 → 100644
View file @ 36044baf
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __IMX_CSU_H__
#define __IMX_CSU_H__
#include <arch.h>
/*
* Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors,
* Rev. 0, 03/2017 Section 3.3.1
*
* Config secure level register (CSU_CSLn)
*/
#define CSU_CSL_LOCK_S1 BIT(24)
#define CSU_CSL_NSW_S1 BIT(23)
#define CSU_CSL_NUW_S1 BIT(22)
#define CSU_CSL_SSW_S1 BIT(21)
#define CSU_CSL_SUW_S1 BIT(20)
#define CSU_CSL_NSR_S1 BIT(19)
#define CSU_CSL_NUR_S1 BIT(18)
#define CSU_CSL_SSR_S1 BIT(17)
#define CSU_CSL_SUR_S1 BIT(16)
#define CSU_CSL_LOCK_S2 BIT(8)
#define CSU_CSL_NSW_S2 BIT(7)
#define CSU_CSL_NUW_S2 BIT(6)
#define CSU_CSL_SSW_S2 BIT(5)
#define CSU_CSL_SUW_S2 BIT(4)
#define CSU_CSL_NSR_S2 BIT(3)
#define CSU_CSL_NUR_S2 BIT(2)
#define CSU_CSL_SSR_S2 BIT(1)
#define CSU_CSL_SUR_S2 BIT(0)
#define CSU_CSL_OPEN_ACCESS (CSU_CSL_NSW_S1 | CSU_CSL_NUW_S1 | CSU_CSL_SSW_S1 |\
CSU_CSL_SUW_S1 | CSU_CSL_NSR_S1 | CSU_CSL_NUR_S1 |\
CSU_CSL_SSR_S1 | CSU_CSL_SUR_S1 | CSU_CSL_NSW_S2 |\
CSU_CSL_NUW_S2 | CSU_CSL_SSW_S2 | CSU_CSL_SUW_S2 |\
CSU_CSL_NSR_S2 | CSU_CSL_NUR_S2 | CSU_CSL_SSR_S2 |\
CSU_CSL_SUR_S2)
void imx_csu_init(void);
#endif /* __IMX_CSU_H__ */
plat/imx/common/include/imx_hab.h 0 → 100644
View file @ 36044baf
/*
* Copyright (C) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __IMX_HAB_H__
#define __IMX_HAB_H__
#include <imx_hab_arch.h>
#include <imx_regs.h>
#define HAB_ROM_VECTOR_BASE\
(BOOTROM_BASE + HAB_CALLBACK_OFFSET)
/*
* Section 4.5 of the High Assurance Boot Version 4 Application Programming
* Interface Reference Manual defines the ROM Vector table as coming after a 4
* byte header
*
* A series of function pointers are enumerated at fixed addresses, which are
* described below
*/
#define HAB_ROM_VECTOR_TABLE_ENTRY (HAB_ROM_VECTOR_BASE + 0x04)
#define HAB_ROM_VECTOR_TABLE_EXIT (HAB_ROM_VECTOR_BASE + 0x08)
#define HAB_ROM_VECTOR_TABLE_CHECK_TARGET (HAB_ROM_VECTOR_BASE + 0x0C)
#define HAB_ROM_VECTOR_TABLE_AUTHENTICATE_IMAGE (HAB_ROM_VECTOR_BASE + 0x10)
#define HAB_ROM_VECTOR_TABLE_RUN_DCD (HAB_ROM_VECTOR_BASE + 0x14)
#define HAB_ROM_VECTOR_TABLE_RUN_CSF (HAB_ROM_VECTOR_BASE + 0x18)
#define HAB_ROM_VECTOR_TABLE_ASSERT (HAB_ROM_VECTOR_BASE + 0x1C)
#define HAB_ROM_VECTOR_TABLE_REPORT_EVENT (HAB_ROM_VECTOR_BASE + 0x20)
#define HAB_ROM_VECTOR_TABLE_REPORT_STATUS (HAB_ROM_VECTOR_BASE + 0x24)
#define HAB_ROM_VECTOR_TABLE_FAILSAFE (HAB_ROM_VECTOR_BASE + 0x28)
#endif /* __IMX_HAB_H__ */
plat/imx/common/include/imx_io_mux.h 0 → 100644
View file @ 36044baf
/*
* Copyright 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __IMX_IO_MUX_H__
#define __IMX_IO_MUX_H__
#include <stdint.h>
/*
* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
* Section 8.2.7 IOMUXC Memory Map/Register Definition
*/
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO08_OFFSET 0x0014
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO09_OFFSET 0x0018
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO10_OFFSET 0x001C
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO11_OFFSET 0x0020
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO12_OFFSET 0x0024
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO13_OFFSET 0x0028
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO14_OFFSET 0x002C
#define IOMUXC_SW_MUX_CTL_PAD_GPIO1_IO15_OFFSET 0x0030
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA00_OFFSET 0x0034
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA01_OFFSET 0x0038
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA02_OFFSET 0x003C
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA03_OFFSET 0x0040
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA04_OFFSET 0x0044
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA05_OFFSET 0x0048
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA06_OFFSET 0x004C
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA07_OFFSET 0x0050
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA08_OFFSET 0x0054
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA09_OFFSET 0x0058
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA10_OFFSET 0x005C
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA11_OFFSET 0x0060
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA12_OFFSET 0x0064
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA13_OFFSET 0x0068
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA14_OFFSET 0x006C
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_DATA15_OFFSET 0x0070
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCLK_OFFSET 0x0074
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDLE_OFFSET 0x0078
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDOE_OFFSET 0x007C
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDSHR_OFFSET 0x0080
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE0_OFFSET 0x0084
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE1_OFFSET 0x0088
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE2_OFFSET 0x008C
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_SDCE3_OFFSET 0x0090
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDCLK_OFFSET 0x0094
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDOE_OFFSET 0x0098
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDRL_OFFSET 0x009C
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_GDSP_OFFSET 0x00A0
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR0_OFFSET 0x00A4
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_BDR1_OFFSET 0x00A8
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_COM_OFFSET 0x00AC
#define IOMUXC_SW_MUX_CTL_PAD_EPDC_PWR_STAT_OFFSET 0x00B0
#define IOMUXC_SW_MUX_CTL_PAD_LCD_CLK_OFFSET 0x00B4
#define IOMUXC_SW_MUX_CTL_PAD_LCD_ENABLE_OFFSET 0x00B8
#define IOMUXC_SW_MUX_CTL_PAD_LCD_HSYNC_OFFSET 0x00BC
#define IOMUXC_SW_MUX_CTL_PAD_LCD_VSYNC_OFFSET 0x00C0
#define IOMUXC_SW_MUX_CTL_PAD_LCD_RESET_OFFSET 0x00C4
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA00_OFFSET 0x00C8
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA01_OFFSET 0x00CC
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA02_OFFSET 0x00D0
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA03_OFFSET 0x00D4
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA04_OFFSET 0x00D8
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA05_OFFSET 0x00DC
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA06_OFFSET 0x00E0
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA07_OFFSET 0x00E4
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA08_OFFSET 0x00E8
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA09_OFFSET 0x00EC
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA10_OFFSET 0x00F0
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA11_OFFSET 0x00F4
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA12_OFFSET 0x00F8
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA13_OFFSET 0x00FC
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA14_OFFSET 0x0100
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA15_OFFSET 0x0104
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA16_OFFSET 0x0108
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA17_OFFSET 0x010C
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA18_OFFSET 0x0110
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA19_OFFSET 0x0114
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA20_OFFSET 0x0118
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA21_OFFSET 0x011C
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA22_OFFSET 0x0120
#define IOMUXC_SW_MUX_CTL_PAD_LCD_DATA23_OFFSET 0x0124
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET 0x0128
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA 0x00
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT1_I2C1_SCL BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT2_PMIC_READY BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT3_ECSPI1_SS1 (BIT(1) | BIT(0))
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT4_ENET2_1588_EVENT0_IN BIT(3)
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT5_GPIO4_IO0 (BIT(2) | BIT(0))
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT6_ENET1_MDIO (BIT(2) | BIT(1))
#define IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_SION BIT(3)
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET 0x012C
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA 0x00
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT1_I2C1_SDA BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT2_SAI3_MCLK BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT3_ECSPI1_SS2 (BIT(1) | BIT(0))
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT4_ENET2_1588_EVENT0_OUT BIT(3)
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT5_GPIO4_IO1 (BIT(2) | BIT(0))
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT6_ENET1_MDC (BIT(2) | BIT(1))
#define IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_SION BIT(3)
#define IOMUXC_SW_MUX_CTL_PAD_UART2_RX_DATA_OFFSET 0x0130
#define IOMUXC_SW_MUX_CTL_PAD_UART2_TX_DATA_OFFSET 0x0134
#define IOMUXC_SW_MUX_CTL_PAD_UART3_RX_DATA_OFFSET 0x0138
#define IOMUXC_SW_MUX_CTL_PAD_UART3_TX_DATA_OFFSET 0x013C
#define IOMUXC_SW_MUX_CTL_PAD_UART3_RTS_B_OFFSET 0x0140
#define IOMUXC_SW_MUX_CTL_PAD_UART3_CTS_B_OFFSET 0x0144
#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_OFFSET 0x0148
#define IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_OFFSET 0x014C
#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_OFFSET 0x0150
#define IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_OFFSET 0x0154
#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_OFFSET 0x0158
#define IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_OFFSET 0x015C
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SCL_OFFSET 0x0160
#define IOMUXC_SW_MUX_CTL_PAD_I2C4_SDA_OFFSET 0x0164
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET 0x0168
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT0_ECSPI1_SCLK 0x00
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT2_SD2_DATA4 BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT3_CSI_DATA2 (BIT(1) | BIT(0))
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT5_GPIO4_IO16 (BIT(2) | BIT(0))
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT6_EPDC_PWR_COM (BIT(2) | (BIT(1))
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET 0x016C
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT0_ECSPI1_MOSI 0x00
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA BIT(0)
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT2_SD2_DATA5 BIT(1)
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT3_CSI_DATA3 (BIT(1) | BIT(0))
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT5_GPIO4_IO17 (BIT(2) | BIT(0))
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT6_EPDC_PWR_STAT (BIT(2) | (BIT(1))
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MISO_OFFSET 0x0170
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SS0_OFFSET 0x0174
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SCLK_OFFSET 0x0178
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MOSI_OFFSET 0x017C
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_MISO_OFFSET 0x0180
#define IOMUXC_SW_MUX_CTL_PAD_ECSPI2_SS0_OFFSET 0x0184
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CD_B_OFFSET 0x0188
#define IOMUXC_SW_MUX_CTL_PAD_SD1_WP_OFFSET 0x018C
#define IOMUXC_SW_MUX_CTL_PAD_SD1_RESET_B_OFFSET 0x0190
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CLK_OFFSET 0x0194
#define IOMUXC_SW_MUX_CTL_PAD_SD1_CMD_OFFSET 0x0198
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA0_OFFSET 0x019C
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA1_OFFSET 0x01A0
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA2_OFFSET 0x01A4
#define IOMUXC_SW_MUX_CTL_PAD_SD1_DATA3_OFFSET 0x01A8
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CD_B_OFFSET 0x01AC
#define IOMUXC_SW_MUX_CTL_PAD_SD2_WP_OFFSET 0x01B0
#define IOMUXC_SW_MUX_CTL_PAD_SD2_RESET_B_OFFSET 0x01B4
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CLK_OFFSET 0x01B8
#define IOMUXC_SW_MUX_CTL_PAD_SD2_CMD_OFFSET 0x01BC
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA0_OFFSET 0x01C0
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA1_OFFSET 0x01C4
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA2_OFFSET 0x01C8
#define IOMUXC_SW_MUX_CTL_PAD_SD2_DATA3_OFFSET 0x01CC
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CLK_OFFSET 0x01D0
#define IOMUXC_SW_MUX_CTL_PAD_SD3_CMD_OFFSET 0x01D4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA0_OFFSET 0x01D8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA1_OFFSET 0x01DC
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA2_OFFSET 0x01E0
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA3_OFFSET 0x01E4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA4_OFFSET 0x01E8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA5_OFFSET 0x01EC
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA6_OFFSET 0x01F0
#define IOMUXC_SW_MUX_CTL_PAD_SD3_DATA7_OFFSET 0x01F4
#define IOMUXC_SW_MUX_CTL_PAD_SD3_STROBE_OFFSET 0x01F8
#define IOMUXC_SW_MUX_CTL_PAD_SD3_RESET_B_OFFSET 0x01FC
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_DATA_OFFSET 0x0200
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_BCLK_OFFSET 0x0204
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_SYNC_OFFSET 0x0208
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_TX_DATA_OFFSET 0x020C
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_SYNC_OFFSET 0x0210
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_RX_BCLK_OFFSET 0x0214
#define IOMUXC_SW_MUX_CTL_PAD_SAI1_MCLK_OFFSET 0x0218
#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_SYNC_OFFSET 0x021C
#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_BCLK_OFFSET 0x0220
#define IOMUXC_SW_MUX_CTL_PAD_SAI2_RX_DATA_OFFSET 0x0224
#define IOMUXC_SW_MUX_CTL_PAD_SAI2_TX_DATA_OFFSET 0x0228
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD0_OFFSET 0x022C
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD1_OFFSET 0x0230
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD2_OFFSET 0x0234
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RD3_OFFSET 0x0238
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RX_CTL_OFFSET 0x023C
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_RXC_OFFSET 0x0240
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD0_OFFSET 0x0244
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD1_OFFSET 0x0248
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_OFFSET 0x024C
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_OFFSET 0x0250
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TX_CTL_OFFSET 0x0254
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TXC_OFFSET 0x0258
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_TX_CLK_OFFSET 0x025C
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_RX_CLK_OFFSET 0x0260
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_CRS_OFFSET 0x0264
#define IOMUXC_SW_MUX_CTL_PAD_ENET1_COL_OFFSET 0x0268
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO08_OFFSET 0x026C
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO09_OFFSET 0x0270
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO10_OFFSET 0x0274
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO11_OFFSET 0x0278
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO12_OFFSET 0x027C
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO13_OFFSET 0x0280
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO14_OFFSET 0x0284
#define IOMUXC_SW_PAD_CTL_PAD_GPIO1_IO15_OFFSET 0x0288
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_MOD_OFFSET 0x028C
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TCK_OFFSET 0x0290
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDI_OFFSET 0x0294
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TDO_OFFSET 0x0298
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TMS_OFFSET 0x029C
#define IOMUXC_SW_PAD_CTL_PAD_JTAG_TRST_B_OFFSET 0x02A0
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA00_OFFSET 0x02A4
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA01_OFFSET 0x02A8
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA02_OFFSET 0x02AC
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA03_OFFSET 0x02B0
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA04_OFFSET 0x02B4
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA05_OFFSET 0x02B8
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA06_OFFSET 0x02BC
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA07_OFFSET 0x02C0
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA08_OFFSET 0x02C4
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA09_OFFSET 0x02C8
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA10_OFFSET 0x02CC
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA11_OFFSET 0x02D0
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA12_OFFSET 0x02D4
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA13_OFFSET 0x02D8
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA14_OFFSET 0x02DC
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_DATA15_OFFSET 0x02E0
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCLK_OFFSET 0x02E4
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDLE_OFFSET 0x02E8
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDOE_OFFSET 0x02EC
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDSHR_OFFSET 0x02F0
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE0_OFFSET 0x02F4
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE1_OFFSET 0x02F8
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE2_OFFSET 0x02FC
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_SDCE3_OFFSET 0x0300
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDCLK_OFFSET 0x0304
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDOE_OFFSET 0x0308
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDRL_OFFSET 0x030C
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_GDSP_OFFSET 0x0310
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR0_OFFSET 0x0314
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_BDR1_OFFSET 0x0318
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_COM_OFFSET 0x031C
#define IOMUXC_SW_PAD_CTL_PAD_EPDC_PWR_STAT_OFFSET 0x0320
#define IOMUXC_SW_PAD_CTL_PAD_LCD_CLK_OFFSET 0x0324
#define IOMUXC_SW_PAD_CTL_PAD_LCD_ENABLE_OFFSET 0x0328
#define IOMUXC_SW_PAD_CTL_PAD_LCD_HSYNC_OFFSET 0x032C
#define IOMUXC_SW_PAD_CTL_PAD_LCD_VSYNC_OFFSET 0x0330
#define IOMUXC_SW_PAD_CTL_PAD_LCD_RESET_OFFSET 0x0334
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA00_OFFSET 0x0338
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA01_OFFSET 0x033C
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA02_OFFSET 0x0340
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA03_OFFSET 0x0344
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA04_OFFSET 0x0348
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA05_OFFSET 0x034C
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA06_OFFSET 0x0350
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA07_OFFSET 0x0354
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA08_OFFSET 0x0358
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA09_OFFSET 0x035C
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA10_OFFSET 0x0360
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA11_OFFSET 0x0364
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA12_OFFSET 0x0368
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA13_OFFSET 0x036C
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA14_OFFSET 0x0370
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA15_OFFSET 0x0374
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA16_OFFSET 0x0378
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA17_OFFSET 0x037C
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA18_OFFSET 0x0380
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA19_OFFSET 0x0384
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA20_OFFSET 0x0388
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA21_OFFSET 0x038C
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA22_OFFSET 0x0390
#define IOMUXC_SW_PAD_CTL_PAD_LCD_DATA23_OFFSET 0x0394
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET 0x0398
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_0_X1 0
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4 BIT(0)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_2_X2 BIT(1)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_3_X6 (BIT(1) | BIT(0))
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_FAST 0
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_SRE_SLOW BIT(2)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_DIS 0
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN BIT(3)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_DIS 0
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN BIT(4)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_0_100K_PD 0
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_1_5K_PU BIT(5)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_2_47K_PU BIT(6)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU (BIT(6) | BIT(5))
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET 0x039C
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_0_X1 0
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4 BIT(0)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_2_X2 BIT(1)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_3_X6 (BIT(1) | BIT(0))
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_FAST 0
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_SRE_SLOW BIT(2)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_DIS 0
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN BIT(3)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_DIS 0
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN BIT(4)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_0_100K_PD 0
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_1_5K_PU BIT(5)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_2_47K_PU BIT(6)
#define IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU (BIT(6) | BIT(5))
#define IOMUXC_SW_PAD_CTL_PAD_UART2_RX_DATA_OFFSET 0x03A0
#define IOMUXC_SW_PAD_CTL_PAD_UART2_TX_DATA_OFFSET 0x03A4
#define IOMUXC_SW_PAD_CTL_PAD_UART3_RX_DATA_OFFSET 0x03A8
#define IOMUXC_SW_PAD_CTL_PAD_UART3_TX_DATA_OFFSET 0x03AC
#define IOMUXC_SW_PAD_CTL_PAD_UART3_RTS_B_OFFSET 0x03B0
#define IOMUXC_SW_PAD_CTL_PAD_UART3_CTS_B_OFFSET 0x03B4
#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_OFFSET 0x03B8
#define IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_OFFSET 0x03BC
#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_OFFSET 0x03C0
#define IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_OFFSET 0x03C4
#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_OFFSET 0x03C8
#define IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_OFFSET 0x03CC
#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SCL_OFFSET 0x03D0
#define IOMUXC_SW_PAD_CTL_PAD_I2C4_SDA_OFFSET 0x03D4
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET 0x03D8
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_0_X1 0
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4 BIT(0)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_2_X2 BIT(1)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_3_X6 (BIT(1) | BIT(0))
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_FAST 0
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_SRE_SLOW BIT(2)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_DIS 0
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN BIT(3)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_DIS 0
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN BIT(4)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_0_100K_PD 0
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_1_5K_PU BIT(5)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_2_47K_PU BIT(6)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU (BIT(6) | BIT(5))
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET 0x03DC
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_0_X1 0
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4 BIT(0)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_2_X2 BIT(1)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_3_X6 (BIT(1) | BIT(0))
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_FAST 0
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_SRE_SLOW BIT(2)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_DIS 0
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN BIT(3)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_DIS 0
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN BIT(4)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_0_100K_PD 0
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_1_5K_PU BIT(5)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_2_47K_PU BIT(6)
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU (BIT(6) | BIT(5))
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MISO_OFFSET 0x03E0
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SS0_OFFSET 0x03E4
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SCLK_OFFSET 0x03E8
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MOSI_OFFSET 0x03EC
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_MISO_OFFSET 0x03F0
#define IOMUXC_SW_PAD_CTL_PAD_ECSPI2_SS0_OFFSET 0x03F4
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CD_B_OFFSET 0x03F8
#define IOMUXC_SW_PAD_CTL_PAD_SD1_WP_OFFSET 0x03FC
#define IOMUXC_SW_PAD_CTL_PAD_SD1_RESET_B_OFFSET 0x0400
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CLK_OFFSET 0x0404
#define IOMUXC_SW_PAD_CTL_PAD_SD1_CMD_OFFSET 0x0408
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA0_OFFSET 0x040C
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA1_OFFSET 0x0410
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA2_OFFSET 0x0414
#define IOMUXC_SW_PAD_CTL_PAD_SD1_DATA3_OFFSET 0x0418
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CD_B_OFFSET 0x041C
#define IOMUXC_SW_PAD_CTL_PAD_SD2_WP_OFFSET 0x0420
#define IOMUXC_SW_PAD_CTL_PAD_SD2_RESET_B_OFFSET 0x0424
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CLK_OFFSET 0x0428
#define IOMUXC_SW_PAD_CTL_PAD_SD2_CMD_OFFSET 0x042C
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA0_OFFSET 0x0430
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA1_OFFSET 0x0434
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA2_OFFSET 0x0438
#define IOMUXC_SW_PAD_CTL_PAD_SD2_DATA3_OFFSET 0x043C
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CLK_OFFSET 0x0440
#define IOMUXC_SW_PAD_CTL_PAD_SD3_CMD_OFFSET 0x0444
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA0_OFFSET 0x0448
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA1_OFFSET 0x044C
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA2_OFFSET 0x0450
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA3_OFFSET 0x0454
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA4_OFFSET 0x0458
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA5_OFFSET 0x045C
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA6_OFFSET 0x0460
#define IOMUXC_SW_PAD_CTL_PAD_SD3_DATA7_OFFSET 0x0464
#define IOMUXC_SW_PAD_CTL_PAD_SD3_STROBE_OFFSET 0x0468
#define IOMUXC_SW_PAD_CTL_PAD_SD3_RESET_B_OFFSET 0x046C
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_DATA_OFFSET 0x0470
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_BCLK_OFFSET 0x0474
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_SYNC_OFFSET 0x0478
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_TX_DATA_OFFSET 0x047C
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_SYNC_OFFSET 0x0480
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_RX_BCLK_OFFSET 0x0484
#define IOMUXC_SW_PAD_CTL_PAD_SAI1_MCLK_OFFSET 0x0488
#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_SYNC_OFFSET 0x048C
#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_BCLK_OFFSET 0x0490
#define IOMUXC_SW_PAD_CTL_PAD_SAI2_RX_DATA_OFFSET 0x0494
#define IOMUXC_SW_PAD_CTL_PAD_SAI2_TX_DATA_OFFSET 0x0498
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD0_OFFSET 0x049C
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD1_OFFSET 0x04A0
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD2_OFFSET 0x04A4
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RD3_OFFSET 0x04A8
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RX_CTL_OFFSET 0x04AC
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_RXC_OFFSET 0x04B0
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD0_OFFSET 0x04B4
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD1_OFFSET 0x04B8
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_OFFSET 0x04BC
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_OFFSET 0x04C0
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TX_CTL_OFFSET 0x04C4
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TXC_OFFSET 0x04C8
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_TX_CLK_OFFSET 0x04CC
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_RX_CLK_OFFSET 0x04D0
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_CRS_OFFSET 0x04D4
#define IOMUXC_SW_PAD_CTL_PAD_ENET1_COL_OFFSET 0x04D8
#define IOMUXC_FLEXCAN1_RX_SELECT_INPUT_OFFSET 0x04DC
#define IOMUXC_FLEXCAN2_RX_SELECT_INPUT_OFFSET 0x04E0
#define IOMUXC_CCM_EXT_CLK_1_SELECT_INPUT_OFFSET 0x04E4
#define IOMUXC_CCM_EXT_CLK_2_SELECT_INPUT_OFFSET 0x04E8
#define IOMUXC_CCM_EXT_CLK_3_SELECT_INPUT_OFFSET 0x04EC
#define IOMUXC_CCM_EXT_CLK_4_SELECT_INPUT_OFFSET 0x04F0
#define IOMUXC_CCM_PMIC_READY_SELECT_INPUT_OFFSET 0x04F4
#define IOMUXC_CSI_DATA2_SELECT_INPUT_OFFSET 0x04F8
#define IOMUXC_CSI_DATA3_SELECT_INPUT_OFFSET 0x04FC
#define IOMUXC_CSI_DATA4_SELECT_INPUT_OFFSET 0x0500
#define IOMUXC_CSI_DATA5_SELECT_INPUT_OFFSET 0x0504
#define IOMUXC_CSI_DATA6_SELECT_INPUT_OFFSET 0x0508
#define IOMUXC_CSI_DATA7_SELECT_INPUT_OFFSET 0x050C
#define IOMUXC_CSI_DATA8_SELECT_INPUT_OFFSET 0x0510
#define IOMUXC_CSI_DATA9_SELECT_INPUT_OFFSET 0x0514
#define IOMUXC_CSI_HSYNC_SELECT_INPUT_OFFSET 0x0518
#define IOMUXC_CSI_PIXCLK_SELECT_INPUT_OFFSET 0x051C
#define IOMUXC_CSI_VSYNC_SELECT_INPUT_OFFSET 0x0520
#define IOMUXC_ECSPI1_SCLK_SELECT_INPUT_OFFSET 0x0524
#define IOMUXC_ECSPI1_MISO_SELECT_INPUT_OFFSET 0x0528
#define IOMUXC_ECSPI1_MOSI_SELECT_INPUT_OFFSET 0x052C
#define IOMUXC_ECSPI1_SS0_B_SELECT_INPUT_OFFSET 0x0530
#define IOMUXC_ECSPI2_SCLK_SELECT_INPUT_OFFSET 0x0534
#define IOMUXC_ECSPI2_MISO_SELECT_INPUT_OFFSET 0x0538
#define IOMUXC_ECSPI2_MOSI_SELECT_INPUT_OFFSET 0x053C
#define IOMUXC_ECSPI2_SS0_B_SELECT_INPUT_OFFSET 0x0540
#define IOMUXC_ECSPI3_SCLK_SELECT_INPUT_OFFSET 0x0544
#define IOMUXC_ECSPI3_MISO_SELECT_INPUT_OFFSET 0x0548
#define IOMUXC_ECSPI3_MOSI_SELECT_INPUT_OFFSET 0x054C
#define IOMUXC_ECSPI3_SS0_B_SELECT_INPUT_OFFSET 0x0550
#define IOMUXC_ECSPI4_SCLK_SELECT_INPUT_OFFSET 0x0554
#define IOMUXC_ECSPI4_MISO_SELECT_INPUT_OFFSET 0x0558
#define IOMUXC_ECSPI4_MOSI_SELECT_INPUT_OFFSET 0x055C
#define IOMUXC_ECSPI4_SS0_B_SELECT_INPUT_OFFSET 0x0560
#define IOMUXC_CCM_ENET1_REF_CLK_SELECT_INPUT_OFFSET 0x0564
#define IOMUXC_ENET1_MDIO_SELECT_INPUT_OFFSET 0x0568
#define IOMUXC_ENET1_RX_CLK_SELECT_INPUT_OFFSET 0x056C
#define IOMUXC_CCM_ENET2_REF_CLK_SELECT_INPUT_OFFSET 0x0570
#define IOMUXC_ENET2_MDIO_SELECT_INPUT_OFFSET 0x0574
#define IOMUXC_ENET2_RX_CLK_SELECT_INPUT_OFFSET 0x0578
#define IOMUXC_EPDC_PWR_IRQ_SELECT_INPUT_OFFSET 0x057C
#define IOMUXC_EPDC_PWR_STAT_SELECT_INPUT_OFFSET 0x0580
#define IOMUXC_FLEXTIMER1_CH0_SELECT_INPUT_OFFSET 0x0584
#define IOMUXC_FLEXTIMER1_CH1_SELECT_INPUT_OFFSET 0x0588
#define IOMUXC_FLEXTIMER1_CH2_SELECT_INPUT_OFFSET 0x058C
#define IOMUXC_FLEXTIMER1_CH3_SELECT_INPUT_OFFSET 0x0590
#define IOMUXC_FLEXTIMER1_CH4_SELECT_INPUT_OFFSET 0x0594
#define IOMUXC_FLEXTIMER1_CH5_SELECT_INPUT_OFFSET 0x0598
#define IOMUXC_FLEXTIMER1_CH6_SELECT_INPUT_OFFSET 0x059C
#define IOMUXC_FLEXTIMER1_CH7_SELECT_INPUT_OFFSET 0x05A0
#define IOMUXC_FLEXTIMER1_PHA_SELECT_INPUT_OFFSET 0x05A4
#define IOMUXC_FLEXTIMER1_PHB_SELECT_INPUT_OFFSET 0x05A8
#define IOMUXC_FLEXTIMER2_CH0_SELECT_INPUT_OFFSET 0x05AC
#define IOMUXC_FLEXTIMER2_CH1_SELECT_INPUT_OFFSET 0x05B0
#define IOMUXC_FLEXTIMER2_CH2_SELECT_INPUT_OFFSET 0x05B4
#define IOMUXC_FLEXTIMER2_CH3_SELECT_INPUT_OFFSET 0x05B8
#define IOMUXC_FLEXTIMER2_CH4_SELECT_INPUT_OFFSET 0x05BC
#define IOMUXC_FLEXTIMER2_CH5_SELECT_INPUT_OFFSET 0x05C0
#define IOMUXC_FLEXTIMER2_CH6_SELECT_INPUT_OFFSET 0x05C4
#define IOMUXC_FLEXTIMER2_CH7_SELECT_INPUT_OFFSET 0x05C8
#define IOMUXC_FLEXTIMER2_PHA_SELECT_INPUT_OFFSET 0x05CC
#define IOMUXC_FLEXTIMER2_PHB_SELECT_INPUT_OFFSET 0x05D0
#define IOMUXC_I2C1_SCL_SELECT_INPUT_OFFSET 0x05D4
#define IOMUXC_I2C1_SDA_SELECT_INPUT_OFFSET 0x05D8
#define IOMUXC_I2C2_SCL_SELECT_INPUT_OFFSET 0x05DC
#define IOMUXC_I2C2_SDA_SELECT_INPUT_OFFSET 0x05E0
#define IOMUXC_I2C3_SCL_SELECT_INPUT_OFFSET 0x05E4
#define IOMUXC_I2C3_SDA_SELECT_INPUT_OFFSET 0x05E8
#define IOMUXC_I2C4_SCL_SELECT_INPUT_OFFSET 0x05EC
#define IOMUXC_I2C4_SDA_SELECT_INPUT_OFFSET 0x05F0
#define IOMUXC_KPP_COL0_SELECT_INPUT_OFFSET 0x05F4
#define IOMUXC_KPP_COL1_SELECT_INPUT_OFFSET 0x05F8
#define IOMUXC_KPP_COL2_SELECT_INPUT_OFFSET 0x05FC
#define IOMUXC_KPP_COL3_SELECT_INPUT_OFFSET 0x0600
#define IOMUXC_KPP_COL4_SELECT_INPUT_OFFSET 0x0604
#define IOMUXC_KPP_COL5_SELECT_INPUT_OFFSET 0x0608
#define IOMUXC_KPP_COL6_SELECT_INPUT_OFFSET 0x060C
#define IOMUXC_KPP_COL7_SELECT_INPUT_OFFSET 0x0610
#define IOMUXC_KPP_ROW0_SELECT_INPUT_OFFSET 0x0614
#define IOMUXC_KPP_ROW1_SELECT_INPUT_OFFSET 0x0618
#define IOMUXC_KPP_ROW2_SELECT_INPUT_OFFSET 0x061C
#define IOMUXC_KPP_ROW3_SELECT_INPUT_OFFSET 0x0620
#define IOMUXC_KPP_ROW4_SELECT_INPUT_OFFSET 0x0624
#define IOMUXC_KPP_ROW5_SELECT_INPUT_OFFSET 0x0628
#define IOMUXC_KPP_ROW6_SELECT_INPUT_OFFSET 0x062C
#define IOMUXC_KPP_ROW7_SELECT_INPUT_OFFSET 0x0630
#define IOMUXC_LCD_BUSY_SELECT_INPUT_OFFSET 0x0634
#define IOMUXC_LCD_DATA00_SELECT_INPUT_OFFSET 0x0638
#define IOMUXC_LCD_DATA01_SELECT_INPUT_OFFSET 0x063C
#define IOMUXC_LCD_DATA02_SELECT_INPUT_OFFSET 0x0640
#define IOMUXC_LCD_DATA03_SELECT_INPUT_OFFSET 0x0644
#define IOMUXC_LCD_DATA04_SELECT_INPUT_OFFSET 0x0648
#define IOMUXC_LCD_DATA05_SELECT_INPUT_OFFSET 0x064C
#define IOMUXC_LCD_DATA06_SELECT_INPUT_OFFSET 0x0650
#define IOMUXC_LCD_DATA07_SELECT_INPUT_OFFSET 0x0654
#define IOMUXC_LCD_DATA08_SELECT_INPUT_OFFSET 0x0658
#define IOMUXC_LCD_DATA09_SELECT_INPUT_OFFSET 0x065C
#define IOMUXC_LCD_DATA10_SELECT_INPUT_OFFSET 0x0660
#define IOMUXC_LCD_DATA11_SELECT_INPUT_OFFSET 0x0664
#define IOMUXC_LCD_DATA12_SELECT_INPUT_OFFSET 0x0668
#define IOMUXC_LCD_DATA13_SELECT_INPUT_OFFSET 0x066C
#define IOMUXC_LCD_DATA14_SELECT_INPUT_OFFSET 0x0670
#define IOMUXC_LCD_DATA15_SELECT_INPUT_OFFSET 0x0674
#define IOMUXC_LCD_DATA16_SELECT_INPUT_OFFSET 0x0678
#define IOMUXC_LCD_DATA17_SELECT_INPUT_OFFSET 0x067C
#define IOMUXC_LCD_DATA18_SELECT_INPUT_OFFSET 0x0680
#define IOMUXC_LCD_DATA19_SELECT_INPUT_OFFSET 0x0684
#define IOMUXC_LCD_DATA20_SELECT_INPUT_OFFSET 0x0688
#define IOMUXC_LCD_DATA21_SELECT_INPUT_OFFSET 0x068C
#define IOMUXC_LCD_DATA22_SELECT_INPUT_OFFSET 0x0690
#define IOMUXC_LCD_DATA23_SELECT_INPUT_OFFSET 0x0694
#define IOMUXC_LCD_VSYNC_SELECT_INPUT_OFFSET 0x0698
#define IOMUXC_SAI1_RX_BCLK_SELECT_INPUT_OFFSET 0x069C
#define IOMUXC_SAI1_RX_DATA_SELECT_INPUT_OFFSET 0x06A0
#define IOMUXC_SAI1_RX_SYNC_SELECT_INPUT_OFFSET 0x06A4
#define IOMUXC_SAI1_TX_BCLK_SELECT_INPUT_OFFSET 0x06A8
#define IOMUXC_SAI1_TX_SYNC_SELECT_INPUT_OFFSET 0x06AC
#define IOMUXC_SAI2_RX_BCLK_SELECT_INPUT_OFFSET 0x06B0
#define IOMUXC_SAI2_RX_DATA_SELECT_INPUT_OFFSET 0x06B4
#define IOMUXC_SAI2_RX_SYNC_SELECT_INPUT_OFFSET 0x06B8
#define IOMUXC_SAI2_TX_BCLK_SELECT_INPUT_OFFSET 0x06BC
#define IOMUXC_SAI2_TX_SYNC_SELECT_INPUT_OFFSET 0x06C0
#define IOMUXC_SAI3_RX_BCLK_SELECT_INPUT_OFFSET 0x06C4
#define IOMUXC_SAI3_RX_DATA_SELECT_INPUT_OFFSET 0x06C8
#define IOMUXC_SAI3_RX_SYNC_SELECT_INPUT_OFFSET 0x06CC
#define IOMUXC_SAI3_TX_BCLK_SELECT_INPUT_OFFSET 0x06D0
#define IOMUXC_SAI3_TX_SYNC_SELECT_INPUT_OFFSET 0x06D4
#define IOMUXC_SDMA_EVENTS0_SELECT_INPUT_OFFSET 0x06D8
#define IOMUXC_SDMA_EVENTS1_SELECT_INPUT_OFFSET 0x06DC
#define IOMUXC_SIM1_PORT1_PD_SELECT_INPUT_OFFSET 0x06E0
#define IOMUXC_SIM1_PORT1_TRXD_SELECT_INPUT_OFFSET 0x06E4
#define IOMUXC_SIM2_PORT1_PD_SELECT_INPUT_OFFSET 0x06E8
#define IOMUXC_SIM2_PORT1_TRXD_SELECT_INPUT_OFFSET 0x06EC
#define IOMUXC_UART1_RTS_B_SELECT_INPUT_OFFSET 0x06F0
#define IOMUXC_UART1_RX_DATA_SELECT_INPUT_OFFSET 0x06F4
#define IOMUXC_UART2_RTS_B_SELECT_INPUT_OFFSET 0x06F8
#define IOMUXC_UART2_RX_DATA_SELECT_INPUT_OFFSET 0x06FC
#define IOMUXC_UART3_RTS_B_SELECT_INPUT_OFFSET 0x0700
#define IOMUXC_UART3_RX_DATA_SELECT_INPUT_OFFSET 0x0704
#define IOMUXC_UART4_RTS_B_SELECT_INPUT_OFFSET 0x0708
#define IOMUXC_UART4_RX_DATA_SELECT_INPUT_OFFSET 0x070C
#define IOMUXC_UART5_RTS_B_SELECT_INPUT_OFFSET 0x0710
#define IOMUXC_UART5_RX_DATA_SELECT_INPUT_OFFSET 0x0714
#define IOMUXC_UART6_RTS_B_SELECT_INPUT_OFFSET 0x0718
#define IOMUXC_UART6_RX_DATA_SELECT_INPUT_OFFSET 0x071C
#define IOMUXC_UART7_RTS_B_SELECT_INPUT_OFFSET 0x0720
#define IOMUXC_UART7_RX_DATA_SELECT_INPUT_OFFSET 0x0724
#define IOMUXC_USB_OTG2_OC_SELECT_INPUT_OFFSET 0x0728
#define IOMUXC_USB_OTG1_OC_SELECT_INPUT_OFFSET 0x072C
#define IOMUXC_USB_OTG2_ID_SELECT_INPUT_OFFSET 0x0730
#define IOMUXC_USB_OTG1_ID_SELECT_INPUT_OFFSET 0x0734
#define IOMUXC_SD3_CD_B_SELECT_INPUT_OFFSET 0x0738
#define IOMUXC_SD3_WP_SELECT_INPUT_OFFSET 0x073C
/* Pad mux/feature set routines */
void imx_io_muxc_set_pad_alt_function(uint32_t pad_mux_offset, uint32_t alt_function);
void imx_io_muxc_set_pad_features(uint32_t pad_feature_offset, uint32_t pad_features);
#endif /* __IMX_IO_MUX_H__ */
plat/imx/common/include/imx_snvs.h 0 → 100644
View file @ 36044baf
/*
* Copyright (C) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __IMX_SNVS_H__
#define __IMX_SNVS_H__
#include <stdint.h>
#include <arch.h>
struct snvs {
uint32_t hplr;
uint32_t hpcomr;
uint32_t hpcr;
uint32_t hpsicr;
uint32_t hpsvcr;
uint32_t hpsr;
uint32_t hpsvsr;
uint32_t hphacivr;
uint32_t hphacr;
uint32_t hprtcmr;
uint32_t hprtclr;
uint32_t hptamr;
uint32_t hptalr;
uint32_t lplr;
uint32_t lpcr;
uint32_t lpmkcr;
uint32_t lpsvcr;
uint32_t lptgfcr;
uint32_t lptdcr;
uint32_t lpsr;
uint32_t lpsrtcmr;
uint32_t lpsrtclr;
uint32_t lptar;
uint32_t lpsmcmr;
uint32_t lpsmclr;
uint32_t lppgdr;
uint32_t lpgpr0_alias;
uint8_t lpzmkr[32];
uint16_t res0;
uint32_t lpgpr0[4];
uint32_t lptdc2r;
uint32_t lptdsr;
uint32_t lptgf1cr;
uint32_t lptgf2cr;
uint32_t res1[4];
uint32_t lpat1cr;
uint32_t lpat2cr;
uint32_t lpat3cr;
uint32_t lpat4cr;
uint32_t lpat5cr;
uint32_t res2[3];
uint32_t lpatctlr;
uint32_t lpatclkr;
uint32_t lpatrc1r;
uint32_t lpatrc2r;
uint32_t res3[706];
uint32_t hpvidr1;
uint32_t hpvidr2;
} __packed;
/* Define the HPCOMR bits */
#define HPCOMR_NPSWA_EN BIT(31)
#define HPCOMR_HAC_STOP BIT(19)
#define HPCOMR_HAC_CLEAR BIT(18)
#define HPCOMR_HAC_LOAD BIT(17)
#define HPCOMR_HAC_EN BIT(16)
#define HPCOMR_MKS_EN BIT(13)
#define HPCOMR_PROG_ZMK BIT(12)
#define HPCOMR_SW_LPSV BIT(10)
#define HPCOMR_SW_FSV BIT(9)
#define HPCOMR_SW_SV BIT(8)
#define HPCOMR_LP_SWR_DIS BIT(5)
#define HPCOMR_LP_SWR BIT(4)
#define HPCOMR_SSM_SFNS_DIS BIT(2)
#define HPCOMR_SSM_ST_DIS BIT(1)
#define HPCOMR_SSM_ST BIT(0)
void imx_snvs_init(void);
#endif /* __IMX_SNVS_H__ */
plat/imx/common/include/imx_wdog.h 0 → 100644
View file @ 36044baf
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __IMX_WDOG_H__
#define __IMX_WDOG_H__
#include <arch.h>
#include <stdint.h>
struct wdog_regs {
uint16_t wcr;
uint16_t wsr;
uint16_t wrsr;
uint16_t wicr;
uint16_t wmcr;
};
/* WCR bits */
#define WCR_WDZST BIT(0)
#define WCR_WDBG BIT(1)
#define WCR_WDE BIT(2)
#define WCR_WDT BIT(3)
#define WCR_SRS BIT(4)
#define WCR_WDA BIT(5)
#define WCR_SRE BIT(6)
#define WCR_WDW BIT(7)
#define WCR_WT(x) ((x) << 8)
/* WSR bits */
#define WSR_FIRST 0x5555
#define WSR_SECOND 0xAAAA
/* WRSR bits */
#define WRSR_SFTW BIT(0)
#define WRSR_TOUT BIT(1)
#define WRSR_POR BIT(4)
/* WICR bits */
static inline int wicr_calc_wict(int sec, int half_sec)
{
int wict_bits;
/* Represents WICR bits 7 - 0 */
wict_bits = ((sec << 1) | (half_sec ? 1 : 0));
return wict_bits;
}
#define WICR_WTIS BIT(14)
#define WICR_WIE BIT(15)
/* WMCR bits */
#define WMCR_PDE BIT(0)
/* External facing API */
void imx_wdog_init(void);
#endif /* __IMX_WDOG_H__ */
plat/imx/imx7/include/imx_hab_arch.h 0 → 100644
View file @ 36044baf
/*
* Copyright (C) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __IMX_HAB_ARCH_H__
#define __IMX_HAB_ARCH_H__
/* Define the offset the High Assurance Boot callback table is at */
#define HAB_CALLBACK_OFFSET 0x100
#endif /* __IMX_HAB_ARCH_H__ */
plat/imx/imx7/include/imx_regs.h 0 → 100644
View file @ 36044baf
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __IMX_REGS_H__
#define __IMX_REGS_H__
/* Define the processor memory map */
#define OCRAM_S_ALIAS_BASE 0x00000000 /* CM4 Alias Code */
#define ROM_HIGH_BASE 0x00008000 /* ROM high 64k */
#define ROM_HIGH_PROT_BASE 0x00017000 /* ROM high 64k protected */
#define CAAM_BASE 0x00020000 /* CAAM block base address */
#define OCRAM_S_BASE 0x00180000 /* OCRAM_S */
#define ROM_LOW_BASE 0x007f8000 /* ROM low 64k */
#define OCRAM_BASE 0x00900000 /* OCRAM base */
#define CM4_ALIAS_CODE_BASE 0x04000000 /* CM4 alias code */
#define TCM_BASE 0x1fff0000 /* TCM */
#define BOOTROM_CP_BASE 0x20020000 /* Boot ROM (all 96KB) */
#define CM4_ALIAS_SYSTEM_BASE 0x20100000 /* CM4 Alias system */
#define EIM_BASE 0x28000000 /* EIM */
/* BootROM absolute base address */
#define BOOTROM_BASE 0x00000000 /* BootROM */
/* Peripherals like GPIO live in the AIPS range */
#define AIPS1_BASE 0x30000000 /* AIPS1 */
#define AIPS2_BASE 0x30400000 /* AIPS2 */
#define AIPS3_BASE 0x30800000 /* AIPS3 */
#define AIPS4_BASE 0x30c00000 /* AIPS4 */
/* ARM peripherals like GIC */
#define ARM_PERIPHERAL_GIC_BASE 0x31000000 /* GIC */
/* Configuration ports */
#define GPV0_BASE 0x32000000 /* Main config port */
#define GPV1_BASE 0x32100000 /* Wakeup config port */
#define GPV2_BASE 0x32200000 /* Per_s config port */
#define GPV3_BASE 0x32300000 /* Per_m config port */
#define GPV4_BASE 0x32400000 /* Enet config port */
#define GPV5_BASE 0x32500000 /* Display config port */
#define GPV6_BASE 0x32600000 /* M4 conig port */
/* MMAP peripherals - like APBH DMA */
#define APBH_DMA_BASE 0x33000000 /* APBH DMA block */
/* QSPI RX BUFFERS */
#define QSPI_RX_BUFFER_BASE 0x34000000 /* QSPI RX buffers */
/* QSPI1 FLASH */
#define QSPI_FLASH_BASE 0x60000000 /* QSPI1 flash */
/* AIPS1 block addresses */
#define AIPSTZ_CONFIG_OFFSET 0x001f0000
#define CCM_BASE (AIPS1_BASE + 0x380000)
/* Define the maximum number of UART blocks on this SoC */
#define MXC_UART1_BASE (AIPS3_BASE + 0x060000)
#define MXC_UART2_BASE (AIPS3_BASE + 0x070000)
#define MXC_UART3_BASE (AIPS3_BASE + 0x080000)
#define MXC_UART4_BASE (AIPS3_BASE + 0x260000)
#define MXC_UART5_BASE (AIPS3_BASE + 0x270000)
#define MXC_UART6_BASE (AIPS3_BASE + 0x280000)
#define MXC_UART7_BASE (AIPS3_BASE + 0x290000)
#define MXC_MAX_UART_NUM 0x07
/* Define the maximum number of USDHCI blocks on this SoC */
#define MXC_MAX_USDHC_NUM 3
/* Define the number of CSU registers for this SoC */
#define MXC_MAX_CSU_REGS 0x40
#define CSU_BASE (AIPS1_BASE + 0x3E0000)
/* IO Mux block base */
#define MXC_IO_MUXC_BASE (AIPS1_BASE + 0x330000)
/* SNVS base */
#define SNVS_BASE (AIPS1_BASE + 0x370000)
/* GP Timer base */
#define GPT1_BASE_ADDR (AIPS1_BASE + 0x2d0000)
/* MMC base */
#define USDHC1_BASE (AIPS1_BASE + 0xb40000)
#define USDHC2_BASE (AIPS1_BASE + 0xb50000)
#define USDHC3_BASE (AIPS1_BASE + 0xb60000)
/* Arm optional memory mapped counter module base address */
#define SYS_CNTCTL_BASE (AIPS2_BASE + 0x2c0000)
/* Define CAAM AIPS offset */
#define CAAM_AIPS_BASE (AIPS3_BASE + 0x100000)
#define CAAM_NUM_JOB_RINGS 0x03
#define CAAM_NUM_RTIC 0x04
#define CAAM_NUM_DECO 0x01
/* Define watchdog base addresses */
#define WDOG1_BASE (AIPS1_BASE + 0x280000)
#define WDOG2_BASE (AIPS1_BASE + 0x290000)
#define WDOG3_BASE (AIPS1_BASE + 0x2A0000)
#define WDOG4_BASE (AIPS1_BASE + 0x280000)
/* Define the maximum number of WDOG blocks on this SoC */
#define MXC_MAX_WDOG_NUM 0x04
#endif /* __IMX_REGS_H__ */
plat/imx/imx7/warp7/aarch32/warp7_helpers.S 0 → 100644
View file @ 36044baf
/*
* Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch.h>
#include <asm_macros.S>
#include <assert_macros.S>
#include <platform_def.h>
#include <imx_hab.h>
.globl platform_mem_init
.globl plat_get_my_entrypoint
.globl plat_crash_console_init
.globl plat_crash_console_putc
.globl plat_panic_handler
/* ---------------------------------------------
* int plat_mem_init(void)
* Function to initialize memory.
* The HAB hands off the DDR controller already
* setup and ready to use.
* Implement the mandatory function as a NOP
* ---------------------------------------------
*/
func platform_mem_init
bx lr
endfunc platform_mem_init
func plat_get_my_entrypoint
mov r0, #0
bx lr
endfunc plat_get_my_entrypoint
func plat_crash_console_init
mov_imm r0, PLAT_WARP7_BOOT_UART_BASE
mov_imm r1, PLAT_WARP7_BOOT_UART_CLK_IN_HZ
mov_imm r2, PLAT_WARP7_CONSOLE_BAUDRATE
b imx_crash_uart_init
endfunc plat_crash_console_init
func plat_crash_console_putc
mov_imm r1, PLAT_WARP7_BOOT_UART_BASE
b imx_crash_uart_putc
endfunc plat_crash_console_putc
func plat_panic_handler
mov r3, #HAB_ROM_VECTOR_TABLE_FAILSAFE
ldr r3, [r3, #0]
blx r3
endfunc plat_panic_handler
plat/imx/imx7/warp7/include/platform_def.h 0 → 100644
View file @ 36044baf
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __PLATFORM_DEF_H__
#define __PLATFORM_DEF_H__
#include <arch.h>
#include <common_def.h>
#include <tbbr_img_def.h>
#define PLATFORM_STACK_SIZE 0x1000
#define PLATFORM_MAX_CPUS_PER_CLUSTER 2
#define PLATFORM_CLUSTER_COUNT 1
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
#define PLATFORM_CLUSTER1_CORE_COUNT 0
#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER0_CORE_COUNT + \
PLATFORM_CLUSTER1_CORE_COUNT)
#define WARP7_PRIMARY_CPU 0
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
PLATFORM_CORE_COUNT)
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE 2
/* Local power state for power domains in Run state. */
#define PLAT_LOCAL_STATE_RUN 0
/* Local power state for retention. Valid only for CPU power domains */
#define PLAT_LOCAL_STATE_RET 1
/*
* Local power state for OFF/power-down. Valid for CPU and cluster power
* domains.
*/
#define PLAT_LOCAL_STATE_OFF 2
/*
* Macros used to parse state information from State-ID if it is using the
* recommended encoding for State-ID.
*/
#define PLAT_LOCAL_PSTATE_WIDTH 4
#define PLAT_LOCAL_PSTATE_MASK ((1 << PLAT_LOCAL_PSTATE_WIDTH) - 1)
/*
* Some data must be aligned on the biggest cache line size in the platform.
* This is known only to the platform as it might have a combination of
* integrated and external caches.
* i.MX7 has a 32 byte cacheline size
* i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016 pg 244
*/
#define CACHE_WRITEBACK_SHIFT 4
#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
/*
* Partition memory into secure BootROM, OCRAM_S, non-secure DRAM, secure DRAM
*/
#define BOOT_ROM_BASE 0x00000000
#define BOOT_ROM_SIZE 0x00020000
#define OCRAM_S_BASE 0x00180000
#define OCRAM_S_SIZE 0x00008000
/* Controller maps 2GB, board contains 512 MB. 0x80000000 - 0xa0000000 */
#define DRAM_BASE 0x80000000
#define DRAM_SIZE 0x20000000
#define DRAM_LIMIT (DRAM_BASE + DRAM_SIZE)
/* Place OPTEE at minus 32 MB from the end of memory. 0x9e000000 - 0xa0000000 */
#define WARP7_OPTEE_SIZE 0x02000000
#define WARP7_OPTEE_BASE (DRAM_LIMIT - WARP7_OPTEE_SIZE)
#define WARP7_OPTEE_LIMIT (WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE)
/* Place ATF directly beneath OPTEE. 0x9df00000 - 0x9e000000 */
#define BL2_RAM_SIZE 0x00100000
#define BL2_RAM_BASE (WARP7_OPTEE_BASE - BL2_RAM_SIZE)
#define BL2_RAM_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
/* Optional Mailbox. Only relevant on i.MX7D. 0x9deff000 - 0x9df00000*/
#define SHARED_RAM_SIZE 0x00001000
#define SHARED_RAM_BASE (BL2_RAM_BASE - SHARED_RAM_SIZE)
#define SHARED_RAM_LIMIT (SHARED_RAM_BASE + SHARED_RAM_SIZE)
/* Define the absolute location of u-boot 0x87800000 - 0x87900000 */
#define WARP7_UBOOT_SIZE 0x00100000
#define WARP7_UBOOT_BASE (DRAM_BASE + 0x7800000)
#define WARP7_UBOOT_LIMIT (WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE)
/* Define FIP image absolute location 0x80000000 - 0x80100000 */
#define WARP7_FIP_SIZE 0x00100000
#define WARP7_FIP_BASE (DRAM_BASE)
#define WARP7_FIP_LIMIT (WARP7_FIP_BASE + WARP7_FIP_SIZE)
/* Define FIP image location at 1MB offset */
#define WARP7_FIP_MMC_BASE (1024 * 1024)
/* Define the absolute location of DTB 0x83000000 - 0x83100000 */
#define WARP7_DTB_SIZE 0x00100000
#define WARP7_DTB_BASE (DRAM_BASE + 0x03000000)
#define WARP7_DTB_LIMIT (WARP7_DTB_BASE + WARP7_DTB_SIZE)
/*
* BL2 specific defines.
*
* Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
* size plus a little space for growth.
*/
#define BL2_BASE BL2_RAM_BASE
#define BL2_LIMIT (BL2_RAM_BASE + BL2_RAM_SIZE)
/*
* BL3-2/OPTEE
*/
# define BL32_BASE WARP7_OPTEE_BASE
# define BL32_LIMIT (WARP7_OPTEE_BASE + WARP7_OPTEE_SIZE)
/*
* BL3-3/U-BOOT
*/
#define BL33_BASE WARP7_UBOOT_BASE
#define BL33_LIMIT (WARP7_UBOOT_BASE + WARP7_UBOOT_SIZE)
/*
* ATF's view of memory
*
* 0xa0000000 +-----------------+
* | DDR | BL32/OPTEE
* 0x9e000000 +-----------------+
* | DDR | BL23 ATF
* 0x9df00000 +-----------------+
* | DDR | Shared MBOX RAM
* 0x9de00000 +-----------------+
* | DDR | Unallocated
* 0x87900000 +-----------------+
* | DDR | BL33/U-BOOT
* 0x87800000 +-----------------+
* | DDR | Unallocated
* 0x83100000 +-----------------+
* | DDR | DTB
* 0x83000000 +-----------------+
* | DDR | Unallocated
* 0x80100000 +-----------------+
* | DDR | FIP
* 0x80000000 +-----------------+
* | SOC I/0 |
* 0x00a00000 +-----------------+
* | OCRAM | Not used
* 0x00900000 +-----------------+
* | SOC I/0 |
* 0x00188000 +-----------------+
* | OCRAM_S | Not used
* 0x00180000 +-----------------+
* | SOC I/0 |
* 0x00020000 +-----------------+
* | BootROM | BL1
* 0x00000000 +-----------------+
*/
#define PLAT_PHY_ADDR_SPACE_SIZE (1ULL << 32)
#define PLAT_VIRT_ADDR_SPACE_SIZE (1ULL << 32)
#define MAX_MMAP_REGIONS 10
#define MAX_XLAT_TABLES 6
#define MAX_IO_DEVICES 2
#define MAX_IO_HANDLES 3
#define MAX_IO_BLOCK_DEVICES 1
/* UART defines */
#if PLAT_WARP7_UART == 1
#define PLAT_WARP7_UART_BASE MXC_UART1_BASE
#elif PLAT_WARP7_UART == 6
#define IMX_UART_DTE
#define PLAT_WARP7_UART_BASE MXC_UART6_BASE
#else
#error "define PLAT_WARP7_UART=1 or PLAT_WARP7_UART=6"
#endif
#define PLAT_WARP7_BOOT_UART_BASE PLAT_WARP7_UART_BASE
#define PLAT_WARP7_BOOT_UART_CLK_IN_HZ 24000000
#define PLAT_WARP7_CONSOLE_BAUDRATE 115200
/* MMC defines */
#ifndef PLAT_WARP7_SD
#define PLAT_WARP7_SD 3
#endif
#if PLAT_WARP7_SD == 1
#define PLAT_WARP7_BOOT_MMC_BASE USDHC1_BASE
#endif /* PLAT_WARP7_SD == 1 */
#if PLAT_WARP7_SD == 2
#define PLAT_WARP7_BOOT_MMC_BASE USDHC2_BASE
#endif /* PLAT_WARP7_SD == 2 */
#if PLAT_WARP7_SD == 3
#define PLAT_WARP7_BOOT_MMC_BASE USDHC3_BASE
#endif /* PLAT_WARP7_SD == 3 */
/*
* GIC related constants
*/
#define GICD_BASE 0x31001000
#define GICC_BASE 0x31002000
#define GICR_BASE 0
/*
* System counter
*/
#define SYS_COUNTER_FREQ_IN_TICKS 8000000 /* 8 MHz */
#endif /* __PLATFORM_DEF_H__ */
plat/imx/imx7/warp7/platform.mk 0 → 100644
View file @ 36044baf
#
# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Architecture
$(eval $(call add_define,ARMV7_SUPPORTS_LARGE_PAGE_ADDRESSING))
# Tune compiler for Cortex-A7
ifeq ($(notdir $(CC)),armclang)
TF_CFLAGS += -mfpu=neon
ASFLAGS += -mfpu=neon
else ifneq ($(findstring clang,$(notdir $(CC))),)
TF_CFLAGS += -mfpu=neon
ASFLAGS += -mfpu=neon
else
TF_CFLAGS += -mfpu=neon
ASFLAGS += -mfpu=neon
endif
# Platform
PLAT_INCLUDES := -Idrivers/imx/uart \
-Iinclude/common/tbbr \
-Iinclude/plat/arm/common/ \
-Iplat/imx/common/include/ \
-Iplat/imx/imx7/warp7/include \
-Idrivers/imx/timer \
-Idrivers/imx/usdhc \
-Iplat/imx/imx7/include
# Translation tables library
include lib/xlat_tables_v2/xlat_tables.mk
BL2_SOURCES += common/desc_image_load.c \
drivers/console/aarch32/console.S \
drivers/delay_timer/delay_timer.c \
drivers/mmc/mmc.c \
drivers/io/io_block.c \
drivers/io/io_fip.c \
drivers/io/io_memmap.c \
drivers/io/io_storage.c \
drivers/imx/timer/imx_gpt.c \
drivers/imx/uart/imx_uart.c \
drivers/imx/uart/imx_crash_uart.S \
drivers/imx/usdhc/imx_usdhc.c \
lib/aarch32/arm32_aeabi_divmod.c \
lib/aarch32/arm32_aeabi_divmod_a32.S \
lib/cpus/aarch32/cortex_a7.S \
lib/optee/optee_utils.c \
plat/imx/common/imx_aips.c \
plat/imx/common/imx_caam.c \
plat/imx/common/imx_clock.c \
plat/imx/common/imx_csu.c \
plat/imx/common/imx_io_mux.c \
plat/imx/common/imx_snvs.c \
plat/imx/common/imx_wdog.c \
plat/imx/common/imx7_clock.c \
plat/imx/imx7/warp7/aarch32/warp7_helpers.S \
plat/imx/imx7/warp7/warp7_bl2_el3_setup.c \
plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c \
plat/imx/imx7/warp7/warp7_io_storage.c \
plat/imx/imx7/warp7/warp7_image_load.c \
${XLAT_TABLES_LIB_SRCS}
# Build config flags
# ------------------
WORKAROUND_CVE_2017_5715 := 0
# Disable the PSCI platform compatibility layer by default
ENABLE_PLAT_COMPAT := 0
# Enable reset to BL31 by default
RESET_TO_BL31 := 0
# Non-TF Boot ROM
BL2_AT_EL3 := 1
# Indicate single-core
COLD_BOOT_SINGLE_CPU := 1
# Have different sections for code and rodata
SEPARATE_CODE_AND_RODATA := 1
# Use Coherent memory
USE_COHERENT_MEM := 1
# Enable new version of image loading required for AArch32
LOAD_IMAGE_V2 := 1
# PLAT_WARP7_UART
PLAT_WARP7_UART :=1
$(eval $(call add_define,PLAT_WARP7_UART))
# Verify build config
# -------------------
ifneq (${LOAD_IMAGE_V2}, 1)
$(error Error: warp7 needs LOAD_IMAGE_V2=1)
endif
ifeq (${ARCH},aarch64)
$(error Error: AArch64 not supported on i.mx7)
endif
plat/imx/imx7/warp7/warp7_bl2_el3_setup.c 0 → 100644
View file @ 36044baf
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <console.h>
#include <debug.h>
#include <desc_image_load.h>
#include <mmc.h>
#include <mmio.h>
#include <optee_utils.h>
#include <platform_def.h>
#include <utils.h>
#include <xlat_mmu_helpers.h>
#include <xlat_tables_defs.h>
#include <imx_aips.h>
#include <imx_caam.h>
#include <imx_clock.h>
#include <imx_csu.h>
#include <imx_gpt.h>
#include <imx_io_mux.h>
#include <imx_uart.h>
#include <imx_snvs.h>
#include <imx_usdhc.h>
#include <imx_wdog.h>
#include "warp7_private.h"
#define UART1_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
CCM_TRGT_MUX_UART1_CLK_ROOT_OSC_24M)
#define UART6_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
CCM_TRGT_MUX_UART6_CLK_ROOT_OSC_24M)
#define USDHC_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
CCM_TRGT_MUX_NAND_USDHC_BUS_CLK_ROOT_AHB |\
CCM_TARGET_POST_PODF(2))
#define WDOG_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
CCM_TRGT_MUX_WDOG_CLK_ROOT_OSC_24M)
#define USB_CLK_SELECT (CCM_TARGET_ROOT_ENABLE |\
CCM_TRGT_MUX_USB_HSIC_CLK_ROOT_SYS_PLL)
uintptr_t plat_get_ns_image_entrypoint(void)
{
return WARP7_UBOOT_BASE;
}
static uint32_t warp7_get_spsr_for_bl32_entry(void)
{
return SPSR_MODE32(MODE32_svc, SPSR_T_ARM, SPSR_E_LITTLE,
DISABLE_ALL_EXCEPTIONS);
}
static uint32_t warp7_get_spsr_for_bl33_entry(void)
{
return SPSR_MODE32(MODE32_svc,
plat_get_ns_image_entrypoint() & 0x1,
SPSR_E_LITTLE, DISABLE_ALL_EXCEPTIONS);
}
#ifndef AARCH32_SP_OPTEE
#error "Must build with OPTEE support included"
#endif
int bl2_plat_handle_post_image_load(unsigned int image_id)
{
int err = 0;
bl_mem_params_node_t *bl_mem_params = get_bl_mem_params_node(image_id);
bl_mem_params_node_t *hw_cfg_mem_params = NULL;
bl_mem_params_node_t *pager_mem_params = NULL;
bl_mem_params_node_t *paged_mem_params = NULL;
assert(bl_mem_params);
switch (image_id) {
case BL32_IMAGE_ID:
pager_mem_params = get_bl_mem_params_node(BL32_EXTRA1_IMAGE_ID);
assert(pager_mem_params);
paged_mem_params = get_bl_mem_params_node(BL32_EXTRA2_IMAGE_ID);
assert(paged_mem_params);
err = parse_optee_header(&bl_mem_params->ep_info,
&pager_mem_params->image_info,
&paged_mem_params->image_info);
if (err != 0)
WARN("OPTEE header parse error.\n");
/*
* When ATF loads the DTB the address of the DTB is passed in
* arg2, if an hw config image is present use the base address
* as DTB address an pass it as arg2
*/
hw_cfg_mem_params = get_bl_mem_params_node(HW_CONFIG_ID);
bl_mem_params->ep_info.args.arg0 =
bl_mem_params->ep_info.args.arg1;
bl_mem_params->ep_info.args.arg1 = 0;
if (hw_cfg_mem_params)
bl_mem_params->ep_info.args.arg2 =
hw_cfg_mem_params->image_info.image_base;
else
bl_mem_params->ep_info.args.arg2 = 0;
bl_mem_params->ep_info.args.arg3 = 0;
bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl32_entry();
break;
case BL33_IMAGE_ID:
/* AArch32 only core: OP-TEE expects NSec EP in register LR */
pager_mem_params = get_bl_mem_params_node(BL32_IMAGE_ID);
assert(pager_mem_params);
pager_mem_params->ep_info.lr_svc = bl_mem_params->ep_info.pc;
/* BL33 expects to receive the primary CPU MPID (through r0) */
bl_mem_params->ep_info.args.arg0 = 0xffff & read_mpidr();
bl_mem_params->ep_info.spsr = warp7_get_spsr_for_bl33_entry();
break;
default:
/* Do nothing in default case */
break;
}
return err;
}
void bl2_el3_plat_arch_setup(void)
{
/* Setup the MMU here */
}
#define WARP7_UART1_TX_MUX \
IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_ALT0_UART1_TX_DATA
#define WARP7_UART1_TX_FEATURES \
(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PS_3_100K_PU | \
IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_PE_EN | \
IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_HYS_EN | \
IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_DSE_1_X4)
#define WARP7_UART1_RX_MUX \
IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_ALT0_UART1_RX_DATA
#define WARP7_UART1_RX_FEATURES \
(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PS_3_100K_PU | \
IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_PE_EN | \
IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_HYS_EN | \
IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_DSE_1_X4)
#define WARP7_UART6_TX_MUX \
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_ALT1_UART6_TX_DATA
#define WARP7_UART6_TX_FEATURES \
(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PS_3_100K_PU | \
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_PE_EN | \
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_HYS_EN | \
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_DSE_1_X4)
#define WARP7_UART6_RX_MUX \
IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_ALT1_UART6_RX_DATA
#define WARP7_UART6_RX_FEATURES \
(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PS_3_100K_PU | \
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_PE_EN | \
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_HYS_EN | \
IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_DSE_1_X4)
static void warp7_setup_pinmux(void)
{
/* Configure UART1 TX */
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_TX_DATA_OFFSET,
WARP7_UART1_TX_MUX);
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_TX_DATA_OFFSET,
WARP7_UART1_TX_FEATURES);
/* Configure UART1 RX */
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_UART1_RX_DATA_OFFSET,
WARP7_UART1_RX_MUX);
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_UART1_RX_DATA_OFFSET,
WARP7_UART1_RX_FEATURES);
/* Configure UART6 TX */
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_MOSI_OFFSET,
WARP7_UART6_TX_MUX);
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_MOSI_OFFSET,
WARP7_UART6_TX_FEATURES);
/* Configure UART6 RX */
imx_io_muxc_set_pad_alt_function(IOMUXC_SW_MUX_CTL_PAD_ECSPI1_SCLK_OFFSET,
WARP7_UART6_RX_MUX);
imx_io_muxc_set_pad_features(IOMUXC_SW_PAD_CTL_PAD_ECSPI1_SCLK_OFFSET,
WARP7_UART6_RX_FEATURES);
}
static void warp7_usdhc_setup(void)
{
imx_usdhc_params_t params;
struct mmc_device_info info;
zeromem(&params, sizeof(imx_usdhc_params_t));
params.reg_base = PLAT_WARP7_BOOT_MMC_BASE;
params.clk_rate = 25000000;
params.bus_width = MMC_BUS_WIDTH_8;
info.mmc_dev_type = MMC_IS_EMMC;
imx_usdhc_init(&params, &info);
}
static void warp7_setup_system_counter(void)
{
unsigned long freq = SYS_COUNTER_FREQ_IN_TICKS;
/* Set the frequency table index to our target frequency */
write_cntfrq(freq);
/* Enable system counter @ frequency table index 0, halt on debug */
mmio_write_32(SYS_CNTCTL_BASE + CNTCR_OFF,
CNTCR_FCREQ(0) | CNTCR_HDBG | CNTCR_EN);
}
static void warp7_setup_wdog_clocks(void)
{
uint32_t wdog_en_bits = (uint32_t)WDOG_CLK_SELECT;
imx_clock_set_wdog_clk_root_bits(wdog_en_bits);
imx_clock_enable_wdog(0);
imx_clock_enable_wdog(1);
imx_clock_enable_wdog(2);
imx_clock_enable_wdog(3);
}
static void warp7_setup_usb_clocks(void)
{
uint32_t usb_en_bits = (uint32_t)USB_CLK_SELECT;
imx_clock_set_usb_clk_root_bits(usb_en_bits);
imx_clock_enable_usb(CCM_CCGR_ID_USB_IPG);
imx_clock_enable_usb(CCM_CCGR_ID_USB_PHY_480MCLK);
imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG1_PHY);
imx_clock_enable_usb(CCM_CCGR_ID_USB_OTG2_PHY);
}
/*
* bl2_early_platform_setup()
* MMU off
*/
void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
u_register_t arg3, u_register_t arg4)
{
uint32_t uart1_en_bits = (uint32_t)UART1_CLK_SELECT;
uint32_t uart6_en_bits = (uint32_t)UART6_CLK_SELECT;
uint32_t usdhc_clock_sel = PLAT_WARP7_SD - 1;
/* Initialize the AIPS */
imx_aips_init();
imx_csu_init();
imx_snvs_init();
imx_gpt_ops_init(GPT1_BASE_ADDR);
/* Initialize clocks, regulators, pin-muxes etc */
imx_clock_init();
imx_clock_enable_uart(0, uart1_en_bits);
imx_clock_enable_uart(5, uart6_en_bits);
imx_clock_enable_usdhc(usdhc_clock_sel, USDHC_CLK_SELECT);
warp7_setup_system_counter();
warp7_setup_wdog_clocks();
warp7_setup_usb_clocks();
/* Setup pin-muxes */
warp7_setup_pinmux();
/* Init UART, storage and friends */
console_init(PLAT_WARP7_BOOT_UART_BASE, PLAT_WARP7_BOOT_UART_CLK_IN_HZ,
PLAT_WARP7_CONSOLE_BAUDRATE);
warp7_usdhc_setup();
/* Open handles to persistent storage */
plat_warp7_io_setup();
/* Setup higher-level functionality CAAM, RTC etc */
imx_caam_init();
imx_wdog_init();
/* Print out the expected memory map */
VERBOSE("\tOPTEE 0x%08x-0x%08x\n", WARP7_OPTEE_BASE, WARP7_OPTEE_LIMIT);
VERBOSE("\tATF/BL2 0x%08x-0x%08x\n", BL2_RAM_BASE, BL2_RAM_LIMIT);
VERBOSE("\tSHRAM 0x%08x-0x%08x\n", SHARED_RAM_BASE, SHARED_RAM_LIMIT);
VERBOSE("\tFIP 0x%08x-0x%08x\n", WARP7_FIP_BASE, WARP7_FIP_LIMIT);
VERBOSE("\tDTB 0x%08x-0x%08x\n", WARP7_DTB_BASE, WARP7_DTB_LIMIT);
VERBOSE("\tUBOOT/BL33 0x%08x-0x%08x\n", WARP7_UBOOT_BASE, WARP7_UBOOT_LIMIT);
}
/*
* bl2_platform_setup()
* MMU on - enabled by bl2_el3_plat_arch_setup()
*/
void bl2_platform_setup(void)
{
}
plat/imx/imx7/warp7/warp7_bl2_mem_params_desc.c 0 → 100644
View file @ 36044baf
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <bl_common.h>
#include <desc_image_load.h>
#include <platform.h>
#include <platform_def.h>
static bl_mem_params_node_t bl2_mem_params_descs[] = {
{
.image_id = BL32_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
entry_point_info_t,
SECURE | EXECUTABLE | EP_FIRST_EXE),
.ep_info.pc = BL32_BASE,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
image_info_t, 0),
.image_info.image_base = WARP7_OPTEE_BASE,
.image_info.image_max_size = WARP7_OPTEE_SIZE,
.next_handoff_image_id = BL33_IMAGE_ID,
},
{
.image_id = HW_CONFIG_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
VERSION_2, image_info_t, 0),
.image_info.image_base = WARP7_DTB_BASE,
.image_info.image_max_size = WARP7_DTB_SIZE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
{
.image_id = BL32_EXTRA1_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
entry_point_info_t,
SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, VERSION_2,
image_info_t, IMAGE_ATTRIB_SKIP_LOADING),
.image_info.image_base = WARP7_OPTEE_BASE,
.image_info.image_max_size = WARP7_OPTEE_SIZE,
.next_handoff_image_id = INVALID_IMAGE_ID,
},
{
/* This is a zero sized image so we don't set base or size */
.image_id = BL32_EXTRA2_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t,
SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t,
IMAGE_ATTRIB_SKIP_LOADING),
.next_handoff_image_id = INVALID_IMAGE_ID,
},
{
.image_id = BL33_IMAGE_ID,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, VERSION_2,
entry_point_info_t,
NON_SECURE | EXECUTABLE),
# ifdef PRELOADED_BL33_BASE
.ep_info.pc = PRELOADED_BL33_BASE,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t,
IMAGE_ATTRIB_SKIP_LOADING),
# else
.ep_info.pc = BL33_BASE,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0),
.image_info.image_base = WARP7_UBOOT_BASE,
.image_info.image_max_size = WARP7_UBOOT_SIZE,
# endif /* PRELOADED_BL33_BASE */
.next_handoff_image_id = INVALID_IMAGE_ID,
}
};
REGISTER_BL_IMAGE_DESCS(bl2_mem_params_descs);
plat/imx/imx7/warp7/warp7_image_load.c 0 → 100644
View file @ 36044baf
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <bl_common.h>
#include <desc_image_load.h>
#include <platform.h>
void plat_flush_next_bl_params(void)
{
flush_bl_params_desc();
}
bl_load_info_t *plat_get_bl_image_load_info(void)
{
return get_bl_load_info_from_mem_params_desc();
}
bl_params_t *plat_get_next_bl_params(void)
{
return get_next_bl_params_from_mem_params_desc();
}
plat/imx/imx7/warp7/warp7_io_storage.c 0 → 100644
View file @ 36044baf
/*
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <debug.h>
#include <mmc.h>
#include <firmware_image_package.h>
#include <io_block.h>
#include <io_driver.h>
#include <io_fip.h>
#include <io_memmap.h>
#include <platform_def.h>
static const io_dev_connector_t *fip_dev_con;
static uintptr_t fip_dev_handle;
#ifndef WARP7_FIP_MMAP
static const io_dev_connector_t *mmc_dev_con;
static uintptr_t mmc_dev_handle;
static const io_block_spec_t mmc_fip_spec = {
.offset = WARP7_FIP_MMC_BASE,
.length = WARP7_FIP_SIZE
};
static const io_block_dev_spec_t mmc_dev_spec = {
/* It's used as temp buffer in block driver. */
.buffer = {
.offset = WARP7_FIP_BASE,
/* do we need a new value? */
.length = WARP7_FIP_SIZE
},
.ops = {
.read = mmc_read_blocks,
.write = mmc_write_blocks,
},
.block_size = MMC_BLOCK_SIZE,
};
static int open_mmc(const uintptr_t spec);
#else
static const io_dev_connector_t *memmap_dev_con;
static uintptr_t memmap_dev_handle;
static const io_block_spec_t fip_block_spec = {
.offset = WARP7_FIP_BASE,
.length = WARP7_FIP_SIZE
};
static int open_memmap(const uintptr_t spec);
#endif
static int open_fip(const uintptr_t spec);
static const io_uuid_spec_t bl32_uuid_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32,
};
static const io_uuid_spec_t hw_config_uuid_spec = {
.uuid = UUID_HW_CONFIG,
};
static const io_uuid_spec_t bl32_extra1_uuid_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA1,
};
static const io_uuid_spec_t bl32_extra2_uuid_spec = {
.uuid = UUID_SECURE_PAYLOAD_BL32_EXTRA2,
};
static const io_uuid_spec_t bl33_uuid_spec = {
.uuid = UUID_NON_TRUSTED_FIRMWARE_BL33,
};
/* TODO: this structure is replicated multiple times. rationalize it ! */
struct plat_io_policy {
uintptr_t *dev_handle;
uintptr_t image_spec;
int (*check)(const uintptr_t spec);
};
static const struct plat_io_policy policies[] = {
#ifndef WARP7_FIP_MMAP
[FIP_IMAGE_ID] = {
&mmc_dev_handle,
(uintptr_t)&mmc_fip_spec,
open_mmc
},
#else
[FIP_IMAGE_ID] = {
&memmap_dev_handle,
(uintptr_t)&fip_block_spec,
open_memmap
},
#endif
[BL32_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl32_uuid_spec,
open_fip
},
[BL32_EXTRA1_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl32_extra1_uuid_spec,
open_fip
},
[BL32_EXTRA2_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl32_extra2_uuid_spec,
open_fip
},
[HW_CONFIG_ID] = {
&fip_dev_handle,
(uintptr_t)&hw_config_uuid_spec,
open_fip
},
[BL33_IMAGE_ID] = {
&fip_dev_handle,
(uintptr_t)&bl33_uuid_spec,
open_fip
}
};
static int open_fip(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
/* See if a Firmware Image Package is available */
result = io_dev_init(fip_dev_handle, (uintptr_t)FIP_IMAGE_ID);
if (result == 0) {
result = io_open(fip_dev_handle, spec, &local_image_handle);
if (result == 0) {
VERBOSE("Using FIP\n");
io_close(local_image_handle);
}
}
return result;
}
#ifndef WARP7_FIP_MMAP
static int open_mmc(const uintptr_t spec)
{
int result;
uintptr_t local_handle;
result = io_dev_init(mmc_dev_handle, (uintptr_t)NULL);
if (result == 0) {
result = io_open(mmc_dev_handle, spec, &local_handle);
if (result == 0)
io_close(local_handle);
}
return result;
}
#else
static int open_memmap(const uintptr_t spec)
{
int result;
uintptr_t local_image_handle;
result = io_dev_init(memmap_dev_handle, (uintptr_t)NULL);
if (result == 0) {
result = io_open(memmap_dev_handle, spec, &local_image_handle);
if (result == 0) {
VERBOSE("Using Memmap\n");
io_close(local_image_handle);
}
}
return result;
}
#endif
int plat_get_image_source(unsigned int image_id, uintptr_t *dev_handle,
uintptr_t *image_spec)
{
int result;
const struct plat_io_policy *policy;
assert(image_id < ARRAY_SIZE(policies));
policy = &policies[image_id];
result = policy->check(policy->image_spec);
assert(result == 0);
*image_spec = policy->image_spec;
*dev_handle = *policy->dev_handle;
return result;
}
void plat_warp7_io_setup(void)
{
int result __unused;
#ifndef WARP7_FIP_MMAP
result = register_io_dev_block(&mmc_dev_con);
assert(result == 0);
result = io_dev_open(mmc_dev_con, (uintptr_t)&mmc_dev_spec,
&mmc_dev_handle);
assert(result == 0);
#else
result = register_io_dev_memmap(&memmap_dev_con);
assert(result == 0);
result = io_dev_open(memmap_dev_con, (uintptr_t)NULL,
&memmap_dev_handle);
assert(result == 0);
#endif
result = register_io_dev_fip(&fip_dev_con);
assert(result == 0);
result = io_dev_open(fip_dev_con, (uintptr_t)NULL,
&fip_dev_handle);
assert(result == 0);
}
plat/imx/imx7/warp7/warp7_private.h 0 → 100644
View file @ 36044baf
/*
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __WARP7_PRIVATE_H__
#define __WARP7_PRIVATE_H__
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
void plat_warp7_io_setup(void);
#endif /*__WARP7_PRIVATE_H__ */
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