Merge pull request #1515 from bryanodonoghue/atf-master+linaro-warp7-squash-v4

Atf master+linaro warp7 squash v4

docs/plat/warp7.rst

+Trusted Firmware-A for i.MX7 WaRP7
+==================================
+
+The Trusted Firmware-A port for the i.MX7Solo WaRP7 implements BL2 at EL3.
+The i.MX7S contains a BootROM with a High Assurance Boot (HAB) functionality.
+This functionality provides a mechanism for establishing a root-of-trust from
+the reset vector to the command-line in user-space.
+
+Boot Flow
+=========
+
+BootROM --> TF-A BL2 --> BL32(OP-TEE) --> BL33(U-Boot) --> Linux
+
+In the WaRP7 port we encapsulate OP-TEE, DTB and U-Boot into a FIP. This FIP is
+expected and required
+
+# Build Instructions
+
+We need to use a file generated by u-boot in order to generate a .imx image the
+BootROM will boot. It is therefore _required_ to build u-boot before TF-A and
+furthermore it is _recommended_ to use the mkimage in the u-boot/tools directory
+to generate the TF-A .imx image.
+
+## U-Boot:
+
+https://git.linaro.org/landing-teams/working/mbl/u-boot.git
+
+.. code:: shell
+
+    git checkout -b rms-atf-optee-uboot linaro-mbl/rms-atf-optee-uboot
+    make warp7_bl33_defconfig;
+    make u-boot.imx arch=ARM CROSS_COMPILE=arm-linux-gnueabihf-
+
+## TF-A:
+
+https://github.com/ARM-software/arm-trusted-firmware.git
+
+.. code:: shell
+
+    make CROSS_COMPILE=arm-linux-gnueabihf- PLAT=warp7 ARCH=aarch32 ARM_ARCH_MAJOR=7 ARM_CORTEX_A7=yes AARCH32_SP=optee all
+    /path/to/u-boot/tools/mkimage -n /path/to/u-boot/u-boot.cfgout -T imximage -e 0x9df00000 -d ./build/warp7/debug/bl2.bin ./build/warp7/debug/bl2.bin.imx
+
+## OP-TEE:
+
+https://github.com/OP-TEE/optee_os.git
+
+.. code:: shell
+
+    make ARCH=arm CROSS_COMPILE=arm-linux-gnueabihf- PLATFORM=imx PLATFORM_FLAVOR=mx7swarp7 ARCH=arm CFG_PAGEABLE_ADDR=0 CFG_DT_ADDR=0x83000000 CFG_NS_ENTRY_ADDR=0x87800000
+
+
+## FIP:
+
+.. code:: shell
+
+    mkdir fiptool_images
+    cp /path/to/uboot/u-boot.bin fiptool_images
+    cp /path/to/optee/out/arm-plat-imx/core/tee-header_v2.bin fiptool_images
+    cp /path/to/optee/out/arm-plat-imx/core/tee-pager_v2.bin fiptool_images
+    cp /path/to/optee/out/arm-plat-imx/core/tee-pageable_v2.bin fiptool_images
+    cp /path/to/linux/arch/boot/dts/imx7s-warp.dtb fiptool_images
+    tools/fiptool/fiptool create --tos-fw fiptool_images/tee-header_v2.bin --tos-fw-extra1 fiptool_images/tee-pager_v2.bin --tos-fw-extra2 fiptool_images/tee-pageable_v2.bin --nt-fw fiptool_images/u-boot.bin --hw-config fiptool_images/imx7s-warp.dtb warp7.fip
+
+
+# Deploy Images
+
+
+First place the WaRP7 into UMS mode in u-boot this should produce an entry in
+/dev like /dev/disk/by-id/usb-Linux_UMS_disk_0_WaRP7-0xf42400d3000001d4-0\:0
+
+.. code:: shell
+
+    => ums 0 mmc 0
+
+Next flash bl2.imx and warp7.fip
+
+bl2.imx is flashed @ 1024 bytes
+warp7.fip is flash @ 1048576 bytes
+
+.. code:: shell
+
+    sudo dd if=bl2.bin.imx of=/dev/disk/by-id/usb-Linux_UMS_disk_0_WaRP7-0xf42400d3000001d4-0\:0 bs=512 seek=2 conv=notrunc
+    # Offset is 1MB 1048576 => 1048576 / 512 = 2048
+    sudo dd if=./warp7.fip of=/dev/disk/by-id/usb-Linux_UMS_disk_0_WaRP7-0xf42400d3000001d4-0\:0 bs=512 seek=2048 conv=notrunc
+
+Remember to umount the USB device pefore proceeding
+
+.. code:: shell
+
+    sudo umount /dev/disk/by-id/usb-Linux_UMS_disk_0_WaRP7-0xf42400d3000001d4-0\:0*
+
+
+# Signing BL2
+
+A further step is to sign BL2.
+
+The image_sign.sh and bl2_sign.csf files alluded to blow are available here.
+
+https://github.com/bryanodonoghue/atf-code-signing
+
+It is suggested you use this script plus the example CSF file in order to avoid
+hard-coding data into your CSF files.
+
+Download both "image_sign.sh" and "bl2_sign.csf" to your
+arm-trusted-firmware top-level directory.
+
+.. code:: shell
+
+    #!/bin/bash
+    SIGN=image_sign.sh
+    TEMP=`pwd`/temp
+    BL2_CSF=bl2_sign.csf
+    BL2_IMX=bl2.bin.imx
+    CST_PATH=/path/to/cst-2.3.2
+    CST_BIN=${CST_PATH}/linux64/cst
+
+    #Remove temp
+    rm -rf ${TEMP}
+    mkdir ${TEMP}
+
+    # Generate IMX header
+    /path/to/u-boot/tools/mkimage -n u-boot.cfgout.warp7 -T imximage -e 0x9df00000 -d ./build/warp7/debug/bl2.bin ./build/warp7/debug/bl2.bin.imx > ${TEMP}/${BL2_IMX}.log
+
+    # Copy required items to $TEMP
+    cp build/warp7/debug/bl2.bin.imx ${TEMP}
+    cp ${CST_PATH}/keys/* ${TEMP}
+    cp ${CST_PATH}/crts/* ${TEMP}
+    cp ${BL2_CSF} ${TEMP}
+
+    # Generate signed BL2 image
+    ./${SIGN} image_sign_mbl_binary ${TEMP} ${BL2_CSF} ${BL2_IMX} ${CST_BIN}
+
+    # Copy signed BL2 to top-level directory
+    cp ${TEMP}/${BL2_IMX}-signed .
+    cp ${BL2_RECOVER_CSF} ${TEMP}
+
+
+The resulting bl2.bin.imx-signed can replace bl2.bin.imx in the Deploy
+Images section above, once done.
+
+Suggested flow for verifying.
+
+1. Followed all previous steps above and verify a non-secure ATF boot
+2. Down the NXP Code Singing Tool
+3. Generate keys
+4. Program the fuses on your board
+5. Replace bl2.bin.imx with bl2.bin.imx-signed
+6. Verify inside u-boot that "hab_status" shows no events
+7. Subsequently close your board.
+
+If you have HAB events @ step 6 - do not lock your board.
+
+To get a good over-view of generating keys and programming the fuses on the
+board read "High Assurance Boot for Dummies" by Boundary Devices.
+
+https://boundarydevices.com/high-assurance-boot-hab-dummies/

drivers/imx/timer/imx_gpt.c

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+#include <delay_timer.h>
+#include <mmio.h>
+#include <imx_gpt.h>
+
+#define GPTCR_SWR		BIT(15)		/* Software reset */
+#define GPTCR_24MEN		BIT(10)		/* Enable 24MHz clock input */
+#define GPTCR_CLKSOURCE_OSC	(5 << 6)        /* Clock source OSC */
+#define GPTCR_CLKSOURCE_MASK	(0x7 << 6)
+#define GPTCR_TEN		1		/* Timer enable */
+
+#define GPTPR_PRESCL_24M_SHIFT 12
+
+#define SYS_COUNTER_FREQ_IN_MHZ 3
+
+#define GPTPR_TIMER_CTRL	(imx_base_addr + 0x000)
+#define GPTPR_TIMER_PRESCL	(imx_base_addr + 0x004)
+#define GPTPR_TIMER_CNTR	(imx_base_addr + 0x024)
+
+static uintptr_t imx_base_addr;
+
+uint32_t imx_get_timer_value(void)
+{
+	return ~mmio_read_32(GPTPR_TIMER_CNTR);
+}
+
+static const timer_ops_t imx_gpt_ops = {
+	.get_timer_value	= imx_get_timer_value,
+	.clk_mult		= 1,
+	.clk_div		= SYS_COUNTER_FREQ_IN_MHZ,
+};
+
+void imx_gpt_ops_init(uintptr_t base_addr)
+{
+	int val;
+
+	assert(base_addr != 0);
+
+	imx_base_addr = base_addr;
+
+	/* setup GP Timer */
+	mmio_write_32(GPTPR_TIMER_CTRL, GPTCR_SWR);
+	mmio_write_32(GPTPR_TIMER_CTRL, 0);
+
+	/* get 3MHz from 24MHz */
+	mmio_write_32(GPTPR_TIMER_PRESCL, (7 << GPTPR_PRESCL_24M_SHIFT));
+
+	val = mmio_read_32(GPTPR_TIMER_CTRL);
+	val &= ~GPTCR_CLKSOURCE_MASK;
+	val |= GPTCR_24MEN | GPTCR_CLKSOURCE_OSC | GPTCR_TEN;
+	mmio_write_32(GPTPR_TIMER_CTRL, val);
+
+	timer_init(&imx_gpt_ops);
+}

drivers/imx/timer/imx_gpt.h

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __IMX_GPT_H__
+#define __IMX_GPT_H__
+
+#include <stdint.h>
+
+void imx_gpt_ops_init(uintptr_t reg_base);
+
+#endif /* __IMX_GPT_H__ */

drivers/imx/uart/imx_crash_uart.S

+/*
+ * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <asm_macros.S>
+#include <assert_macros.S>
+#include <imx_uart.h>
+#include <platform_def.h>
+
+	.globl	imx_crash_uart_init
+	.globl	imx_crash_uart_putc
+
+	/* -----------------------------------------------
+	 * int imx_crash_uart_init(uintptr_t base_addr,
+	 * unsigned int uart_clk, unsigned int baud_rate)
+	 * Function to initialize the console without a
+	 * C Runtime to print debug information. This
+	 * function will be accessed by console_init and
+	 * crash reporting.
+	 * In: r0 - console base address
+	 *     r1 - Uart clock in Hz
+	 *     r2 - Baud rate
+	 * Out: return 1 on success else 0 on error
+	 * Clobber list : r1, r2, r3, r4
+	 * -----------------------------------------------
+	 */
+func imx_crash_uart_init
+	/* Free up r1 as a scratch reg */
+	mov     r4, r0
+	mov     r0, r1
+
+	/* Reset UART via CR2 */
+	add     r1, r4, #IMX_UART_CR2_OFFSET
+	movs    r3, #0
+	str     r3, [r4, #IMX_UART_CR2_OFFSET]
+
+	/* Wait for reset complete */
+__wait_cr2_reset:
+	ldr     r3, [r1, #0]
+	ands    r3, #IMX_UART_CR2_SRST
+	beq     __wait_cr2_reset
+
+	/* Enable UART */
+	movs    r3, #IMX_UART_CR1_UARTEN
+	mov     r1, r2
+	str     r3, [r4, #IMX_UART_CR1_OFFSET]
+
+	/*
+	 * Ignore RTC/CTS - disable reset
+	 * Magic value #16423 =>
+	 * IMX_UART_CR2_IRTS | IMX_UART_CR2_WS | IMX_UART_CR2_TXEN | IMX_UART_CR2_RXEN | IMX_UART_CR2_SRST
+	 */
+	movw    r3, #16423
+	str     r3, [r4, #IMX_UART_CR2_OFFSET]
+
+	/*
+	 * No parity, autobaud detect-old, rxdmuxsel=1 (fixed i.mx7)
+	 * Magic value => #132
+	 * IMX_UART_CR3_ADNIMP | IMX_UART_CR3_RXDMUXSEL
+	 */
+	movs    r3, #132
+	str     r3, [r4, #IMX_UART_CR3_OFFSET]
+
+	/*
+	 * Set CTS FIFO trigger to 32 bytes bits 15:10
+	 * Magic value => #32768
+	 * FIFO trigger bitmask 100000
+	 * */
+	mov     r3, #32768
+	str     r3, [r4, #IMX_UART_CR4_OFFSET]
+
+	/*
+	 * TX/RX-thresh = 2 bytes, DCE (bit6 = 0), refclk @24MHz / 4
+	 * Magic value #2562
+	 * IMX_UART_FCR_TXTL(TX_RX_THRESH) | IMX_UART_FCR_RXTL(TX_RX_THRESH) | IMX_UART_FCR_RFDIV2
+	 */
+	#ifdef IMX_UART_DTE
+	movw    r3, #2626
+	#else
+	movw    r3, #2562
+	#endif
+	str     r3, [r4, #IMX_UART_FCR_OFFSET]
+
+	/* This BIR should be set to 0x0F prior to writing the BMR */
+	movs    r3, #15
+	str     r3, [r4, #IMX_UART_BIR_OFFSET]
+
+	/* Hard-code to 115200 @ 24 MHz */
+	movs	r0, #104
+	str     r0, [r4, #IMX_UART_BMR_OFFSET]
+
+	/* Indicate success */
+	movs    r0, #1
+	bx	lr
+endfunc imx_crash_uart_init
+
+	/* --------------------------------------------------------
+	 * int imx_crash_uart_putc(int c, uintptr_t base_addr)
+	 * Function to output a character over the console. It
+	 * returns the character printed on success or -1 on error.
+	 * In : r0 - character to be printed
+	 *      r1 - console base address
+	 * Out : return -1 on error else return character.
+	 * Clobber list : r2
+	 * --------------------------------------------------------
+	 */
+func imx_crash_uart_putc
+	/* Output specified character to UART shift-register */
+	str	r0, [r1, #IMX_UART_TXD_OFFSET]
+
+        /* Wait for transmit IMX_UART_STAT2_OFFSET.IMX_UART_STAT2_TXDC == 1 */
+__putc_spin_ready:
+	ldr	r2, [r1, #IMX_UART_STAT2_OFFSET]
+	ands	r2, #IMX_UART_STAT2_TXDC
+	beq	__putc_spin_ready
+
+        /* Transmit complete do we need to fixup \n to \n\r */
+	cmp	r0, #10
+	beq	__putc_fixup_lf
+
+	/* No fixup necessary - exit here */
+	movs	r0, #0
+	bx	lr
+
+	/* Fixup \n to \n\r */
+__putc_fixup_lf:
+	movs	r0, #13
+	b	imx_crash_uart_putc
+endfunc imx_crash_uart_putc

drivers/imx/uart/imx_uart.c

+/*
+ * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <stdint.h>
+#include <mmio.h>
+#include <platform_def.h>
+#include <imx_uart.h>
+
+/* TX/RX FIFO threshold */
+#define TX_RX_THRESH 2
+
+struct clk_div_factors {
+	uint32_t fcr_div;
+	uint32_t bmr_div;
+};
+
+static struct clk_div_factors clk_div[] = {
+	{
+		.fcr_div = IMX_UART_FCR_RFDIV1,
+		.bmr_div = 1,
+	},
+	{
+		.fcr_div = IMX_UART_FCR_RFDIV2,
+		.bmr_div = 2,
+	},
+	{
+		.fcr_div = IMX_UART_FCR_RFDIV3,
+		.bmr_div = 3,
+	},
+	{
+		.fcr_div = IMX_UART_FCR_RFDIV4,
+		.bmr_div = 4,
+	},
+	{
+		.fcr_div = IMX_UART_FCR_RFDIV5,
+		.bmr_div = 5,
+	},
+	{
+		.fcr_div = IMX_UART_FCR_RFDIV6,
+		.bmr_div = 6,
+	},
+	{
+		.fcr_div = IMX_UART_FCR_RFDIV7,
+		.bmr_div = 7,
+	},
+};
+
+static void write_reg(uintptr_t base, uint32_t offset, uint32_t val)
+{
+	mmio_write_32(base + offset, val);
+}
+
+static uint32_t read_reg(uintptr_t base, uint32_t offset)
+{
+	return mmio_read_32(base + offset);
+}
+
+int console_core_init(uintptr_t base_addr, unsigned int uart_clk,
+		      unsigned int baud_rate)
+{
+	uint32_t val;
+	uint8_t clk_idx = 1;
+
+	/* Reset UART */
+	write_reg(base_addr, IMX_UART_CR2_OFFSET, 0);
+	do {
+		val = read_reg(base_addr, IMX_UART_CR2_OFFSET);
+	} while (!(val & IMX_UART_CR2_SRST));
+
+	/* Enable UART */
+	write_reg(base_addr, IMX_UART_CR1_OFFSET, IMX_UART_CR1_UARTEN);
+
+	/* Ignore RTS, 8N1, enable tx/rx, disable reset */
+	val = (IMX_UART_CR2_IRTS | IMX_UART_CR2_WS | IMX_UART_CR2_TXEN |
+	       IMX_UART_CR2_RXEN | IMX_UART_CR2_SRST);
+	write_reg(base_addr, IMX_UART_CR2_OFFSET, val);
+
+	/* No parity, autobaud detect-old, rxdmuxsel=1 (fixed i.mx7) */
+	val = IMX_UART_CR3_ADNIMP | IMX_UART_CR3_RXDMUXSEL;
+	write_reg(base_addr, IMX_UART_CR3_OFFSET, val);
+
+	/* Set CTS FIFO trigger to 32 bytes bits 15:10 */
+	write_reg(base_addr, IMX_UART_CR4_OFFSET, 0x8000);
+
+	/* TX/RX-thresh = 2 bytes, DTE (bit6 = 0), refclk @24MHz / 4 */
+	val = IMX_UART_FCR_TXTL(TX_RX_THRESH) | IMX_UART_FCR_RXTL(TX_RX_THRESH) |
+	      clk_div[clk_idx].fcr_div;
+	#ifdef IMX_UART_DTE
+		/* Set DTE (bit6 = 1) */
+		val |= IMX_UART_FCR_DCEDTE;
+	#endif
+	write_reg(base_addr, IMX_UART_FCR_OFFSET, val);
+
+	/*
+	 * The equation for BAUD rate calculation is
+	 * RefClk = Supplied clock / FCR_DIVx
+	 *
+	 * BAUD  =    Refclk
+	 *         ------------
+	 *       16 x (UBMR + 1/ UBIR + 1)
+	 *
+	 * We write 0x0f into UBIR to remove the 16 mult
+	 * BAUD  =    6000000
+	 *         ------------
+	 *       16 x (UBMR + 1/ 15 + 1)
+	 */
+
+	write_reg(base_addr, IMX_UART_BIR_OFFSET, 0x0f);
+	val = ((uart_clk / clk_div[clk_idx].bmr_div) / baud_rate) - 1;
+	write_reg(base_addr, IMX_UART_BMR_OFFSET, val);
+
+	return 0;
+}
+
+/* --------------------------------------------------------
+ * int console_core_putc(int c, uintptr_t base_addr)
+ * Function to output a character over the console. It
+ * returns the character printed on success or -1 on error.
+ * In : r0 - character to be printed
+ *      r1 - console base address
+ * Out : return -1 on error else return character.
+ * Clobber list : r2
+ * --------------------------------------------------------
+ */
+int console_core_putc(int c, uintptr_t base_addr)
+{
+	uint32_t val;
+
+	if (c == '\n')
+		console_core_putc('\r', base_addr);
+
+	/* Write data */
+	write_reg(base_addr, IMX_UART_TXD_OFFSET, c);
+
+	/* Wait for transmit */
+	do {
+		val = read_reg(base_addr, IMX_UART_STAT2_OFFSET);
+	} while (!(val & IMX_UART_STAT2_TXDC));
+
+	return 0;
+}
+
+/*
+ * Function to get a character from the console.
+ * It returns the character grabbed on success
+ * or -1 on error.
+ * In : r0 - console base address
+ * Clobber list : r0, r1
+ * ---------------------------------------------
+ */
+int console_core_getc(uintptr_t base_addr)
+{
+	uint32_t val;
+
+	val = read_reg(base_addr, IMX_UART_TS_OFFSET);
+	if (val & IMX_UART_TS_RXEMPTY)
+		return -1;
+
+	val = read_reg(base_addr, IMX_UART_RXD_OFFSET);
+	return (int)(val & 0x000000FF);
+}
+
+/*
+ * Function to force a write of all buffered
+ * data that hasn't been output.
+ * In : r0 - console base address
+ * Out : return -1 on error else return 0.
+ * Clobber list : r0, r1
+ * ---------------------------------------------
+ */
+int console_core_flush(uintptr_t base_addr)
+{
+	return 0;
+}
+

drivers/imx/uart/imx_uart.h

+/*
+ * Copyright (c) Linaro 2018 Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef __IMX_CONSOLE_H__
+#define __IMX_CONSOLE_H__
+
+#define IMX_UART_RXD_OFFSET	0x00
+#define IMX_UART_RXD_CHARRDY	BIT(15)
+#define IMX_UART_RXD_ERR	BIT(14)
+#define IMX_UART_RXD_OVERRUN	BIT(13)
+#define IMX_UART_RXD_FRMERR	BIT(12)
+#define IMX_UART_RXD_BRK	BIT(11)
+#define IMX_UART_RXD_PRERR	BIT(10)
+
+#define IMX_UART_TXD_OFFSET	0x40
+
+#define IMX_UART_CR1_OFFSET	0x80
+#define IMX_UART_CR1_ADEN	BIT(15)
+#define IMX_UART_CR1_ADBR	BIT(14)
+#define IMX_UART_CR1_TRDYEN	BIT(13)
+#define IMX_UART_CR1_IDEN	BIT(12)
+#define IMX_UART_CR1_RRDYEN	BIT(9)
+#define IMX_UART_CR1_RXDMAEN	BIT(8)
+#define IMX_UART_CR1_IREN	BIT(7)
+#define IMX_UART_CR1_TXMPTYEN	BIT(6)
+#define IMX_UART_CR1_RTSDEN	BIT(5)
+#define IMX_UART_CR1_SNDBRK	BIT(4)
+#define IMX_UART_CR1_TXDMAEN	BIT(3)
+#define IMX_UART_CR1_ATDMAEN	BIT(2)
+#define IMX_UART_CR1_DOZE	BIT(1)
+#define IMX_UART_CR1_UARTEN	BIT(0)
+
+#define IMX_UART_CR2_OFFSET	0x84
+#define IMX_UART_CR2_ESCI	BIT(15)
+#define IMX_UART_CR2_IRTS	BIT(14)
+#define IMX_UART_CR2_CTSC	BIT(13)
+#define IMX_UART_CR2_CTS	BIT(12)
+#define IMX_UART_CR2_ESCEN	BIT(11)
+#define IMX_UART_CR2_PREN	BIT(8)
+#define IMX_UART_CR2_PROE	BIT(7)
+#define IMX_UART_CR2_STPB	BIT(6)
+#define IMX_UART_CR2_WS		BIT(5)
+#define IMX_UART_CR2_RTSEN	BIT(4)
+#define IMX_UART_CR2_ATEN	BIT(3)
+#define IMX_UART_CR2_TXEN	BIT(2)
+#define IMX_UART_CR2_RXEN	BIT(1)
+#define IMX_UART_CR2_SRST	BIT(0)
+
+#define IMX_UART_CR3_OFFSET	0x88
+#define IMX_UART_CR3_DTREN	BIT(13)
+#define IMX_UART_CR3_PARERREN	BIT(12)
+#define IMX_UART_CR3_FARERREN	BIT(11)
+#define IMX_UART_CR3_DSD	BIT(10)
+#define IMX_UART_CR3_DCD	BIT(9)
+#define IMX_UART_CR3_RI		BIT(8)
+#define IMX_UART_CR3_ADNIMP	BIT(7)
+#define IMX_UART_CR3_RXDSEN	BIT(6)
+#define IMX_UART_CR3_AIRINTEN	BIT(5)
+#define IMX_UART_CR3_AWAKEN	BIT(4)
+#define IMX_UART_CR3_DTRDEN	BIT(3)
+#define IMX_UART_CR3_RXDMUXSEL	BIT(2)
+#define IMX_UART_CR3_INVT	BIT(1)
+#define IMX_UART_CR3_ACIEN	BIT(0)
+
+#define IMX_UART_CR4_OFFSET	0x8c
+#define IMX_UART_CR4_INVR	BIT(9)
+#define IMX_UART_CR4_ENIRI	BIT(8)
+#define IMX_UART_CR4_WKEN	BIT(7)
+#define IMX_UART_CR4_IDDMAEN	BIT(6)
+#define IMX_UART_CR4_IRSC	BIT(5)
+#define IMX_UART_CR4_LPBYP	BIT(4)
+#define IMX_UART_CR4_TCEN	BIT(3)
+#define IMX_UART_CR4_BKEN	BIT(2)
+#define IMX_UART_CR4_OREN	BIT(1)
+#define IMX_UART_CR4_DREN	BIT(0)
+
+#define IMX_UART_FCR_OFFSET	0x90
+#define IMX_UART_FCR_TXTL_MASK	(BIT(15) | BIT(14) | BIT(13) | BIT(12) |\
+				 BIT(11) | BIT(10))
+#define IMX_UART_FCR_TXTL(x)	((x) << 10)
+#define IMX_UART_FCR_RFDIV_MASK	(BIT(9) | BIT(8) | BIT(7))
+#define IMX_UART_FCR_RFDIV7	(BIT(9) | BIT(8))
+#define IMX_UART_FCR_RFDIV1	(BIT(9) | BIT(7))
+#define IMX_UART_FCR_RFDIV2	BIT(9)
+#define IMX_UART_FCR_RFDIV3	(BIT(8) | BIT(7))
+#define IMX_UART_FCR_RFDIV4	BIT(8)
+#define IMX_UART_FCR_RFDIV5	BIT(7)
+#define IMX_UART_FCR_RFDIV6	0
+#define IMX_UART_FCR_DCEDTE	BIT(6)
+#define IMX_UART_FCR_RXTL_MASK	(BIT(5) | BIT(4) | BIT(3) | BIT(2) |\
+				 BIT(1) | BIT(0))
+#define IMX_UART_FCR_RXTL(x)	x
+
+#define IMX_UART_STAT1_OFFSET	0x94
+#define IMX_UART_STAT1_PARITYERR	BIT(15)
+#define IMX_UART_STAT1_RTSS	BIT(14)
+#define IMX_UART_STAT1_TRDY	BIT(13)
+#define IMX_UART_STAT1_RTSD	BIT(12)
+#define IMX_UART_STAT1_ESCF	BIT(11)
+#define IMX_UART_STAT1_FRAMEERR	BIT(10)
+#define IMX_UART_STAT1_RRDY	BIT(9)
+#define IMX_UART_STAT1_AGTIM	BIT(8)
+#define IMX_UART_STAT1_DTRD	BIT(7)
+#define IMX_UART_STAT1_RXDS	BIT(6)
+#define IMX_UART_STAT1_AIRINT	BIT(5)
+#define IMX_UART_STAT1_AWAKE	BIT(4)
+#define IMX_UART_STAT1_SAD	BIT(3)
+
+#define IMX_UART_STAT2_OFFSET	0x98
+#define IMX_UART_STAT2_ADET	BIT(15)
+#define IMX_UART_STAT2_TXFE	BIT(14)
+#define IMX_UART_STAT2_DTRF	BIT(13)
+#define IMX_UART_STAT2_IDLE	BIT(12)
+#define IMX_UART_STAT2_ACST	BIT(11)
+#define IMX_UART_STAT2_RIDELT	BIT(10)
+#define IMX_UART_STAT2_RIIN	BIT(9)
+#define IMX_UART_STAT2_IRINT	BIT(8)
+#define IMX_UART_STAT2_WAKE	BIT(7)
+#define IMX_UART_STAT2_DCDDELT	BIT(6)
+#define IMX_UART_STAT2_DCDIN	BIT(5)
+#define IMX_UART_STAT2_RTSF	BIT(4)
+#define IMX_UART_STAT2_TXDC	BIT(3)
+#define IMX_UART_STAT2_BRCD	BIT(2)
+#define IMX_UART_STAT2_ORE	BIT(1)
+#define IMX_UART_STAT2_RCR	BIT(0)
+
+#define IMX_UART_ESC_OFFSET	0x9c
+
+#define IMX_UART_TIM_OFFSET	0xa0
+
+#define IMX_UART_BIR_OFFSET	0xa4
+
+#define IMX_UART_BMR_OFFSET	0xa8
+
+#define IMX_UART_BRC_OFFSET	0xac
+
+#define IMX_UART_ONEMS_OFFSET	0xb0
+
+#define IMX_UART_TS_OFFSET	0xb4
+#define IMX_UART_TS_FRCPERR	BIT(13)
+#define IMX_UART_TS_LOOP	BIT(12)
+#define IMX_UART_TS_DBGEN	BIT(11)
+#define IMX_UART_TS_LOOPIR	BIT(10)
+#define IMX_UART_TS_RXDBG	BIT(9)
+#define IMX_UART_TS_TXEMPTY	BIT(6)
+#define IMX_UART_TS_RXEMPTY	BIT(5)
+#define IMX_UART_TS_TXFULL	BIT(4)
+#define IMX_UART_TS_RXFULL	BIT(3)
+#define IMX_UART_TS_SOFTRST	BIT(0)
+
+#endif /* __IMX_UART_H__ */

drivers/imx/usdhc/imx_usdhc.c

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <arch.h>
+#include <arch_helpers.h>
+#include <assert.h>
+#include <debug.h>
+#include <delay_timer.h>
+#include <imx_usdhc.h>
+#include <mmc.h>
+#include <errno.h>
+#include <mmio.h>
+#include <string.h>
+
+static void imx_usdhc_initialize(void);
+static int imx_usdhc_send_cmd(struct mmc_cmd *cmd);
+static int imx_usdhc_set_ios(unsigned int clk, unsigned int width);
+static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size);
+static int imx_usdhc_read(int lba, uintptr_t buf, size_t size);
+static int imx_usdhc_write(int lba, uintptr_t buf, size_t size);
+
+static const struct mmc_ops imx_usdhc_ops = {
+	.init		= imx_usdhc_initialize,
+	.send_cmd	= imx_usdhc_send_cmd,
+	.set_ios	= imx_usdhc_set_ios,
+	.prepare	= imx_usdhc_prepare,
+	.read		= imx_usdhc_read,
+	.write		= imx_usdhc_write,
+};
+
+static imx_usdhc_params_t imx_usdhc_params;
+
+#define IMX7_MMC_SRC_CLK_RATE (200 * 1000 * 1000)
+static void imx_usdhc_set_clk(int clk)
+{
+	int div = 1;
+	int pre_div = 1;
+	unsigned int sdhc_clk = IMX7_MMC_SRC_CLK_RATE;
+	uintptr_t reg_base = imx_usdhc_params.reg_base;
+
+	assert(clk > 0);
+
+	while (sdhc_clk / (16 * pre_div) > clk && pre_div < 256)
+		pre_div *= 2;
+
+	while (sdhc_clk / div > clk && div < 16)
+		div++;
+
+	pre_div >>= 1;
+	div -= 1;
+	clk = (pre_div << 8) | (div << 4);
+
+	mmio_clrbits32(reg_base + VENDSPEC, VENDSPEC_CARD_CLKEN);
+	mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_CLOCK_MASK, clk);
+	udelay(10000);
+
+	mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_PER_CLKEN | VENDSPEC_CARD_CLKEN);
+}
+
+static void imx_usdhc_initialize(void)
+{
+	unsigned int timeout = 10000;
+	uintptr_t reg_base = imx_usdhc_params.reg_base;
+
+	assert((imx_usdhc_params.reg_base & MMC_BLOCK_MASK) == 0);
+
+	/* reset the controller */
+	mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTA);
+
+	/* wait for reset done */
+	while ((mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTA)) {
+		if (!timeout)
+			ERROR("IMX MMC reset timeout.\n");
+		timeout--;
+	}
+
+	mmio_write_32(reg_base + MMCBOOT, 0);
+	mmio_write_32(reg_base + MIXCTRL, 0);
+	mmio_write_32(reg_base + CLKTUNECTRLSTS, 0);
+
+	mmio_write_32(reg_base + VENDSPEC, VENDSPEC_INIT);
+	mmio_write_32(reg_base + DLLCTRL, 0);
+	mmio_setbits32(reg_base + VENDSPEC, VENDSPEC_IPG_CLKEN | VENDSPEC_PER_CLKEN);
+
+	/* Set the initial boot clock rate */
+	imx_usdhc_set_clk(MMC_BOOT_CLK_RATE);
+	udelay(100);
+
+	/* Clear read/write ready status */
+	mmio_clrbits32(reg_base + INTSTATEN, INTSTATEN_BRR | INTSTATEN_BWR);
+
+	/* configure as little endian */
+	mmio_write_32(reg_base + PROTCTRL, PROTCTRL_LE);
+
+	/* Set timeout to the maximum value */
+	mmio_clrsetbits32(reg_base + SYSCTRL, SYSCTRL_TIMEOUT_MASK,
+			  SYSCTRL_TIMEOUT(15));
+
+	/* set wartermark level as 16 for safe for MMC */
+	mmio_clrsetbits32(reg_base + WATERMARKLEV, WMKLV_MASK, 16 | (16 << 16));
+}
+
+#define FSL_CMD_RETRIES	1000
+
+static int imx_usdhc_send_cmd(struct mmc_cmd *cmd)
+{
+	uintptr_t reg_base = imx_usdhc_params.reg_base;
+	unsigned int xfertype = 0, mixctl = 0, multiple = 0, data = 0, err = 0;
+	unsigned int state, flags = INTSTATEN_CC | INTSTATEN_CTOE;
+	unsigned int cmd_retries = 0;
+
+	assert(cmd);
+
+	/* clear all irq status */
+	mmio_write_32(reg_base + INTSTAT, 0xffffffff);
+
+	/* Wait for the bus to be idle */
+	do {
+		state = mmio_read_32(reg_base + PSTATE);
+	} while (state & (PSTATE_CDIHB | PSTATE_CIHB));
+
+	while (mmio_read_32(reg_base + PSTATE) & PSTATE_DLA)
+		;
+
+	mmio_write_32(reg_base + INTSIGEN, 0);
+	udelay(1000);
+
+	switch (cmd->cmd_idx) {
+	case MMC_CMD(12):
+		xfertype |= XFERTYPE_CMDTYP_ABORT;
+		break;
+	case MMC_CMD(18):
+		multiple = 1;
+		/* fall thru for read op */
+	case MMC_CMD(17):
+	case MMC_CMD(8):
+		mixctl |= MIXCTRL_DTDSEL;
+		data = 1;
+		break;
+	case MMC_CMD(25):
+		multiple = 1;
+		/* fall thru for data op flag */
+	case MMC_CMD(24):
+		data = 1;
+		break;
+	default:
+		break;
+	}
+
+	if (multiple) {
+		mixctl |= MIXCTRL_MSBSEL;
+		mixctl |= MIXCTRL_BCEN;
+	}
+
+	if (data) {
+		xfertype |= XFERTYPE_DPSEL;
+		mixctl |= MIXCTRL_DMAEN;
+	}
+
+	if (cmd->resp_type & MMC_RSP_48)
+		xfertype |= XFERTYPE_RSPTYP_48;
+	else if (cmd->resp_type & MMC_RSP_136)
+		xfertype |= XFERTYPE_RSPTYP_136;
+	else if (cmd->resp_type & MMC_RSP_BUSY)
+		xfertype |= XFERTYPE_RSPTYP_48_BUSY;
+
+	if (cmd->resp_type & MMC_RSP_CMD_IDX)
+		xfertype |= XFERTYPE_CICEN;
+
+	if (cmd->resp_type & MMC_RSP_CRC)
+		xfertype |= XFERTYPE_CCCEN;
+
+	xfertype |= XFERTYPE_CMD(cmd->cmd_idx);
+
+	/* Send the command */
+	mmio_write_32(reg_base + CMDARG, cmd->cmd_arg);
+	mmio_clrsetbits32(reg_base + MIXCTRL, MIXCTRL_DATMASK, mixctl);
+	mmio_write_32(reg_base + XFERTYPE, xfertype);
+
+	/* Wait for the command done */
+	do {
+		state = mmio_read_32(reg_base + INTSTAT);
+		if (cmd_retries)
+			udelay(1);
+	} while ((!(state & flags)) && ++cmd_retries < FSL_CMD_RETRIES);
+
+	if ((state & (INTSTATEN_CTOE | CMD_ERR)) || cmd_retries == FSL_CMD_RETRIES) {
+		if (cmd_retries == FSL_CMD_RETRIES)
+			err = -ETIMEDOUT;
+		else
+			err = -EIO;
+		ERROR("imx_usdhc mmc cmd %d state 0x%x errno=%d\n",
+		      cmd->cmd_idx, state, err);
+		goto out;
+	}
+
+	/* Copy the response to the response buffer */
+	if (cmd->resp_type & MMC_RSP_136) {
+		unsigned int cmdrsp3, cmdrsp2, cmdrsp1, cmdrsp0;
+
+		cmdrsp3 = mmio_read_32(reg_base + CMDRSP3);
+		cmdrsp2 = mmio_read_32(reg_base + CMDRSP2);
+		cmdrsp1 = mmio_read_32(reg_base + CMDRSP1);
+		cmdrsp0 = mmio_read_32(reg_base + CMDRSP0);
+		cmd->resp_data[3] = (cmdrsp3 << 8) | (cmdrsp2 >> 24);
+		cmd->resp_data[2] = (cmdrsp2 << 8) | (cmdrsp1 >> 24);
+		cmd->resp_data[1] = (cmdrsp1 << 8) | (cmdrsp0 >> 24);
+		cmd->resp_data[0] = (cmdrsp0 << 8);
+	} else {
+		cmd->resp_data[0] = mmio_read_32(reg_base + CMDRSP0);
+	}
+
+	/* Wait until all of the blocks are transferred */
+	if (data) {
+		flags = DATA_COMPLETE;
+		do {
+			state = mmio_read_32(reg_base + INTSTAT);
+
+			if (state & (INTSTATEN_DTOE | DATA_ERR)) {
+				err = -EIO;
+				ERROR("imx_usdhc mmc data state 0x%x\n", state);
+				goto out;
+			}
+		} while ((state & flags) != flags);
+	}
+
+out:
+	/* Reset CMD and DATA on error */
+	if (err) {
+		mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTC);
+		while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTC)
+			;
+
+		if (data) {
+			mmio_setbits32(reg_base + SYSCTRL, SYSCTRL_RSTD);
+			while (mmio_read_32(reg_base + SYSCTRL) & SYSCTRL_RSTD)
+				;
+		}
+	}
+
+	/* clear all irq status */
+	mmio_write_32(reg_base + INTSTAT, 0xffffffff);
+
+	return err;
+}
+
+static int imx_usdhc_set_ios(unsigned int clk, unsigned int width)
+{
+	uintptr_t reg_base = imx_usdhc_params.reg_base;
+
+	imx_usdhc_set_clk(clk);
+
+	if (width == MMC_BUS_WIDTH_4)
+		mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK,
+				  PROTCTRL_WIDTH_4);
+	else if (width == MMC_BUS_WIDTH_8)
+		mmio_clrsetbits32(reg_base + PROTCTRL, PROTCTRL_WIDTH_MASK,
+				  PROTCTRL_WIDTH_8);
+
+	return 0;
+}
+
+static int imx_usdhc_prepare(int lba, uintptr_t buf, size_t size)
+{
+	uintptr_t reg_base = imx_usdhc_params.reg_base;
+
+	mmio_write_32(reg_base + DSADDR, buf);
+	mmio_write_32(reg_base + BLKATT,
+		      (size / MMC_BLOCK_SIZE) << 16 | MMC_BLOCK_SIZE);
+
+	return 0;
+}
+
+static int imx_usdhc_read(int lba, uintptr_t buf, size_t size)
+{
+	return 0;
+}
+
+static int imx_usdhc_write(int lba, uintptr_t buf, size_t size)
+{
+	return 0;
+}
+
+void imx_usdhc_init(imx_usdhc_params_t *params,
+		    struct mmc_device_info *mmc_dev_info)
+{
+	assert((params != 0) &&
+	       ((params->reg_base & MMC_BLOCK_MASK) == 0) &&
+	       (params->clk_rate > 0) &&
+	       ((params->bus_width == MMC_BUS_WIDTH_1) ||
+		(params->bus_width == MMC_BUS_WIDTH_4) ||
+		(params->bus_width == MMC_BUS_WIDTH_8)));
+
+	memcpy(&imx_usdhc_params, params, sizeof(imx_usdhc_params_t));
+	mmc_init(&imx_usdhc_ops, params->clk_rate, params->bus_width,
+		 params->flags, mmc_dev_info);
+}

drivers/imx/usdhc/imx_usdhc.h

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __IMX_USDHC_H__
+#define	__IMX_USDHC_H__
+
+#include <mmc.h>
+
+typedef struct imx_usdhc_params {
+	uintptr_t	reg_base;
+	int		clk_rate;
+	int		bus_width;
+	unsigned int	flags;
+} imx_usdhc_params_t;
+
+void imx_usdhc_init(imx_usdhc_params_t *params,
+		    struct mmc_device_info *mmc_dev_info);
+
+/* iMX MMC registers definition */
+#define DSADDR			0x000
+#define BLKATT			0x004
+#define CMDARG			0x008
+#define CMDRSP0			0x010
+#define CMDRSP1			0x014
+#define CMDRSP2			0x018
+#define CMDRSP3			0x01c
+
+#define XFERTYPE		0x00c
+#define XFERTYPE_CMD(x)		(((x) & 0x3f) << 24)
+#define XFERTYPE_CMDTYP_ABORT	(3 << 22)
+#define XFERTYPE_DPSEL		BIT(21)
+#define XFERTYPE_CICEN		BIT(20)
+#define XFERTYPE_CCCEN		BIT(19)
+#define XFERTYPE_RSPTYP_136	BIT(16)
+#define XFERTYPE_RSPTYP_48	BIT(17)
+#define XFERTYPE_RSPTYP_48_BUSY	(BIT(16) | BIT(17))
+
+#define PSTATE			0x024
+#define PSTATE_DAT0		BIT(24)
+#define PSTATE_DLA		BIT(2)
+#define PSTATE_CDIHB		BIT(1)
+#define PSTATE_CIHB		BIT(0)
+
+#define PROTCTRL		0x028
+#define PROTCTRL_LE		BIT(5)
+#define PROTCTRL_WIDTH_4	BIT(1)
+#define PROTCTRL_WIDTH_8	BIT(2)
+#define PROTCTRL_WIDTH_MASK	0x6
+
+#define SYSCTRL			0x02c
+#define SYSCTRL_RSTD		BIT(26)
+#define SYSCTRL_RSTC		BIT(25)
+#define SYSCTRL_RSTA		BIT(24)
+#define SYSCTRL_CLOCK_MASK	0x0000fff0
+#define SYSCTRL_TIMEOUT_MASK	0x000f0000
+#define SYSCTRL_TIMEOUT(x)	((0xf & (x)) << 16)
+
+#define INTSTAT			0x030
+#define INTSTAT_DMAE		BIT(28)
+#define INTSTAT_DEBE		BIT(22)
+#define INTSTAT_DCE		BIT(21)
+#define INTSTAT_DTOE		BIT(20)
+#define INTSTAT_CIE		BIT(19)
+#define INTSTAT_CEBE		BIT(18)
+#define INTSTAT_CCE		BIT(17)
+#define INTSTAT_DINT		BIT(3)
+#define INTSTAT_BGE		BIT(2)
+#define INTSTAT_TC		BIT(1)
+#define INTSTAT_CC		BIT(0)
+#define CMD_ERR			(INTSTAT_CIE | INTSTAT_CEBE | INTSTAT_CCE)
+#define DATA_ERR		(INTSTAT_DMAE | INTSTAT_DEBE | INTSTAT_DCE | \
+				 INTSTAT_DTOE)
+#define DATA_COMPLETE		(INTSTAT_DINT | INTSTAT_TC)
+
+#define INTSTATEN		0x034
+#define INTSTATEN_DEBE		BIT(22)
+#define INTSTATEN_DCE		BIT(21)
+#define INTSTATEN_DTOE		BIT(20)
+#define INTSTATEN_CIE		BIT(19)
+#define INTSTATEN_CEBE		BIT(18)
+#define INTSTATEN_CCE		BIT(17)
+#define INTSTATEN_CTOE		BIT(16)
+#define INTSTATEN_CINT		BIT(8)
+#define INTSTATEN_BRR		BIT(5)
+#define INTSTATEN_BWR		BIT(4)
+#define INTSTATEN_DINT		BIT(3)
+#define INTSTATEN_TC		BIT(1)
+#define INTSTATEN_CC		BIT(0)
+#define EMMC_INTSTATEN_BITS	(INTSTATEN_CC | INTSTATEN_TC | INTSTATEN_DINT | \
+				 INTSTATEN_BWR | INTSTATEN_BRR | INTSTATEN_CINT | \
+				 INTSTATEN_CTOE | INTSTATEN_CCE | INTSTATEN_CEBE | \
+				 INTSTATEN_CIE | INTSTATEN_DTOE | INTSTATEN_DCE | \
+				 INTSTATEN_DEBE)
+
+#define INTSIGEN		0x038
+
+#define WATERMARKLEV		0x044
+#define WMKLV_RD_MASK		0xff
+#define WMKLV_WR_MASK		0x00ff0000
+#define WMKLV_MASK		(WMKLV_RD_MASK | WMKLV_WR_MASK)
+
+#define MIXCTRL			0x048
+#define MIXCTRL_MSBSEL		BIT(5)
+#define MIXCTRL_DTDSEL		BIT(4)
+#define MIXCTRL_DDREN		BIT(3)
+#define MIXCTRL_AC12EN		BIT(2)
+#define MIXCTRL_BCEN		BIT(1)
+#define MIXCTRL_DMAEN		BIT(0)
+#define MIXCTRL_DATMASK		0x7f
+
+#define DLLCTRL			0x060
+
+#define CLKTUNECTRLSTS		0x068
+
+#define VENDSPEC		0x0c0
+#define VENDSPEC_RSRV1		BIT(29)
+#define VENDSPEC_CARD_CLKEN	BIT(14)
+#define VENDSPEC_PER_CLKEN	BIT(13)
+#define VENDSPEC_AHB_CLKEN	BIT(12)
+#define VENDSPEC_IPG_CLKEN	BIT(11)
+#define VENDSPEC_AC12_CHKBUSY	BIT(3)
+#define VENDSPEC_EXTDMA		BIT(0)
+#define VENDSPEC_INIT		(VENDSPEC_RSRV1	| VENDSPEC_CARD_CLKEN | \
+				 VENDSPEC_PER_CLKEN | VENDSPEC_AHB_CLKEN | \
+				 VENDSPEC_IPG_CLKEN | VENDSPEC_AC12_CHKBUSY | \
+				 VENDSPEC_EXTDMA)
+
+#define MMCBOOT			0x0c4
+
+#define mmio_clrsetbits32(addr, clear, set)	mmio_write_32(addr, (mmio_read_32(addr) & ~(clear)) | (set))
+#define mmio_clrbits32(addr, clear)		mmio_write_32(addr, mmio_read_32(addr) & ~(clear))
+#define mmio_setbits32(addr, set)		mmio_write_32(addr, mmio_read_32(addr) | (set))
+
+#endif  /* __IMX_USDHC_H__ */

drivers/mmc/mmc.c

@@ -109,7 +109,7 @@ static int mmc_set_ext_csd(unsigned int ext_cmd, unsigned int value)
 	ret = mmc_send_cmd(MMC_CMD(6),
 			   EXTCSD_WRITE_BYTES | EXTCSD_CMD(ext_cmd) |
 			   EXTCSD_VALUE(value) | EXTCSD_CMD_SET_NORMAL,
-			   0, NULL);
+			   MMC_RESPONSE_R1B, NULL);
 	if (ret != 0) {
 		return ret;
 	}
@@ -333,7 +333,7 @@ static int sd_send_op_cond(void)
 		}
 
 		/* ACMD41: SD_SEND_OP_COND */
-		ret = mmc_send_cmd(MMC_ACMD(41), OCR_HCS, MMC_RESPONSE_R(3),
+		ret = mmc_send_cmd(MMC_ACMD(41), OCR_HCS, MMC_RESPONSE_R3,
 				   &resp_data[0]);
 		if (ret != 0) {
 			return ret;
@@ -384,7 +384,7 @@ static int mmc_send_op_cond(void)
 	for (n = 0; n < SEND_OP_COND_MAX_RETRIES; n++) {
 		ret = mmc_send_cmd(MMC_CMD(1), OCR_SECTOR_MODE |
 				   OCR_VDD_MIN_2V7 | OCR_VDD_MIN_1V7,
-				   MMC_RESPONSE_R(3), &resp_data[0]);
+				   MMC_RESPONSE_R3, &resp_data[0]);
 		if (ret != 0) {
 			return ret;
 		}
@@ -539,7 +539,7 @@ size_t mmc_read_blocks(int lba, uintptr_t buf, size_t size)
 	} while ((ret != MMC_STATE_TRAN) && (ret != MMC_STATE_DATA));
 
 	if (!is_cmd23_enabled() && (size > MMC_BLOCK_SIZE)) {
-		ret = mmc_send_cmd(MMC_CMD(12), 0, 0, NULL);
+		ret = mmc_send_cmd(MMC_CMD(12), 0, MMC_RESPONSE_R1B, NULL);
 		if (ret != 0) {
 			return 0;
 		}
@@ -606,7 +606,7 @@ size_t mmc_write_blocks(int lba, const uintptr_t buf, size_t size)
 	} while ((ret != MMC_STATE_TRAN) && (ret != MMC_STATE_RCV));
 
 	if (!is_cmd23_enabled() && (size > MMC_BLOCK_SIZE)) {
-		ret = mmc_send_cmd(MMC_CMD(12), 0, 0, NULL);
+		ret = mmc_send_cmd(MMC_CMD(12), 0, MMC_RESPONSE_R1B, NULL);
 		if (ret != 0) {
 			return 0;
 		}

drivers/synopsys/emmc/dw_mmc.c

@@ -259,11 +259,14 @@ static int dw_send_cmd(struct mmc_cmd *cmd)
 	switch (cmd->resp_type) {
 	case 0:
 		break;
-	case MMC_RESPONSE_R(2):
+	case MMC_RESPONSE_R2:
 		op |= CMD_RESP_EXPECT | CMD_CHECK_RESP_CRC |
 		      CMD_RESP_LEN;
 		break;
-	case MMC_RESPONSE_R(3):
+	case MMC_RESPONSE_R1:
+	case MMC_RESPONSE_R1B:
+	case MMC_RESPONSE_R3:
+	case MMC_RESPONSE_R5:
 		op |= CMD_RESP_EXPECT;
 		break;
 	default:

include/drivers/mmc.h

@@ -36,6 +36,20 @@
 #define OCR_VDD_MIN_2V0			GENMASK(14, 8)
 #define OCR_VDD_MIN_1V7			BIT(7)
 
+#define MMC_RSP_48			BIT(0)
+#define MMC_RSP_136			BIT(1)		/* 136 bit response */
+#define MMC_RSP_CRC			BIT(2)		/* expect valid crc */
+#define MMC_RSP_CMD_IDX			BIT(3)		/* response contains cmd idx */
+#define MMC_RSP_BUSY			BIT(4)		/* device may be busy */
+
+/* JEDEC 4.51 chapter 6.12 */
+#define MMC_RESPONSE_R1			(MMC_RSP_48 | MMC_RSP_CMD_IDX | MMC_RSP_CRC)
+#define MMC_RESPONSE_R1B		(MMC_RESPONSE_R1 | MMC_RSP_BUSY)
+#define MMC_RESPONSE_R2			(MMC_RSP_136 | MMC_RSP_CRC)
+#define MMC_RESPONSE_R3			(MMC_RSP_48)
+#define MMC_RESPONSE_R4			(MMC_RSP_48)
+#define MMC_RESPONSE_R5			(MMC_RSP_48 | MMC_RSP_CRC)
+
 #define MMC_RESPONSE_R(_x)		U(_x)
 
 /* Value randomly chosen for eMMC RCA, it should be > 1 */

maintainers.rst

@@ -97,6 +97,19 @@ NXP QorIQ Layerscape platform ports
 :F: docs/plat/ls1043a.rst
 :F: plat/layerscape/
 
+NXP i.MX 7 WaRP7 platform port and SoC drivers
+----------------------------------------------
+:M: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
+:G: `bryanodonoghue`_
+:M: Jun Nie <jun.nie@linaro.org>
+:G: `niej`_
+:F: docs/plat/warp7.rst
+:F: plat/imx/common/
+:F: plat/imx/imx7/
+:F: drivers/imx/timer/
+:F: drivers/imx/uart/
+:F: drivers/imx/usdhc/
+
 NXP i.MX 8 platform port
 ------------------------
 :M: Anson Huang <Anson.Huang@nxp.com>
@@ -185,6 +198,7 @@ Xilinx platform port
 .. _Andre-ARM: https://github.com/Andre-ARM
 .. _Anson-Huang: https://github.com/Anson-Huang
 .. _antonio-nino-diaz-arm: https://github.com/antonio-nino-diaz-arm
+.. _bryanodonoghue: https://github.com/bryanodonoghue
 .. _b49020: https://github.com/b49020
 .. _danh-arm: https://github.com/danh-arm
 .. _dp-arm: https://github.com/dp-arm
@@ -192,6 +206,7 @@ Xilinx platform port
 .. _glneo: https://github.com/glneo
 .. _hzhuang1: https://github.com/hzhuang1
 .. _jenswi-linaro: https://github.com/jenswi-linaro
+.. _niej: https://github.com/niej
 .. _kostapr: https://github.com/kostapr
 .. _masahir0y: https://github.com/masahir0y
 .. _mtk09422: https://github.com/mtk09422

plat/imx/common/imx7_clock.c

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <imx_regs.h>
+#include <imx_clock.h>
+
+static void imx7_clock_uart_init(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < MXC_MAX_UART_NUM; i++)
+		imx_clock_disable_uart(i);
+}
+
+static void imx7_clock_wdog_init(void)
+{
+	unsigned int i;
+
+	for (i = 0; i < MXC_MAX_WDOG_NUM; i++)
+		imx_clock_disable_wdog(i);
+}
+
+static void imx7_clock_usb_init(void)
+{
+	/* Disable the clock root */
+	imx_clock_target_clr(CCM_TRT_ID_USB_HSIC_CLK_ROOT, 0xFFFFFFFF);
+}
+
+void imx_clock_init(void)
+{
+	/*
+	 * The BootROM hands off to the next stage with the internal 24 MHz XTAL
+	 * crystal already clocking the main PLL, which is very handy.
+	 * Here we should enable whichever peripherals are required for ATF and
+	 * OPTEE.
+	 *
+	 * Subsequent stages in the boot process such as u-boot and Linux
+	 * already have a significant and mature code-base around clocks, so our
+	 * objective should be to enable what we need for ATF/OPTEE without
+	 * breaking any existing upstream code in Linux and u-boot.
+	 */
+
+	/* Initialize UART clocks */
+	imx7_clock_uart_init();
+
+	/* Watchdog clocks */
+
+	imx7_clock_wdog_init();
+
+	/* USB clocks */
+	imx7_clock_usb_init();
+
+}

plat/imx/common/imx_aips.c

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <utils_def.h>
+#include <imx_aips.h>
+#include <imx_regs.h>
+
+static void imx_aips_set_default_access(struct aipstz_regs *aips_regs)
+{
+	int i;
+	uintptr_t addr;
+
+	/*
+	 * See section 4.7.7.1 AIPSTZ_MPR field descriptions
+	 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
+	 * 0111 ->
+	 *	0: Write Access from master not buffered
+	 *	1: Master is trusted for read access
+	 *	1: Master is trsuted for write access
+	 *	1: Access from master is not forced to user mode
+	 */
+	addr = (uintptr_t)&aips_regs->aipstz_mpr;
+	mmio_write_32(addr, 0x77777777);
+
+	/*
+	 * Helpfully the OPACR registers have the logical inversion of the above
+	 * See section 4.7.7.1 AIPSTZ_MPR field descriptions
+	 * i.MX 7Solo Applications Processor Reference Manual, Rev. 0.1, 08/2016
+	 * 0000 ->
+	 *	0: Write Access to the peripheral is not buffered by AIPSTZ
+	 *	0: The peripheral does not require supervisor priv to access
+	 *	0: Master is trsuted for write access
+	 *	0: Access from master is not forced to user mode
+	 */
+	for (i = 0; i < AIPSTZ_OAPCR_COUNT; i++) {
+		addr = (uintptr_t)&aips_regs->aipstz_opacr[i];
+		mmio_write_32(addr, 0x00000000);
+	}
+}
+
+void imx_aips_init(void)
+{
+	int i;
+	struct aipstz_regs *aips_regs[] = {
+		(struct aipstz_regs *)(AIPS1_BASE + AIPSTZ_CONFIG_OFFSET),
+		(struct aipstz_regs *)(AIPS2_BASE + AIPSTZ_CONFIG_OFFSET),
+		(struct aipstz_regs *)(AIPS3_BASE + AIPSTZ_CONFIG_OFFSET),
+	};
+
+	for (i = 0; i < ARRAY_SIZE(aips_regs); i++)
+		imx_aips_set_default_access(aips_regs[i]);
+}

plat/imx/common/imx_caam.c

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stdint.h>
+#include <mmio.h>
+#include <imx_caam.h>
+
+void imx_caam_init(void)
+{
+	struct caam_ctrl *caam = (struct caam_ctrl *)CAAM_AIPS_BASE;
+	uint32_t reg;
+	int i;
+
+	for (i = 0; i < CAAM_NUM_JOB_RINGS; i++) {
+		reg = mmio_read_32((uintptr_t)&caam->jr[i].jrmidr_ms);
+		reg |= JROWN_NS | JROWN_MID;
+		mmio_write_32((uintptr_t)&caam->jr[i].jrmidr_ms, reg);
+	}
+}

plat/imx/common/imx_clock.c

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <arch.h>
+#include <mmio.h>
+#include <stdint.h>
+#include <stdbool.h>
+#include <imx_regs.h>
+#include <imx_clock.h>
+
+void imx_clock_target_set(unsigned int id, uint32_t val)
+{
+	struct ccm *ccm = ((struct ccm *)CCM_BASE);
+	uintptr_t addr;
+
+	if (id > CCM_ROOT_CTRL_NUM)
+		return;
+
+	addr = (uintptr_t)&ccm->ccm_root_ctrl[id].ccm_target_root;
+	mmio_write_32(addr, val);
+}
+
+void imx_clock_target_clr(unsigned int id, uint32_t val)
+{
+	struct ccm *ccm = ((struct ccm *)CCM_BASE);
+	uintptr_t addr;
+
+	if (id > CCM_ROOT_CTRL_NUM)
+		return;
+
+	addr = (uintptr_t)&ccm->ccm_root_ctrl[id].ccm_target_root_clr;
+	mmio_write_32(addr, val);
+}
+
+void imx_clock_gate_enable(unsigned int id, bool enable)
+{
+	struct ccm *ccm = ((struct ccm *)CCM_BASE);
+	uintptr_t addr;
+
+	if (id > CCM_CLK_GATE_CTRL_NUM)
+		return;
+
+	/* TODO: add support for more than DOMAIN0 clocks */
+	if (enable)
+		addr = (uintptr_t)&ccm->ccm_clk_gate_ctrl[id].ccm_ccgr_set;
+	else
+		addr = (uintptr_t)&ccm->ccm_clk_gate_ctrl[id].ccm_ccgr_clr;
+
+	mmio_write_32(addr, CCM_CCGR_SETTING0_DOM_CLK_ALWAYS);
+}
+
+void imx_clock_enable_uart(unsigned int uart_id, uint32_t uart_clk_en_bits)
+{
+	unsigned int ccm_trgt_id = CCM_TRT_ID_UART1_CLK_ROOT + uart_id;
+	unsigned int ccm_ccgr_id = CCM_CCGR_ID_UART1 + uart_id;
+
+	/* Check for error */
+	if (uart_id > MXC_MAX_UART_NUM)
+		return;
+
+	/* Set target register values */
+	imx_clock_target_set(ccm_trgt_id, uart_clk_en_bits);
+
+	/* Enable the clock gate */
+	imx_clock_gate_enable(ccm_ccgr_id, true);
+}
+
+void imx_clock_disable_uart(unsigned int uart_id)
+{
+	unsigned int ccm_trgt_id = CCM_TRT_ID_UART1_CLK_ROOT + uart_id;
+	unsigned int ccm_ccgr_id = CCM_CCGR_ID_UART1 + uart_id;
+
+	/* Check for error */
+	if (uart_id > MXC_MAX_UART_NUM)
+		return;
+
+	/* Disable the clock gate */
+	imx_clock_gate_enable(ccm_ccgr_id, false);
+
+	/* Clear the target */
+	imx_clock_target_clr(ccm_trgt_id, 0xFFFFFFFF);
+}
+
+void imx_clock_enable_usdhc(unsigned int usdhc_id, uint32_t usdhc_clk_en_bits)
+{
+	unsigned int ccm_trgt_id = CCM_TRT_ID_USDHC1_CLK_ROOT + usdhc_id;
+	unsigned int ccm_ccgr_id = CCM_CCGR_ID_USBHDC1 + usdhc_id;
+
+	/* Check for error */
+	if (usdhc_id > MXC_MAX_USDHC_NUM)
+		return;
+
+	/* Set target register values */
+	imx_clock_target_set(ccm_trgt_id, usdhc_clk_en_bits);
+
+	/* Enable the clock gate */
+	imx_clock_gate_enable(ccm_ccgr_id, true);
+}
+
+void imx_clock_enable_wdog(unsigned int wdog_id)
+{
+	unsigned int ccm_ccgr_id = CCM_CCGR_ID_WDOG1 + wdog_id;
+
+	/* Check for error */
+	if (wdog_id > MXC_MAX_WDOG_NUM)
+		return;
+
+	/* Enable the clock gate */
+	imx_clock_gate_enable(ccm_ccgr_id, true);
+}
+
+void imx_clock_disable_wdog(unsigned int wdog_id)
+{
+	unsigned int ccm_trgt_id = CCM_TRT_ID_WDOG_CLK_ROOT;
+	unsigned int ccm_ccgr_id = CCM_CCGR_ID_WDOG1 + wdog_id;
+
+	/* Check for error */
+	if (wdog_id > MXC_MAX_WDOG_NUM)
+		return;
+
+	/* Disable the clock gate */
+	imx_clock_gate_enable(ccm_ccgr_id, false);
+
+	/* Clear the target */
+	imx_clock_target_clr(ccm_trgt_id, 0xFFFFFFFF);
+}
+
+void imx_clock_set_wdog_clk_root_bits(uint32_t wdog_clk_root_en_bits)
+{
+	/* Enable the common clock root just once */
+	imx_clock_target_set(CCM_TRT_ID_WDOG_CLK_ROOT, wdog_clk_root_en_bits);
+}
+
+void imx_clock_enable_usb(unsigned int ccm_ccgr_usb_id)
+{
+	/* Enable the clock gate */
+	imx_clock_gate_enable(ccm_ccgr_usb_id, true);
+}
+
+void imx_clock_disable_usb(unsigned int ccm_ccgr_usb_id)
+{
+	/* Disable the clock gate */
+	imx_clock_gate_enable(ccm_ccgr_usb_id, false);
+}
+
+void imx_clock_set_usb_clk_root_bits(uint32_t usb_clk_root_en_bits)
+{
+	/* Enable the common clock root just once */
+	imx_clock_target_set(CCM_TRT_ID_USB_HSIC_CLK_ROOT, usb_clk_root_en_bits);
+}

plat/imx/common/imx_csu.c

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <mmio.h>
+#include <imx_csu.h>
+#include <imx_regs.h>
+
+void imx_csu_init(void)
+{
+	int i;
+	uintptr_t *csl_reg = (uintptr_t *)CSU_BASE;
+
+	for (i = 0; i < MXC_MAX_CSU_REGS; i++, csl_reg++)
+		mmio_write_32((uintptr_t)csl_reg, CSU_CSL_OPEN_ACCESS);
+}

plat/imx/common/imx_io_mux.c

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <imx_regs.h>
+#include <imx_io_mux.h>
+
+void imx_io_muxc_set_pad_alt_function(uint32_t pad_mux_offset, uint32_t alt_function)
+{
+	uintptr_t addr = (uintptr_t)(MXC_IO_MUXC_BASE + pad_mux_offset);
+
+	mmio_write_32(addr, alt_function);
+}
+
+void imx_io_muxc_set_pad_features(uint32_t pad_feature_offset, uint32_t pad_features)
+{
+	uintptr_t addr = (uintptr_t)(MXC_IO_MUXC_BASE + pad_feature_offset);
+
+	mmio_write_32(addr, pad_features);
+}

plat/imx/common/imx_snvs.c

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <imx_regs.h>
+#include <imx_snvs.h>
+
+void imx_snvs_init(void)
+{
+	struct snvs *snvs = (struct snvs *)SNVS_BASE;
+	uintptr_t addr;
+	uint32_t val;
+
+	addr = (uintptr_t)&snvs->hpcomr;
+	val = mmio_read_32(addr);
+	val |= HPCOMR_NPSWA_EN;
+	mmio_write_32(addr, val);
+}

plat/imx/common/imx_wdog.c

+/*
+ * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <mmio.h>
+#include <imx_regs.h>
+#include <imx_wdog.h>
+
+static void imx_wdog_power_down(unsigned long base)
+{
+	struct wdog_regs *wdog = (struct wdog_regs *)base;
+
+	mmio_write_16((uintptr_t)&wdog->wmcr, 0);
+}
+
+void imx_wdog_init(void)
+{
+	imx_wdog_power_down(WDOG1_BASE);
+	imx_wdog_power_down(WDOG2_BASE);
+	imx_wdog_power_down(WDOG3_BASE);
+	imx_wdog_power_down(WDOG4_BASE);
+}