Merge pull request #1821 from Yann-lms/stm32mp1_2019-02-14

Series of new patches for STM32MP1

include/drivers/st/stm32mp1_rcc.h

@@ -280,6 +280,9 @@
 /* Offset between RCC_MP_xxxENSETR and RCC_MP_xxxENCLRR registers */
 #define RCC_MP_ENCLRR_OFFSET		U(4)
 
+/* Offset between RCC_xxxRSTSETR and RCC_xxxRSTCLRR registers */
+#define RCC_RSTCLRR_OFFSET		U(4)
+
 /* Fields of RCC_BDCR register */
 #define RCC_BDCR_LSEON			BIT(0)
 #define RCC_BDCR_LSEBYP			BIT(1)

include/drivers/st/stm32mp1_reset.h

-/*
- * Copyright (c) 2018, STMicroelectronics - All Rights Reserved
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef STM32MP1_RESET_H
-#define STM32MP1_RESET_H
-
-#include <stdint.h>
-
-void stm32mp1_reset_assert(uint32_t reset_id);
-void stm32mp1_reset_deassert(uint32_t reset_id);
-
-#endif /* STM32MP1_RESET_H */

include/drivers/st/stm32mp_clkfunc.h

+/*
+ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_CLKFUNC_H
+#define STM32MP_CLKFUNC_H
+
+#include <stdbool.h>
+
+#include <libfdt.h>
+
+int fdt_get_rcc_node(void *fdt);
+uint32_t fdt_rcc_read_addr(void);
+int fdt_rcc_read_uint32_array(const char *prop_name,
+			      uint32_t *array, uint32_t count);
+int fdt_rcc_subnode_offset(const char *name);
+const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp);
+bool fdt_get_rcc_secure_status(void);
+
+uintptr_t fdt_get_stgen_base(void);
+int fdt_get_clock_id(int node);
+
+#endif /* STM32MP_CLKFUNC_H */

include/drivers/st/stm32mp_pmic.h

@@ -11,10 +11,41 @@
 
 #include <platform_def.h>
 
-bool dt_check_pmic(void);
-int dt_pmic_enable_boot_on_regulators(void);
-void initialize_pmic_i2c(void);
+/*
+ * dt_pmic_status - Check PMIC status from device tree
+ *
+ * Returns the status of the PMIC (secure, non-secure), or a negative value on
+ * error
+ */
+int dt_pmic_status(void);
+
+/*
+ * dt_pmic_configure_boot_on_regulators - Configure boot-on and always-on
+ * regulators from device tree configuration
+ *
+ * Returns 0 on success, and negative values on errors
+ */
+int dt_pmic_configure_boot_on_regulators(void);
+
+/*
+ * initialize_pmic_i2c - Initialize I2C for the PMIC control
+ *
+ * Returns true if PMIC is available, false if not found, panics on errors
+ */
+bool initialize_pmic_i2c(void);
+
+/*
+ * initialize_pmic - Main PMIC initialization function, called at platform init
+ *
+ * Panics on errors
+ */
 void initialize_pmic(void);
+
+/*
+ * pmic_ddr_power_init - Initialize regulators required for DDR
+ *
+ * Returns 0 on success, and negative values on errors
+ */
 int pmic_ddr_power_init(enum ddr_type ddr_type);
 
 #endif /* STM32MP_PMIC_H */

include/drivers/st/stm32mp_reset.h

+/*
+ * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_RESET_H
+#define STM32MP_RESET_H
+
+#include <stdint.h>
+
+void stm32mp_reset_assert(uint32_t reset_id);
+void stm32mp_reset_deassert(uint32_t reset_id);
+
+#endif /* STM32MP_RESET_H */

plat/st/stm32mp1/bl2_io_storage.c → plat/st/common/bl2_io_storage.c

@@ -20,14 +20,10 @@
 #include <drivers/st/io_mmc.h>
 #include <drivers/st/io_stm32image.h>
 #include <drivers/st/stm32_sdmmc2.h>
-#include <drivers/st/stm32mp1_rcc.h>
 #include <lib/mmio.h>
 #include <lib/utils.h>
 #include <plat/common/platform.h>
 
-#include <boot_api.h>
-#include <stm32mp1_private.h>
-
 /* IO devices */
 static const io_dev_connector_t *dummy_dev_con;
 static uintptr_t dummy_dev_handle;
@@ -60,12 +56,12 @@ static const io_dev_connector_t *mmc_dev_con;
 
 static const io_block_spec_t bl32_block_spec = {
 	.offset = BL32_BASE,
-	.length = STM32MP1_BL32_SIZE
+	.length = STM32MP_BL32_SIZE
 };
 
 static const io_block_spec_t bl2_block_spec = {
 	.offset = BL2_BASE,
-	.length = STM32MP1_BL2_SIZE,
+	.length = STM32MP_BL2_SIZE,
 };
 
 static const struct stm32image_part_info bl33_partition_spec = {
@@ -166,7 +162,7 @@ static void print_boot_device(boot_api_context_t *boot_context)
 	}
 }
 
-void stm32mp1_io_setup(void)
+void stm32mp_io_setup(void)
 {
 	int io_result __unused;
 	uint8_t idx;
@@ -176,7 +172,7 @@ void stm32mp1_io_setup(void)
 	uintptr_t mmc_default_instance;
 	const partition_entry_t *entry;
 	boot_api_context_t *boot_context =
-		(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
+		(boot_api_context_t *)stm32mp_get_boot_ctx_address();
 
 	print_boot_device(boot_context);
 
@@ -203,21 +199,21 @@ void stm32mp1_io_setup(void)
 		if (boot_context->boot_interface_selected ==
 		    BOOT_API_CTX_BOOT_INTERFACE_SEL_FLASH_EMMC) {
 			device_info.mmc_dev_type = MMC_IS_EMMC;
-			mmc_default_instance = STM32MP1_SDMMC2_BASE;
+			mmc_default_instance = STM32MP_SDMMC2_BASE;
 		} else {
 			device_info.mmc_dev_type = MMC_IS_SD;
-			mmc_default_instance = STM32MP1_SDMMC1_BASE;
+			mmc_default_instance = STM32MP_SDMMC1_BASE;
 		}
 
 		switch (boot_context->boot_interface_instance) {
 		case 1:
-			params.reg_base = STM32MP1_SDMMC1_BASE;
+			params.reg_base = STM32MP_SDMMC1_BASE;
 			break;
 		case 2:
-			params.reg_base = STM32MP1_SDMMC2_BASE;
+			params.reg_base = STM32MP_SDMMC2_BASE;
 			break;
 		case 3:
-			params.reg_base = STM32MP1_SDMMC3_BASE;
+			params.reg_base = STM32MP_SDMMC3_BASE;
 			break;
 		default:
 			WARN("SDMMC instance not found, using default\n");

plat/st/common/include/stm32mp_common.h

+/*
+ * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2018-2019, Linaro Limited
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_COMMON_H
+#define STM32MP_COMMON_H
+
+#include <stdbool.h>
+
+#include <arch_helpers.h>
+
+/* Functions to save and get boot context address given by ROM code */
+void stm32mp_save_boot_ctx_address(uintptr_t address);
+uintptr_t stm32mp_get_boot_ctx_address(void);
+
+/* Return the base address of the DDR controller */
+uintptr_t stm32mp_ddrctrl_base(void);
+
+/* Return the base address of the DDR PHY */
+uintptr_t stm32mp_ddrphyc_base(void);
+
+/* Return the base address of the PWR peripheral */
+uintptr_t stm32mp_pwr_base(void);
+
+/* Return the base address of the RCC peripheral */
+uintptr_t stm32mp_rcc_base(void);
+
+/*
+ * Platform util functions for the GPIO driver
+ * @bank: Target GPIO bank ID as per DT bindings
+ *
+ * Platform shall implement these functions to provide to stm32_gpio
+ * driver the resource reference for a target GPIO bank. That are
+ * memory mapped interface base address, interface offset (see below)
+ * and clock identifier.
+ *
+ * stm32_get_gpio_bank_offset() returns a bank offset that is used to
+ * check DT configuration matches platform implementation of the banks
+ * description.
+ */
+uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
+unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
+uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
+
+/*
+ * Util for clock gating and to get clock rate for stm32 and platform drivers
+ * @id: Target clock ID, ID used in clock DT bindings
+ */
+bool stm32mp_clk_is_enabled(unsigned long id);
+void stm32mp_clk_enable(unsigned long id);
+void stm32mp_clk_disable(unsigned long id);
+unsigned long stm32mp_clk_get_rate(unsigned long id);
+
+/* Initialise the IO layer and register platform IO devices */
+void stm32mp_io_setup(void);
+
+static inline uint64_t arm_cnt_us2cnt(uint32_t us)
+{
+	return ((uint64_t)us * (uint64_t)read_cntfrq()) / 1000000ULL;
+}
+
+static inline uint64_t timeout_init_us(uint32_t us)
+{
+	return read_cntpct_el0() + arm_cnt_us2cnt(us);
+}
+
+static inline bool timeout_elapsed(uint64_t expire)
+{
+	return read_cntpct_el0() > expire;
+}
+
+#endif /* STM32MP_COMMON_H */

plat/st/stm32mp1/include/stm32mp1_dt.h → plat/st/common/include/stm32mp_dt.h

@@ -4,8 +4,8 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef STM32MP1_DT_H
-#define STM32MP1_DT_H
+#ifndef STM32MP_DT_H
+#define STM32MP_DT_H
 
 #include <stdbool.h>
 
@@ -27,7 +27,7 @@ struct dt_node_info {
 int dt_open_and_check(void);
 int fdt_get_address(void **fdt_addr);
 bool fdt_check_node(int node);
-uint32_t fdt_get_status(int node);
+uint8_t fdt_get_status(int node);
 uint32_t fdt_read_uint32_default(int node, const char *prop_name,
 				 uint32_t dflt_value);
 int fdt_read_uint32_array(int node, const char *prop_name,
@@ -38,6 +38,9 @@ int dt_get_node(struct dt_node_info *info, int offset, const char *compat);
 int dt_get_stdout_uart_info(struct dt_node_info *info);
 int dt_get_stdout_node_offset(void);
 uint32_t dt_get_ddr_size(void);
+uintptr_t dt_get_ddrctrl_base(void);
+uintptr_t dt_get_ddrphyc_base(void);
+uintptr_t dt_get_pwr_base(void);
 const char *dt_get_board_model(void);
 
-#endif /* STM32MP1_DT_H */
+#endif /* STM32MP_DT_H */

plat/st/common/include/stm32mp_shres_helpers.h

+/*
+ * Copyright (C) 2018-2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef STM32MP_SHRES_HELPERS_H
+#define STM32MP_SHRES_HELPERS_H
+
+#include <stdint.h>
+
+#include <common/debug.h>
+
+/*
+ * Shared reference counter: increments by 2 on secure increment
+ * request, decrements by 2 on secure decrement request. Bit #0
+ * is set to 1 on non-secure increment request and reset to 0 on
+ * non-secure decrement request. The counter initializes to
+ * either 0, 1 or 2 upon their expect default state.
+ * Counters saturates once above UINT_MAX / 2.
+ */
+#define SHREFCNT_NONSECURE_FLAG		0x1UL
+#define SHREFCNT_SECURE_STEP		0x2UL
+#define SHREFCNT_MAX			(UINT32_MAX / 2)
+
+/* Return 1 if refcnt increments from 0, else return 0 */
+static inline int stm32mp_incr_shrefcnt(unsigned int *refcnt, bool secure)
+{
+	int rc = !*refcnt;
+
+	if (secure) {
+		*refcnt += SHREFCNT_SECURE_STEP;
+		if (*refcnt >= SHREFCNT_MAX) {
+			panic();
+		}
+	} else {
+		*refcnt |= SHREFCNT_NONSECURE_FLAG;
+	}
+
+	return rc;
+}
+
+/* Return 1 if refcnt decrements to 0, else return 0 */
+static inline int stm32mp_decr_shrefcnt(unsigned int *refcnt, bool secure)
+{
+	int  rc = 0;
+
+	if (secure) {
+		if (*refcnt < SHREFCNT_MAX) {
+			if (*refcnt < SHREFCNT_SECURE_STEP) {
+				panic();
+			}
+			*refcnt -= SHREFCNT_SECURE_STEP;
+			rc = !*refcnt;
+		}
+	} else {
+		rc = (*refcnt == SHREFCNT_NONSECURE_FLAG) ? 1 : 0;
+		*refcnt &= ~SHREFCNT_NONSECURE_FLAG;
+	}
+
+	return rc;
+}
+
+static inline int stm32mp_incr_refcnt(unsigned int *refcnt)
+{
+	return stm32mp_incr_shrefcnt(refcnt, true);
+}
+
+static inline int stm32mp_decr_refcnt(unsigned int *refcnt)
+{
+	return stm32mp_decr_shrefcnt(refcnt, true);
+}
+
+#endif /* STM32MP_SHRES_HELPERS_H */

plat/st/common/stm32mp_common.c

+/*
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <assert.h>
+
+#include <platform_def.h>
+
+#include <arch_helpers.h>
+#include <common/debug.h>
+#include <drivers/st/stm32mp_clkfunc.h>
+#include <plat/common/platform.h>
+
+uintptr_t plat_get_ns_image_entrypoint(void)
+{
+	return BL33_BASE;
+}
+
+unsigned int plat_get_syscnt_freq2(void)
+{
+	return read_cntfrq_el0();
+}
+
+static uintptr_t boot_ctx_address;
+
+void stm32mp_save_boot_ctx_address(uintptr_t address)
+{
+	boot_ctx_address = address;
+}
+
+uintptr_t stm32mp_get_boot_ctx_address(void)
+{
+	return boot_ctx_address;
+}
+
+uintptr_t stm32mp_ddrctrl_base(void)
+{
+	static uintptr_t ddrctrl_base;
+
+	if (ddrctrl_base == 0) {
+		ddrctrl_base = dt_get_ddrctrl_base();
+
+		assert(ddrctrl_base == DDRCTRL_BASE);
+	}
+
+	return ddrctrl_base;
+}
+
+uintptr_t stm32mp_ddrphyc_base(void)
+{
+	static uintptr_t ddrphyc_base;
+
+	if (ddrphyc_base == 0) {
+		ddrphyc_base = dt_get_ddrphyc_base();
+
+		assert(ddrphyc_base == DDRPHYC_BASE);
+	}
+
+	return ddrphyc_base;
+}
+
+uintptr_t stm32mp_pwr_base(void)
+{
+	static uintptr_t pwr_base;
+
+	if (pwr_base == 0) {
+		pwr_base = dt_get_pwr_base();
+
+		assert(pwr_base == PWR_BASE);
+	}
+
+	return pwr_base;
+}
+
+uintptr_t stm32mp_rcc_base(void)
+{
+	static uintptr_t rcc_base;
+
+	if (rcc_base == 0) {
+		rcc_base = fdt_rcc_read_addr();
+
+		assert(rcc_base == RCC_BASE);
+	}
+
+	return rcc_base;
+}
+
+uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
+{
+	if (bank == GPIO_BANK_Z) {
+		return GPIOZ_BASE;
+	}
+
+	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+
+	return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
+}
+
+unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
+{
+	if (bank == GPIO_BANK_Z) {
+		return GPIOZ;
+	}
+
+	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+
+	return GPIOA + (bank - GPIO_BANK_A);
+}
+
+uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
+{
+	if (bank == GPIO_BANK_Z) {
+		return 0;
+	}
+
+	assert(GPIO_BANK_A == 0 && bank <= GPIO_BANK_K);
+
+	return bank * GPIO_BANK_OFFSET;
+}

plat/st/stm32mp1/stm32mp1_dt.c → plat/st/common/stm32mp_dt.c

@@ -13,14 +13,14 @@
 
 #include <common/debug.h>
 #include <drivers/st/stm32_gpio.h>
-#include <drivers/st/stm32mp1_clk.h>
-#include <drivers/st/stm32mp1_clkfunc.h>
 #include <drivers/st/stm32mp1_ddr.h>
 #include <drivers/st/stm32mp1_ram.h>
 
+#include <stm32mp_dt.h>
+
 static int fdt_checked;
 
-static void *fdt = (void *)(uintptr_t)STM32MP1_DTB_BASE;
+static void *fdt = (void *)(uintptr_t)STM32MP_DTB_BASE;
 
 /*******************************************************************************
  * This function checks device tree file with its header.
@@ -68,9 +68,9 @@ bool fdt_check_node(int node)
 /*******************************************************************************
  * This function return global node status (generic use of fdt library).
  ******************************************************************************/
-uint32_t fdt_get_status(int node)
+uint8_t fdt_get_status(int node)
 {
-	uint32_t status = DT_DISABLED;
+	uint8_t status = DT_DISABLED;
 	int len;
 	const char *cchar;
 
@@ -291,6 +291,73 @@ uint32_t dt_get_ddr_size(void)
 	return fdt_read_uint32_default(node, "st,mem-size", 0);
 }
 
+/*******************************************************************************
+ * This function gets DDRCTRL base address information from the DT.
+ * Returns value on success, and 0 on failure.
+ ******************************************************************************/
+uintptr_t dt_get_ddrctrl_base(void)
+{
+	int node;
+	uint32_t array[4];
+
+	node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
+	if (node < 0) {
+		INFO("%s: Cannot read DDR node in DT\n", __func__);
+		return 0;
+	}
+
+	if (fdt_read_uint32_array(node, "reg", array, 4) < 0) {
+		return 0;
+	}
+
+	return array[0];
+}
+
+/*******************************************************************************
+ * This function gets DDRPHYC base address information from the DT.
+ * Returns value on success, and 0 on failure.
+ ******************************************************************************/
+uintptr_t dt_get_ddrphyc_base(void)
+{
+	int node;
+	uint32_t array[4];
+
+	node = fdt_node_offset_by_compatible(fdt, -1, DT_DDR_COMPAT);
+	if (node < 0) {
+		INFO("%s: Cannot read DDR node in DT\n", __func__);
+		return 0;
+	}
+
+	if (fdt_read_uint32_array(node, "reg", array, 4) < 0) {
+		return 0;
+	}
+
+	return array[2];
+}
+
+/*******************************************************************************
+ * This function gets PWR base address information from the DT.
+ * Returns value on success, and 0 on failure.
+ ******************************************************************************/
+uintptr_t dt_get_pwr_base(void)
+{
+	int node;
+	const fdt32_t *cuint;
+
+	node = fdt_node_offset_by_compatible(fdt, -1, DT_PWR_COMPAT);
+	if (node < 0) {
+		INFO("%s: Cannot read PWR node in DT\n", __func__);
+		return 0;
+	}
+
+	cuint = fdt_getprop(fdt, node, "reg", NULL);
+	if (cuint == NULL) {
+		return 0;
+	}
+
+	return fdt32_to_cpu(*cuint);
+}
+
 /*******************************************************************************
  * This function retrieves board model from DT
  * Returns string taken from model node, NULL otherwise

plat/st/stm32mp1/bl2_plat_setup.c

@@ -17,25 +17,21 @@
 #include <drivers/generic_delay_timer.h>
 #include <drivers/st/stm32_console.h>
 #include <drivers/st/stm32mp_pmic.h>
+#include <drivers/st/stm32mp_reset.h>
 #include <drivers/st/stm32mp1_clk.h>
 #include <drivers/st/stm32mp1_pwr.h>
 #include <drivers/st/stm32mp1_ram.h>
-#include <drivers/st/stm32mp1_rcc.h>
-#include <drivers/st/stm32mp1_reset.h>
 #include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
 #include <plat/common/platform.h>
 
-#include <boot_api.h>
 #include <stm32mp1_context.h>
-#include <stm32mp1_dt.h>
-#include <stm32mp1_private.h>
 
 static struct console_stm32 console;
 
 static void print_reset_reason(void)
 {
-	uint32_t rstsr = mmio_read_32(RCC_BASE + RCC_MP_RSTSCLRR);
+	uint32_t rstsr = mmio_read_32(stm32mp_rcc_base() + RCC_MP_RSTSCLRR);
 
 	if (rstsr == 0U) {
 		WARN("Reset reason unknown\n");
@@ -123,14 +119,14 @@ void bl2_el3_early_platform_setup(u_register_t arg0,
 				  u_register_t arg2 __unused,
 				  u_register_t arg3 __unused)
 {
-	stm32mp1_save_boot_ctx_address(arg0);
+	stm32mp_save_boot_ctx_address(arg0);
 }
 
 void bl2_platform_setup(void)
 {
 	int ret;
 
-	if (dt_check_pmic()) {
+	if (dt_pmic_status() > 0) {
 		initialize_pmic();
 	}
 
@@ -149,8 +145,10 @@ void bl2_el3_plat_arch_setup(void)
 	struct dt_node_info dt_uart_info;
 	const char *board_model;
 	boot_api_context_t *boot_context =
-		(boot_api_context_t *)stm32mp1_get_boot_ctx_address();
+		(boot_api_context_t *)stm32mp_get_boot_ctx_address();
 	uint32_t clk_rate;
+	uintptr_t pwr_base;
+	uintptr_t rcc_base;
 
 	mmap_add_region(BL_CODE_BASE, BL_CODE_BASE,
 			BL_CODE_END - BL_CODE_BASE,
@@ -162,9 +160,9 @@ void bl2_el3_plat_arch_setup(void)
 			MT_MEMORY | MT_RO | MT_SECURE);
 
 	/* Map non secure DDR for BL33 load and DDR training area restore */
-	mmap_add_region(STM32MP1_DDR_BASE,
-			STM32MP1_DDR_BASE,
-			STM32MP1_DDR_MAX_SIZE,
+	mmap_add_region(STM32MP_DDR_BASE,
+			STM32MP_DDR_BASE,
+			STM32MP_DDR_MAX_SIZE,
 			MT_MEMORY | MT_RW | MT_NS);
 
 	/* Prevent corruption of preloaded Device Tree */
@@ -178,27 +176,30 @@ void bl2_el3_plat_arch_setup(void)
 		panic();
 	}
 
+	pwr_base = stm32mp_pwr_base();
+	rcc_base = stm32mp_rcc_base();
+
 	/*
 	 * Disable the backup domain write protection.
 	 * The protection is enable at each reset by hardware
 	 * and must be disabled by software.
 	 */
-	mmio_setbits_32(PWR_BASE + PWR_CR1, PWR_CR1_DBP);
+	mmio_setbits_32(pwr_base + PWR_CR1, PWR_CR1_DBP);
 
-	while ((mmio_read_32(PWR_BASE + PWR_CR1) & PWR_CR1_DBP) == 0U) {
+	while ((mmio_read_32(pwr_base + PWR_CR1) & PWR_CR1_DBP) == 0U) {
 		;
 	}
 
 	/* Reset backup domain on cold boot cases */
-	if ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
-		mmio_setbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST);
+	if ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_RTCSRC_MASK) == 0U) {
+		mmio_setbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
 
-		while ((mmio_read_32(RCC_BASE + RCC_BDCR) & RCC_BDCR_VSWRST) ==
+		while ((mmio_read_32(rcc_base + RCC_BDCR) & RCC_BDCR_VSWRST) ==
 		       0U) {
 			;
 		}
 
-		mmio_clrbits_32(RCC_BASE + RCC_BDCR, RCC_BDCR_VSWRST);
+		mmio_clrbits_32(rcc_base + RCC_BDCR, RCC_BDCR_VSWRST);
 	}
 
 	generic_delay_timer_init();
@@ -224,19 +225,17 @@ void bl2_el3_plat_arch_setup(void)
 		goto skip_console_init;
 	}
 
-	if (stm32mp1_clk_enable((unsigned long)dt_uart_info.clock) != 0) {
-		goto skip_console_init;
-	}
+	stm32mp_clk_enable((unsigned long)dt_uart_info.clock);
 
-	stm32mp1_reset_assert((uint32_t)dt_uart_info.reset);
+	stm32mp_reset_assert((uint32_t)dt_uart_info.reset);
 	udelay(2);
-	stm32mp1_reset_deassert((uint32_t)dt_uart_info.reset);
+	stm32mp_reset_deassert((uint32_t)dt_uart_info.reset);
 	mdelay(1);
 
-	clk_rate = stm32mp1_clk_get_rate((unsigned long)dt_uart_info.clock);
+	clk_rate = stm32mp_clk_get_rate((unsigned long)dt_uart_info.clock);
 
 	if (console_stm32_register(dt_uart_info.base, clk_rate,
-				   STM32MP1_UART_BAUDRATE, &console) == 0) {
+				   STM32MP_UART_BAUDRATE, &console) == 0) {
 		panic();
 	}
 
@@ -257,5 +256,5 @@ skip_console_init:
 
 	print_reset_reason();
 
-	stm32mp1_io_setup();
+	stm32mp_io_setup();
 }

plat/st/stm32mp1/include/platform_def.h

@@ -29,8 +29,8 @@
 #define BL33_IMAGE_NAME			"ssbl"
 #define BL33_BINARY_TYPE		U(0x0)
 
-#define STM32MP1_PRIMARY_CPU		U(0x0)
-#define STM32MP1_SECONDARY_CPU		U(0x1)
+#define STM32MP_PRIMARY_CPU		U(0x0)
+#define STM32MP_SECONDARY_CPU		U(0x1)
 
 #define PLATFORM_CLUSTER_COUNT		ULL(1)
 #define PLATFORM_CLUSTER0_CORE_COUNT	U(2)
@@ -50,33 +50,33 @@
  * Put BL2 just below BL3-1. BL2_BASE is calculated using the current BL2 debug
  * size plus a little space for growth.
  */
-#define BL2_BASE			STM32MP1_BL2_BASE
-#define BL2_LIMIT			(STM32MP1_BL2_BASE + \
-					 STM32MP1_BL2_SIZE)
+#define BL2_BASE			STM32MP_BL2_BASE
+#define BL2_LIMIT			(STM32MP_BL2_BASE + \
+					 STM32MP_BL2_SIZE)
 
 /*******************************************************************************
  * BL32 specific defines.
  ******************************************************************************/
-#define BL32_BASE			STM32MP1_BL32_BASE
-#define BL32_LIMIT			(STM32MP1_BL32_BASE + \
-					 STM32MP1_BL32_SIZE)
+#define BL32_BASE			STM32MP_BL32_BASE
+#define BL32_LIMIT			(STM32MP_BL32_BASE + \
+					 STM32MP_BL32_SIZE)
 
 /*******************************************************************************
  * BL33 specific defines.
  ******************************************************************************/
-#define BL33_BASE			STM32MP1_BL33_BASE
+#define BL33_BASE			STM32MP_BL33_BASE
 
 /*
  * Load address of BL33 for this platform port
  */
-#define PLAT_STM32MP1_NS_IMAGE_OFFSET	BL33_BASE
+#define PLAT_STM32MP_NS_IMAGE_OFFSET	BL33_BASE
 
 /*******************************************************************************
  * DTB specific defines.
  ******************************************************************************/
-#define DTB_BASE			STM32MP1_DTB_BASE
-#define DTB_LIMIT			(STM32MP1_DTB_BASE + \
-					 STM32MP1_DTB_SIZE)
+#define DTB_BASE			STM32MP_DTB_BASE
+#define DTB_LIMIT			(STM32MP_DTB_BASE + \
+					 STM32MP_DTB_SIZE)
 
 /*******************************************************************************
  * Platform specific page table and MMU setup constants

plat/st/stm32mp1/include/stm32mp1_private.h

@@ -9,20 +9,12 @@
 
 #include <stdint.h>
 
-void stm32mp1_io_setup(void);
 void configure_mmu(void);
 
 void stm32mp1_arch_security_setup(void);
 void stm32mp1_security_setup(void);
 
-void stm32mp1_save_boot_ctx_address(uintptr_t address);
-uintptr_t stm32mp1_get_boot_ctx_address(void);
-
 void stm32mp1_gic_pcpu_init(void);
 void stm32mp1_gic_init(void);
 
-uintptr_t stm32_get_gpio_bank_base(unsigned int bank);
-unsigned long stm32_get_gpio_bank_clock(unsigned int bank);
-uint32_t stm32_get_gpio_bank_offset(unsigned int bank);
-
 #endif /* STM32MP1_PRIVATE_H */

plat/st/stm32mp1/plat_bl2_mem_params_desc.c

 /*
- * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -50,7 +50,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
 				      VERSION_2, entry_point_info_t,
 				      NON_SECURE | EXECUTABLE),
 
-		.ep_info.pc = PLAT_STM32MP1_NS_IMAGE_OFFSET,
+		.ep_info.pc = PLAT_STM32MP_NS_IMAGE_OFFSET,
 		.ep_info.spsr = SPSR_MODE32(MODE32_svc, SPSR_T_ARM,
 					    SPSR_E_LITTLE,
 					    DISABLE_ALL_EXCEPTIONS),
@@ -58,9 +58,9 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
 		SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
 				      VERSION_2, image_info_t, 0),
 
-		.image_info.image_base = PLAT_STM32MP1_NS_IMAGE_OFFSET,
-		.image_info.image_max_size = STM32MP1_DDR_MAX_SIZE -
-			(PLAT_STM32MP1_NS_IMAGE_OFFSET - STM32MP1_DDR_BASE),
+		.image_info.image_base = PLAT_STM32MP_NS_IMAGE_OFFSET,
+		.image_info.image_max_size = STM32MP_DDR_MAX_SIZE -
+			(PLAT_STM32MP_NS_IMAGE_OFFSET - STM32MP_DDR_BASE),
 
 		.next_handoff_image_id = INVALID_IMAGE_ID,
 	}

plat/st/stm32mp1/platform.mk

@@ -21,7 +21,8 @@ $(eval $(call add_define,STM32_TF_A_COPIES))
 PLAT_PARTITION_MAX_ENTRIES	:=	$(shell echo $$(($(STM32_TF_A_COPIES) + 1)))
 $(eval $(call add_define,PLAT_PARTITION_MAX_ENTRIES))
 
-PLAT_INCLUDES		:=	-Iplat/st/stm32mp1/include/
+PLAT_INCLUDES		:=	-Iplat/st/common/include/
+PLAT_INCLUDES		+=	-Iplat/st/stm32mp1/include/
 
 # Device tree
 DTB_FILE_NAME		?=	stm32mp157c-ev1.dtb
@@ -30,7 +31,8 @@ DTC_FLAGS		+=	-Wno-unit_address_vs_reg
 
 include lib/libfdt/libfdt.mk
 
-PLAT_BL_COMMON_SOURCES	:=	plat/st/stm32mp1/stm32mp1_common.c
+PLAT_BL_COMMON_SOURCES	:=	plat/st/common/stm32mp_common.c				\
+				plat/st/stm32mp1/stm32mp1_private.c
 
 PLAT_BL_COMMON_SOURCES	+=	drivers/st/uart/aarch32/stm32_console.S
 
@@ -48,6 +50,7 @@ PLAT_BL_COMMON_SOURCES	+=	${LIBFDT_SRCS}						\
 				drivers/delay_timer/delay_timer.c			\
 				drivers/delay_timer/generic_delay_timer.c		\
 				drivers/st/bsec/bsec.c					\
+				drivers/st/clk/stm32mp_clkfunc.c			\
 				drivers/st/clk/stm32mp1_clk.c				\
 				drivers/st/clk/stm32mp1_clkfunc.c			\
 				drivers/st/ddr/stm32mp1_ddr_helpers.c			\
@@ -56,8 +59,8 @@ PLAT_BL_COMMON_SOURCES	+=	${LIBFDT_SRCS}						\
 				drivers/st/pmic/stm32mp_pmic.c				\
 				drivers/st/pmic/stpmic1.c				\
 				drivers/st/reset/stm32mp1_reset.c			\
+				plat/st/common/stm32mp_dt.c				\
 				plat/st/stm32mp1/stm32mp1_context.c			\
-				plat/st/stm32mp1/stm32mp1_dt.c				\
 				plat/st/stm32mp1/stm32mp1_helper.S			\
 				plat/st/stm32mp1/stm32mp1_security.c
 
@@ -65,7 +68,7 @@ BL2_SOURCES		+=	drivers/io/io_block.c					\
 				drivers/io/io_dummy.c					\
 				drivers/io/io_storage.c					\
 				drivers/st/io/io_stm32image.c				\
-				plat/st/stm32mp1/bl2_io_storage.c			\
+				plat/st/common/bl2_io_storage.c				\
 				plat/st/stm32mp1/bl2_plat_setup.c
 
 BL2_SOURCES		+=	drivers/mmc/mmc.c					\

plat/st/stm32mp1/sp_min/sp_min_setup.c

@@ -27,8 +27,6 @@
 #include <plat/common/platform.h>
 
 #include <platform_sp_min.h>
-#include <stm32mp1_dt.h>
-#include <stm32mp1_private.h>
 
 /******************************************************************************
  * Placeholder variables for copying the arguments that have been passed to
@@ -125,7 +123,7 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
 
 	if ((result > 0) && (dt_uart_info.status != 0U)) {
 		if (console_stm32_register(dt_uart_info.base, 0,
-					   STM32MP1_UART_BAUDRATE, &console) ==
+					   STM32MP_UART_BAUDRATE, &console) ==
 		    0) {
 			panic();
 		}

plat/st/stm32mp1/stm32mp1.ld.S

 /*
- * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -17,7 +17,7 @@ ENTRY(__BL2_IMAGE_START__)
 
 MEMORY {
 	HEADER (rw) : ORIGIN = 0x00000000, LENGTH = 0x3000
-	RAM (rwx) : ORIGIN = STM32MP1_BINARY_BASE, LENGTH = STM32MP1_BINARY_SIZE
+	RAM (rwx) : ORIGIN = STM32MP_BINARY_BASE, LENGTH = STM32MP_BINARY_SIZE
 }
 
 SECTIONS
@@ -32,7 +32,7 @@ SECTIONS
         __HEADER_END__ = .;
     } >HEADER
 
-    . = STM32MP1_BINARY_BASE;
+    . = STM32MP_BINARY_BASE;
     .data . : {
         . = ALIGN(PAGE_SIZE);
         __DATA_START__ = .;
@@ -43,7 +43,7 @@ SECTIONS
          * The strongest and only alignment contraint is MMU 4K page.
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
-        . = ( STM32MP1_DTB_BASE - STM32MP1_BINARY_BASE );
+        . = ( STM32MP_DTB_BASE - STM32MP_BINARY_BASE );
         __DTB_IMAGE_START__ = .;
         *(.dtb_image*)
         __DTB_IMAGE_END__ = .;
@@ -53,7 +53,7 @@ SECTIONS
          * The strongest and only alignment contraint is MMU 4K page.
          * Indeed as images below will be removed, 4K pages will be re-used.
          */
-        . = ( STM32MP1_BL2_BASE - STM32MP1_BINARY_BASE );
+        . = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
         __BL2_IMAGE_START__ = .;
         *(.bl2_image*)
         __BL2_IMAGE_END__ = .;
@@ -63,7 +63,7 @@ SECTIONS
          * The strongest and only alignment constraint is 8 words to simplify
          * memraise8 assembly code.
          */
-        . = ( STM32MP1_BL32_BASE - STM32MP1_BINARY_BASE );
+        . = ( STM32MP_BL32_BASE - STM32MP_BINARY_BASE );
         __BL32_IMAGE_START__ = .;
         *(.bl32_image*)
         __BL32_IMAGE_END__ = .;

plat/st/stm32mp1/stm32mp1_context.c

 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -20,26 +20,16 @@
 
 int stm32_save_boot_interface(uint32_t interface, uint32_t instance)
 {
-	uint32_t tamp_clk_off = 0;
 	uint32_t bkpr_itf_idx = tamp_bkpr(TAMP_BOOT_ITF_BACKUP_REG_ID);
 
-	if (!stm32mp1_clk_is_enabled(RTCAPB)) {
-		tamp_clk_off = 1;
-		if (stm32mp1_clk_enable(RTCAPB) != 0) {
-			return -EINVAL;
-		}
-	}
+	stm32mp_clk_enable(RTCAPB);
 
 	mmio_clrsetbits_32(bkpr_itf_idx,
 			   TAMP_BOOT_ITF_MASK,
 			   ((interface << 4) | (instance & 0xFU)) <<
 			   TAMP_BOOT_ITF_SHIFT);
 
-	if (tamp_clk_off != 0U) {
-		if (stm32mp1_clk_disable(RTCAPB) != 0) {
-			return -EINVAL;
-		}
-	}
+	stm32mp_clk_disable(RTCAPB);
 
 	return 0;
 }

plat/st/stm32mp1/stm32mp1_def.h

@@ -8,12 +8,19 @@
 #define STM32MP1_DEF_H
 
 #include <common/tbbr/tbbr_img_def.h>
+#include <drivers/st/stm32mp1_rcc.h>
+#include <dt-bindings/clock/stm32mp1-clks.h>
+#include <dt-bindings/reset/stm32mp1-resets.h>
 #include <lib/utils_def.h>
 #include <lib/xlat_tables/xlat_tables_defs.h>
 
 #ifndef __ASSEMBLY__
+#include <drivers/st/stm32mp1_clk.h>
+
 #include <boot_api.h>
-#include <stm32mp1_dt.h>
+#include <stm32mp_common.h>
+#include <stm32mp_dt.h>
+#include <stm32mp_shres_helpers.h>
 #include <stm32mp1_private.h>
 #endif
 
@@ -21,14 +28,13 @@
  * STM32MP1 memory map related constants
  ******************************************************************************/
 
-#define STM32MP1_SRAM_BASE		U(0x2FFC0000)
-#define STM32MP1_SRAM_SIZE		U(0x00040000)
+#define STM32MP_SYSRAM_BASE		U(0x2FFC0000)
+#define STM32MP_SYSRAM_SIZE		U(0x00040000)
 
 /* DDR configuration */
-#define STM32MP1_DDR_BASE		U(0xC0000000)
-#define STM32MP1_DDR_SIZE_DFLT		U(0x20000000)	/* 512 MB */
-#define STM32MP1_DDR_MAX_SIZE		U(0x40000000)	/* Max 1GB */
-#define STM32MP1_DDR_SPEED_DFLT		528
+#define STM32MP_DDR_BASE		U(0xC0000000)
+#define STM32MP_DDR_MAX_SIZE		U(0x40000000)	/* Max 1GB */
+#define STM32MP_DDR_SPEED_DFLT		528
 
 /* DDR power initializations */
 #ifndef __ASSEMBLY__
@@ -39,36 +45,36 @@ enum ddr_type {
 #endif
 
 /* Section used inside TF binaries */
-#define STM32MP1_PARAM_LOAD_SIZE	U(0x00002400)	/* 9 Ko for param */
+#define STM32MP_PARAM_LOAD_SIZE		U(0x00002400)	/* 9 Ko for param */
 /* 256 Octets reserved for header */
-#define STM32MP1_HEADER_SIZE		U(0x00000100)
+#define STM32MP_HEADER_SIZE		U(0x00000100)
 
-#define STM32MP1_BINARY_BASE		(STM32MP1_SRAM_BASE +		\
-					 STM32MP1_PARAM_LOAD_SIZE +	\
-					 STM32MP1_HEADER_SIZE)
+#define STM32MP_BINARY_BASE		(STM32MP_SYSRAM_BASE +		\
+					 STM32MP_PARAM_LOAD_SIZE +	\
+					 STM32MP_HEADER_SIZE)
 
-#define STM32MP1_BINARY_SIZE		(STM32MP1_SRAM_SIZE -		\
-					 (STM32MP1_PARAM_LOAD_SIZE +	\
-					  STM32MP1_HEADER_SIZE))
+#define STM32MP_BINARY_SIZE		(STM32MP_SYSRAM_SIZE -		\
+					 (STM32MP_PARAM_LOAD_SIZE +	\
+					  STM32MP_HEADER_SIZE))
 
 #if STACK_PROTECTOR_ENABLED
-#define STM32MP1_BL32_SIZE		U(0x00012000)	/* 72 Ko for BL32 */
+#define STM32MP_BL32_SIZE		U(0x00012000)	/* 72 Ko for BL32 */
 #else
-#define STM32MP1_BL32_SIZE		U(0x00011000)	/* 68 Ko for BL32 */
+#define STM32MP_BL32_SIZE		U(0x00011000)	/* 68 Ko for BL32 */
 #endif
 
-#define STM32MP1_BL32_BASE		(STM32MP1_SRAM_BASE + \
-					 STM32MP1_SRAM_SIZE - \
-					 STM32MP1_BL32_SIZE)
+#define STM32MP_BL32_BASE		(STM32MP_SYSRAM_BASE + \
+					 STM32MP_SYSRAM_SIZE - \
+					 STM32MP_BL32_SIZE)
 
 #if STACK_PROTECTOR_ENABLED
-#define STM32MP1_BL2_SIZE		U(0x00015000)	/* 84 Ko for BL2 */
+#define STM32MP_BL2_SIZE		U(0x00015000)	/* 84 Ko for BL2 */
 #else
-#define STM32MP1_BL2_SIZE		U(0x00013000)	/* 76 Ko for BL2 */
+#define STM32MP_BL2_SIZE		U(0x00013000)	/* 76 Ko for BL2 */
 #endif
 
-#define STM32MP1_BL2_BASE		(STM32MP1_BL32_BASE - \
-					 STM32MP1_BL2_SIZE)
+#define STM32MP_BL2_BASE		(STM32MP_BL32_BASE - \
+					 STM32MP_BL2_SIZE)
 
 /* BL2 and BL32/sp_min require 5 tables */
 #define MAX_XLAT_TABLES			5
@@ -85,12 +91,12 @@ enum ddr_type {
 #endif
 
 /* DTB initialization value */
-#define STM32MP1_DTB_SIZE		U(0x00004000)	/* 16Ko for DTB */
+#define STM32MP_DTB_SIZE		U(0x00004000)	/* 16Ko for DTB */
 
-#define STM32MP1_DTB_BASE		(STM32MP1_BL2_BASE - \
-					 STM32MP1_DTB_SIZE)
+#define STM32MP_DTB_BASE		(STM32MP_BL2_BASE - \
+					 STM32MP_DTB_SIZE)
 
-#define STM32MP1_BL33_BASE		(STM32MP1_DDR_BASE + U(0x100000))
+#define STM32MP_BL33_BASE		(STM32MP_DDR_BASE + U(0x100000))
 
 /*******************************************************************************
  * STM32MP1 device/io map related constants (used for MMU)
@@ -155,12 +161,12 @@ enum ddr_type {
 #define USART6_BASE			U(0x44003000)
 #define UART7_BASE			U(0x40018000)
 #define UART8_BASE			U(0x40019000)
-#define STM32MP1_UART_BAUDRATE		U(115200)
+#define STM32MP_UART_BAUDRATE		U(115200)
 
 /* For UART crash console */
-#define STM32MP1_DEBUG_USART_BASE	UART4_BASE
+#define STM32MP_DEBUG_USART_BASE	UART4_BASE
 /* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
-#define STM32MP1_DEBUG_USART_CLK_FRQ	64000000
+#define STM32MP_DEBUG_USART_CLK_FRQ	64000000
 #define DEBUG_UART_TX_GPIO_BANK_ADDRESS	GPIOG_BASE
 #define DEBUG_UART_TX_GPIO_BANK_CLK_REG	RCC_MP_AHB4ENSETR
 #define DEBUG_UART_TX_GPIO_BANK_CLK_EN	RCC_MP_AHB4ENSETR_GPIOGEN
@@ -192,15 +198,15 @@ enum ddr_type {
 /*******************************************************************************
  * STM32MP1 SDMMC
  ******************************************************************************/
-#define STM32MP1_SDMMC1_BASE		U(0x58005000)
-#define STM32MP1_SDMMC2_BASE		U(0x58007000)
-#define STM32MP1_SDMMC3_BASE		U(0x48004000)
+#define STM32MP_SDMMC1_BASE		U(0x58005000)
+#define STM32MP_SDMMC2_BASE		U(0x58007000)
+#define STM32MP_SDMMC3_BASE		U(0x48004000)
 
-#define STM32MP1_MMC_INIT_FREQ			400000		/*400 KHz*/
-#define STM32MP1_SD_NORMAL_SPEED_MAX_FREQ	25000000	/*25 MHz*/
-#define STM32MP1_SD_HIGH_SPEED_MAX_FREQ		50000000	/*50 MHz*/
-#define STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ	26000000	/*26 MHz*/
-#define STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ	52000000	/*52 MHz*/
+#define STM32MP_MMC_INIT_FREQ			400000		/*400 KHz*/
+#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ	25000000	/*25 MHz*/
+#define STM32MP_SD_HIGH_SPEED_MAX_FREQ		50000000	/*50 MHz*/
+#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ	26000000	/*26 MHz*/
+#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ	52000000	/*52 MHz*/
 
 /*******************************************************************************
  * STM32MP1 BSEC / OTP
@@ -245,4 +251,10 @@ static inline uint32_t tamp_bkpr(uint32_t idx)
  ******************************************************************************/
 #define I2C4_BASE			U(0x5C002000)
 
+/*******************************************************************************
+ * Device Tree defines
+ ******************************************************************************/
+#define DT_PWR_COMPAT			"st,stm32mp1-pwr"
+#define DT_RCC_CLK_COMPAT		"st,stm32mp1-rcc"
+
 #endif /* STM32MP1_DEF_H */