Merge pull request #1821 from Yann-lms/stm32mp1_2019-02-14

Series of new patches for STM32MP1

drivers/st/clk/stm32mp1_clkfunc.c

@@ -10,17 +10,12 @@
 
 #include <platform_def.h>
 
+#include <drivers/st/stm32_gpio.h>
+#include <drivers/st/stm32mp_clkfunc.h>
 #include <drivers/st/stm32mp1_clk.h>
 #include <drivers/st/stm32mp1_clkfunc.h>
 #include <dt-bindings/clock/stm32mp1-clksrc.h>
 
-#define DT_RCC_NODE_NAME	"rcc@50000000"
-#define DT_RCC_CLK_COMPAT	"st,stm32mp1-rcc"
-#define DT_RCC_COMPAT		"syscon"
-#define DT_STGEN_COMPAT		"st,stm32-stgen"
-#define DT_UART_COMPAT		"st,stm32h7-uart"
-#define DT_USART_COMPAT		"st,stm32h7-usart"
-
 const char *stm32mp_osc_node_label[NB_OSC] = {
 	[_LSI] = "clk-lsi",
 	[_LSE] = "clk-lse",
@@ -28,23 +23,14 @@ const char *stm32mp_osc_node_label[NB_OSC] = {
 	[_HSE] = "clk-hse",
 	[_CSI] = "clk-csi",
 	[_I2S_CKIN] = "i2s_ckin",
-	[_USB_PHY_48] = "ck_usbo_48m"
 };
 
-/*******************************************************************************
- * This function returns the RCC node in the device tree.
- ******************************************************************************/
-static int fdt_get_rcc_node(void *fdt)
-{
-	return fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
-}
-
-/*******************************************************************************
- * This function reads the frequency of an oscillator from its name.
- * It reads the value indicated inside the device tree.
- * Returns 0 on success, and a negative FDT/ERRNO error code on failure.
- * On success, value is stored in the second parameter.
- ******************************************************************************/
+/*
+ * Get the frequency of an oscillator from its name in device tree.
+ * @param name: oscillator name
+ * @param freq: stores the frequency of the oscillator
+ * @return: 0 on success, and a negative FDT/ERRNO error code on failure.
+ */
 int fdt_osc_read_freq(const char *name, uint32_t *freq)
 {
 	int node, subnode;
@@ -88,11 +74,12 @@ int fdt_osc_read_freq(const char *name, uint32_t *freq)
 	return 0;
 }
 
-/*******************************************************************************
- * This function checks the presence of an oscillator property from its id.
- * The search is done inside the device tree.
- * Returns true/false regarding search result.
- ******************************************************************************/
+/*
+ * Check the presence of an oscillator property from its id.
+ * @param osc_id: oscillator ID
+ * @param prop_name: property name
+ * @return: true/false regarding search result.
+ */
 bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name)
 {
 	int node, subnode;
@@ -133,11 +120,13 @@ bool fdt_osc_read_bool(enum stm32mp_osc_id osc_id, const char *prop_name)
 	return false;
 }
 
-/*******************************************************************************
- * This function reads a value of a oscillator property from its id.
- * Returns value on success, and a default value if property not found.
- * Default value is passed as parameter.
- ******************************************************************************/
+/*
+ * Get the value of a oscillator property from its ID.
+ * @param osc_id: oscillator ID
+ * @param prop_name: property name
+ * @param dflt_value: default value
+ * @return oscillator value on success, default value if property not found.
+ */
 uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
 				     const char *prop_name, uint32_t dflt_value)
 {
@@ -176,201 +165,3 @@ uint32_t fdt_osc_read_uint32_default(enum stm32mp_osc_id osc_id,
 
 	return dflt_value;
 }
-
-/*******************************************************************************
- * This function reads the rcc base address.
- * It reads the value indicated inside the device tree.
- * Returns address if success, and 0 value else.
- ******************************************************************************/
-uint32_t fdt_rcc_read_addr(void)
-{
-	int node, subnode;
-	void *fdt;
-
-	if (fdt_get_address(&fdt) == 0) {
-		return 0;
-	}
-
-	node = fdt_path_offset(fdt, "/soc");
-	if (node < 0) {
-		return 0;
-	}
-
-	fdt_for_each_subnode(subnode, fdt, node) {
-		const char *cchar;
-		int ret;
-
-		cchar = fdt_get_name(fdt, subnode, &ret);
-		if (cchar == NULL) {
-			return 0;
-		}
-
-		if (strncmp(cchar, DT_RCC_NODE_NAME, (size_t)ret) == 0) {
-			const fdt32_t *cuint;
-
-			cuint = fdt_getprop(fdt, subnode, "reg", NULL);
-			if (cuint == NULL) {
-				return 0;
-			}
-
-			return fdt32_to_cpu(*cuint);
-		}
-	}
-
-	return 0;
-}
-
-/*******************************************************************************
- * This function reads a series of parameters in rcc-clk section.
- * It reads the values indicated inside the device tree, from property name.
- * The number of parameters is also indicated as entry parameter.
- * Returns 0 if success, and a negative value else.
- * If success, values are stored at the second parameter address.
- ******************************************************************************/
-int fdt_rcc_read_uint32_array(const char *prop_name,
-			      uint32_t *array, uint32_t count)
-{
-	int node;
-	void *fdt;
-
-	if (fdt_get_address(&fdt) == 0) {
-		return -ENOENT;
-	}
-
-	node = fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
-	if (node < 0) {
-		return -FDT_ERR_NOTFOUND;
-	}
-
-	return fdt_read_uint32_array(node, prop_name, array, count);
-}
-
-/*******************************************************************************
- * This function gets the subnode offset in rcc-clk section from its name.
- * It reads the values indicated inside the device tree.
- * Returns offset on success, and a negative FDT/ERRNO error code on failure.
- ******************************************************************************/
-int fdt_rcc_subnode_offset(const char *name)
-{
-	int node, subnode;
-	void *fdt;
-
-	if (fdt_get_address(&fdt) == 0) {
-		return -ENOENT;
-	}
-
-	node = fdt_get_rcc_node(fdt);
-	if (node < 0) {
-		return -FDT_ERR_NOTFOUND;
-	}
-
-	subnode = fdt_subnode_offset(fdt, node, name);
-	if (subnode <= 0) {
-		return -FDT_ERR_NOTFOUND;
-	}
-
-	return subnode;
-}
-
-/*******************************************************************************
- * This function gets the pointer to a rcc-clk property from its name.
- * It reads the values indicated inside the device tree.
- * Length of the property is stored in the second parameter.
- * Returns pointer on success, and NULL value on failure.
- ******************************************************************************/
-const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp)
-{
-	const fdt32_t *cuint;
-	int node, len;
-	void *fdt;
-
-	if (fdt_get_address(&fdt) == 0) {
-		return NULL;
-	}
-
-	node = fdt_get_rcc_node(fdt);
-	if (node < 0) {
-		return NULL;
-	}
-
-	cuint = fdt_getprop(fdt, node, prop_name, &len);
-	if (cuint == NULL) {
-		return NULL;
-	}
-
-	*lenp = len;
-	return cuint;
-}
-
-/*******************************************************************************
- * This function gets the secure status for rcc node.
- * It reads secure-status in device tree.
- * Returns true if rcc is available from secure world, false if not.
- ******************************************************************************/
-bool fdt_get_rcc_secure_status(void)
-{
-	int node;
-	void *fdt;
-
-	if (fdt_get_address(&fdt) == 0) {
-		return false;
-	}
-
-	node = fdt_get_rcc_node(fdt);
-	if (node < 0) {
-		return false;
-	}
-
-	return (fdt_get_status(node) & DT_SECURE) != 0U;
-}
-
-/*******************************************************************************
- * This function reads the stgen base address.
- * It reads the value indicated inside the device tree.
- * Returns address on success, and NULL value on failure.
- ******************************************************************************/
-uintptr_t fdt_get_stgen_base(void)
-{
-	int node;
-	const fdt32_t *cuint;
-	void *fdt;
-
-	if (fdt_get_address(&fdt) == 0) {
-		return 0;
-	}
-
-	node = fdt_node_offset_by_compatible(fdt, -1, DT_STGEN_COMPAT);
-	if (node < 0) {
-		return 0;
-	}
-
-	cuint = fdt_getprop(fdt, node, "reg", NULL);
-	if (cuint == NULL) {
-		return 0;
-	}
-
-	return fdt32_to_cpu(*cuint);
-}
-
-/*******************************************************************************
- * This function gets the clock ID of the given node.
- * It reads the value indicated inside the device tree.
- * Returns ID on success, and a negative FDT/ERRNO error code on failure.
- ******************************************************************************/
-int fdt_get_clock_id(int node)
-{
-	const fdt32_t *cuint;
-	void *fdt;
-
-	if (fdt_get_address(&fdt) == 0) {
-		return -ENOENT;
-	}
-
-	cuint = fdt_getprop(fdt, node, "clocks", NULL);
-	if (cuint == NULL) {
-		return -FDT_ERR_NOTFOUND;
-	}
-
-	cuint++;
-	return (int)fdt32_to_cpu(*cuint);
-}

drivers/st/clk/stm32mp_clkfunc.c

+/*
+ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include <errno.h>
+
+#include <libfdt.h>
+
+#include <platform_def.h>
+
+#include <drivers/st/stm32_gpio.h>
+#include <drivers/st/stm32mp_clkfunc.h>
+
+#define DT_STGEN_COMPAT		"st,stm32-stgen"
+
+/*
+ * Get the RCC node offset from the device tree
+ * @param fdt: Device tree reference
+ * @return: Node offset or a negative value on error
+ */
+int fdt_get_rcc_node(void *fdt)
+{
+	return fdt_node_offset_by_compatible(fdt, -1, DT_RCC_CLK_COMPAT);
+}
+
+/*
+ * Get the RCC base address from the device tree
+ * @return: RCC address or 0 on error
+ */
+uint32_t fdt_rcc_read_addr(void)
+{
+	int node;
+	void *fdt;
+	const fdt32_t *cuint;
+
+	if (fdt_get_address(&fdt) == 0) {
+		return 0;
+	}
+
+	node = fdt_get_rcc_node(fdt);
+	if (node < 0) {
+		return 0;
+	}
+
+	cuint = fdt_getprop(fdt, node, "reg", NULL);
+	if (cuint == NULL) {
+		return 0;
+	}
+
+	return fdt32_to_cpu(*cuint);
+}
+
+/*
+ * Read a series of parameters in rcc-clk section in device tree
+ * @param prop_name: Name of the RCC property to be read
+ * @param array: the array to store the property parameters
+ * @param count: number of parameters to be read
+ * @return: 0 on succes or a negative value on error
+ */
+int fdt_rcc_read_uint32_array(const char *prop_name,
+			      uint32_t *array, uint32_t count)
+{
+	int node;
+	void *fdt;
+
+	if (fdt_get_address(&fdt) == 0) {
+		return -ENOENT;
+	}
+
+	node = fdt_get_rcc_node(fdt);
+	if (node < 0) {
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	return fdt_read_uint32_array(node, prop_name, array, count);
+}
+
+/*
+ * Get the subnode offset in rcc-clk section from its name in device tree
+ * @param name: name of the RCC property
+ * @return: offset on success, and a negative FDT/ERRNO error code on failure.
+ */
+int fdt_rcc_subnode_offset(const char *name)
+{
+	int node, subnode;
+	void *fdt;
+
+	if (fdt_get_address(&fdt) == 0) {
+		return -ENOENT;
+	}
+
+	node = fdt_get_rcc_node(fdt);
+	if (node < 0) {
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	subnode = fdt_subnode_offset(fdt, node, name);
+	if (subnode <= 0) {
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	return subnode;
+}
+
+/*
+ * Get the pointer to a rcc-clk property from its name.
+ * @param name: name of the RCC property
+ * @param lenp: stores the length of the property.
+ * @return: pointer to the property on success, and NULL value on failure.
+ */
+const fdt32_t *fdt_rcc_read_prop(const char *prop_name, int *lenp)
+{
+	const fdt32_t *cuint;
+	int node, len;
+	void *fdt;
+
+	if (fdt_get_address(&fdt) == 0) {
+		return NULL;
+	}
+
+	node = fdt_get_rcc_node(fdt);
+	if (node < 0) {
+		return NULL;
+	}
+
+	cuint = fdt_getprop(fdt, node, prop_name, &len);
+	if (cuint == NULL) {
+		return NULL;
+	}
+
+	*lenp = len;
+	return cuint;
+}
+
+/*
+ * Get the secure status for rcc node in device tree.
+ * @return: true if rcc is available from secure world, false if not.
+ */
+bool fdt_get_rcc_secure_status(void)
+{
+	int node;
+	void *fdt;
+
+	if (fdt_get_address(&fdt) == 0) {
+		return false;
+	}
+
+	node = fdt_get_rcc_node(fdt);
+	if (node < 0) {
+		return false;
+	}
+
+	return !!(fdt_get_status(node) & DT_SECURE);
+}
+
+/*
+ * Get the stgen base address.
+ * @return: address of stgen on success, and NULL value on failure.
+ */
+uintptr_t fdt_get_stgen_base(void)
+{
+	int node;
+	const fdt32_t *cuint;
+	void *fdt;
+
+	if (fdt_get_address(&fdt) == 0) {
+		return 0;
+	}
+
+	node = fdt_node_offset_by_compatible(fdt, -1, DT_STGEN_COMPAT);
+	if (node < 0) {
+		return 0;
+	}
+
+	cuint = fdt_getprop(fdt, node, "reg", NULL);
+	if (cuint == NULL) {
+		return 0;
+	}
+
+	return fdt32_to_cpu(*cuint);
+}
+
+/*
+ * Get the clock ID of the given node in device tree.
+ * @param node: node offset
+ * @return: Clock ID on success, and a negative FDT/ERRNO error code on failure.
+ */
+int fdt_get_clock_id(int node)
+{
+	const fdt32_t *cuint;
+	void *fdt;
+
+	if (fdt_get_address(&fdt) == 0) {
+		return -ENOENT;
+	}
+
+	cuint = fdt_getprop(fdt, node, "clocks", NULL);
+	if (cuint == NULL) {
+		return -FDT_ERR_NOTFOUND;
+	}
+
+	cuint++;
+	return (int)fdt32_to_cpu(*cuint);
+}

drivers/st/ddr/stm32mp1_ddr.c

@@ -14,13 +14,10 @@
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
 #include <drivers/st/stm32mp_pmic.h>
-#include <drivers/st/stm32mp1_clk.h>
 #include <drivers/st/stm32mp1_ddr.h>
 #include <drivers/st/stm32mp1_ddr_regs.h>
 #include <drivers/st/stm32mp1_pwr.h>
 #include <drivers/st/stm32mp1_ram.h>
-#include <drivers/st/stm32mp1_rcc.h>
-#include <dt-bindings/clock/stm32mp1-clks.h>
 #include <lib/mmio.h>
 #include <plat/common/platform.h>
 
@@ -32,7 +29,7 @@ struct reg_desc {
 
 #define INVALID_OFFSET	0xFFU
 
-#define TIMESLOT_1US	(plat_get_syscnt_freq2() / 1000000U)
+#define TIMEOUT_US_1S	1000000U
 
 #define DDRCTL_REG(x, y)					\
 	{							\
@@ -327,49 +324,43 @@ static void stm32mp1_ddrphy_idone_wait(struct stm32mp1_ddrphy *phy)
 {
 	uint32_t pgsr;
 	int error = 0;
-	unsigned long start;
-	unsigned long time0, time;
-
-	start = get_timer(0);
-	time0 = start;
+	uint64_t timeout = timeout_init_us(TIMEOUT_US_1S);
 
 	do {
 		pgsr = mmio_read_32((uintptr_t)&phy->pgsr);
-		time = get_timer(start);
-		if (time != time0) {
-			VERBOSE("  > [0x%lx] pgsr = 0x%x &\n",
-				(uintptr_t)&phy->pgsr, pgsr);
-			VERBOSE("    [0x%lx] pir = 0x%x (time=%lx)\n",
-				(uintptr_t)&phy->pir,
-				mmio_read_32((uintptr_t)&phy->pir),
-				time);
-		}
 
-		time0 = time;
-		if (time > plat_get_syscnt_freq2()) {
+		VERBOSE("  > [0x%lx] pgsr = 0x%x &\n",
+			(uintptr_t)&phy->pgsr, pgsr);
+
+		if (timeout_elapsed(timeout)) {
 			panic();
 		}
+
 		if ((pgsr & DDRPHYC_PGSR_DTERR) != 0U) {
 			VERBOSE("DQS Gate Trainig Error\n");
 			error++;
 		}
+
 		if ((pgsr & DDRPHYC_PGSR_DTIERR) != 0U) {
 			VERBOSE("DQS Gate Trainig Intermittent Error\n");
 			error++;
 		}
+
 		if ((pgsr & DDRPHYC_PGSR_DFTERR) != 0U) {
 			VERBOSE("DQS Drift Error\n");
 			error++;
 		}
+
 		if ((pgsr & DDRPHYC_PGSR_RVERR) != 0U) {
 			VERBOSE("Read Valid Training Error\n");
 			error++;
 		}
+
 		if ((pgsr & DDRPHYC_PGSR_RVEIRR) != 0U) {
 			VERBOSE("Read Valid Training Intermittent Error\n");
 			error++;
 		}
-	} while ((pgsr & DDRPHYC_PGSR_IDONE) == 0U && error == 0);
+	} while (((pgsr & DDRPHYC_PGSR_IDONE) == 0U) && (error == 0));
 	VERBOSE("\n[0x%lx] pgsr = 0x%x\n",
 		(uintptr_t)&phy->pgsr, pgsr);
 }
@@ -401,21 +392,19 @@ static void stm32mp1_start_sw_done(struct stm32mp1_ddrctl *ctl)
 /* Wait quasi dynamic register update */
 static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
 {
-	unsigned long start;
+	uint64_t timeout;
 	uint32_t swstat;
 
 	mmio_setbits_32((uintptr_t)&ctl->swctl, DDRCTRL_SWCTL_SW_DONE);
 	VERBOSE("[0x%lx] swctl = 0x%x\n",
 		(uintptr_t)&ctl->swctl, mmio_read_32((uintptr_t)&ctl->swctl));
 
-	start = get_timer(0);
+	timeout = timeout_init_us(TIMEOUT_US_1S);
 	do {
 		swstat = mmio_read_32((uintptr_t)&ctl->swstat);
 		VERBOSE("[0x%lx] swstat = 0x%x ",
 			(uintptr_t)&ctl->swstat, swstat);
-		VERBOSE("timer in ms 0x%x = start 0x%lx\r",
-			get_timer(0), start);
-		if (get_timer(start) > plat_get_syscnt_freq2()) {
+		if (timeout_elapsed(timeout)) {
 			panic();
 		}
 	} while ((swstat & DDRCTRL_SWSTAT_SW_DONE_ACK) == 0U);
@@ -427,22 +416,21 @@ static void stm32mp1_wait_sw_done_ack(struct stm32mp1_ddrctl *ctl)
 /* Wait quasi dynamic register update */
 static void stm32mp1_wait_operating_mode(struct ddr_info *priv, uint32_t mode)
 {
-	unsigned long start;
+	uint64_t timeout;
 	uint32_t stat;
-	uint32_t operating_mode;
-	uint32_t selref_type;
 	int break_loop = 0;
 
-	start = get_timer(0);
+	timeout = timeout_init_us(TIMEOUT_US_1S);
 	for ( ; ; ) {
+		uint32_t operating_mode;
+		uint32_t selref_type;
+
 		stat = mmio_read_32((uintptr_t)&priv->ctl->stat);
 		operating_mode = stat & DDRCTRL_STAT_OPERATING_MODE_MASK;
 		selref_type = stat & DDRCTRL_STAT_SELFREF_TYPE_MASK;
 		VERBOSE("[0x%lx] stat = 0x%x\n",
 			(uintptr_t)&priv->ctl->stat, stat);
-		VERBOSE("timer in ms 0x%x = start 0x%lx\r",
-			get_timer(0), start);
-		if (get_timer(start) > plat_get_syscnt_freq2()) {
+		if (timeout_elapsed(timeout)) {
 			panic();
 		}
 
@@ -639,7 +627,7 @@ static void stm32mp1_ddr3_dll_off(struct ddr_info *priv)
 	 */
 
 	/* Change Bypass Mode Frequency Range */
-	if (stm32mp1_clk_get_rate(DDRPHYC) < 100000000U) {
+	if (stm32mp_clk_get_rate(DDRPHYC) < 100000000U) {
 		mmio_clrbits_32((uintptr_t)&priv->phy->dllgcr,
 				DDRPHYC_DLLGCR_BPS200);
 	} else {
@@ -712,7 +700,7 @@ static void stm32mp1_refresh_restore(struct stm32mp1_ddrctl *ctl,
 
 static int board_ddr_power_init(enum ddr_type ddr_type)
 {
-	if (dt_check_pmic()) {
+	if (dt_pmic_status() > 0) {
 		return pmic_ddr_power_init(ddr_type);
 	}
 

drivers/st/ddr/stm32mp1_ddr_helpers.c

 /*
- * Copyright (c) 2017-2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2017-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -7,15 +7,18 @@
 #include <platform_def.h>
 
 #include <drivers/st/stm32mp1_ddr_helpers.h>
-#include <drivers/st/stm32mp1_rcc.h>
 #include <lib/mmio.h>
 
 void ddr_enable_clock(void)
 {
-	mmio_setbits_32(RCC_BASE + RCC_DDRITFCR,
+	stm32mp1_clk_rcc_regs_lock();
+
+	mmio_setbits_32(stm32mp_rcc_base() + RCC_DDRITFCR,
 			RCC_DDRITFCR_DDRC1EN |
 			RCC_DDRITFCR_DDRC2EN |
 			RCC_DDRITFCR_DDRPHYCEN |
 			RCC_DDRITFCR_DDRPHYCAPBEN |
 			RCC_DDRITFCR_DDRCAPBEN);
+
+	stm32mp1_clk_rcc_regs_unlock();
 }

drivers/st/ddr/stm32mp1_ram.c

@@ -12,12 +12,9 @@
 
 #include <arch_helpers.h>
 #include <common/debug.h>
-#include <drivers/st/stm32mp1_clk.h>
 #include <drivers/st/stm32mp1_ddr.h>
 #include <drivers/st/stm32mp1_ddr_helpers.h>
 #include <drivers/st/stm32mp1_ram.h>
-#include <drivers/st/stm32mp1_rcc.h>
-#include <dt-bindings/clock/stm32mp1-clks.h>
 #include <lib/mmio.h>
 
 #define DDR_PATTERN	0xAAAAAAAAU
@@ -31,7 +28,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed)
 
 	ddr_enable_clock();
 
-	ddrphy_clk = stm32mp1_clk_get_rate(DDRPHYC);
+	ddrphy_clk = stm32mp_clk_get_rate(DDRPHYC);
 
 	VERBOSE("DDR: mem_speed (%d kHz), RCC %ld kHz\n",
 		mem_speed, ddrphy_clk / 1000U);
@@ -65,10 +62,10 @@ static uint32_t ddr_test_data_bus(void)
 	uint32_t pattern;
 
 	for (pattern = 1U; pattern != 0U; pattern <<= 1) {
-		mmio_write_32(STM32MP1_DDR_BASE, pattern);
+		mmio_write_32(STM32MP_DDR_BASE, pattern);
 
-		if (mmio_read_32(STM32MP1_DDR_BASE) != pattern) {
-			return (uint32_t)STM32MP1_DDR_BASE;
+		if (mmio_read_32(STM32MP_DDR_BASE) != pattern) {
+			return (uint32_t)STM32MP_DDR_BASE;
 		}
 	}
 
@@ -92,44 +89,44 @@ static uint32_t ddr_test_addr_bus(void)
 	/* Write the default pattern at each of the power-of-two offsets. */
 	for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
 	     offset <<= 1) {
-		mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)offset,
+		mmio_write_32(STM32MP_DDR_BASE + (uint32_t)offset,
 			      DDR_PATTERN);
 	}
 
 	/* Check for address bits stuck high. */
-	mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset,
+	mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
 		      DDR_ANTIPATTERN);
 
 	for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
 	     offset <<= 1) {
-		if (mmio_read_32(STM32MP1_DDR_BASE + (uint32_t)offset) !=
+		if (mmio_read_32(STM32MP_DDR_BASE + (uint32_t)offset) !=
 		    DDR_PATTERN) {
-			return (uint32_t)(STM32MP1_DDR_BASE + offset);
+			return (uint32_t)(STM32MP_DDR_BASE + offset);
 		}
 	}
 
-	mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN);
+	mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN);
 
 	/* Check for address bits stuck low or shorted. */
 	for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U;
 	     testoffset <<= 1) {
-		mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset,
+		mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
 			      DDR_ANTIPATTERN);
 
-		if (mmio_read_32(STM32MP1_DDR_BASE) != DDR_PATTERN) {
-			return STM32MP1_DDR_BASE;
+		if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
+			return STM32MP_DDR_BASE;
 		}
 
 		for (offset = sizeof(uint32_t); (offset & addressmask) != 0U;
 		     offset <<= 1) {
-			if ((mmio_read_32(STM32MP1_DDR_BASE +
+			if ((mmio_read_32(STM32MP_DDR_BASE +
 					  (uint32_t)offset) != DDR_PATTERN) &&
 			    (offset != testoffset)) {
-				return (uint32_t)(STM32MP1_DDR_BASE + offset);
+				return (uint32_t)(STM32MP_DDR_BASE + offset);
 			}
 		}
 
-		mmio_write_32(STM32MP1_DDR_BASE + (uint32_t)testoffset,
+		mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset,
 			      DDR_PATTERN);
 	}
 
@@ -147,13 +144,13 @@ static uint32_t ddr_check_size(void)
 {
 	uint32_t offset = sizeof(uint32_t);
 
-	mmio_write_32(STM32MP1_DDR_BASE, DDR_PATTERN);
+	mmio_write_32(STM32MP_DDR_BASE, DDR_PATTERN);
 
-	while (offset < STM32MP1_DDR_MAX_SIZE) {
-		mmio_write_32(STM32MP1_DDR_BASE + offset, DDR_ANTIPATTERN);
+	while (offset < STM32MP_DDR_MAX_SIZE) {
+		mmio_write_32(STM32MP_DDR_BASE + offset, DDR_ANTIPATTERN);
 		dsb();
 
-		if (mmio_read_32(STM32MP1_DDR_BASE) != DDR_PATTERN) {
+		if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) {
 			break;
 		}
 
@@ -171,7 +168,7 @@ static int stm32mp1_ddr_setup(void)
 	int ret;
 	struct stm32mp1_ddr_config config;
 	int node, len;
-	uint32_t tamp_clk_off = 0, uret, idx;
+	uint32_t uret, idx;
 	void *fdt;
 
 #define PARAM(x, y)							\
@@ -240,19 +237,6 @@ static int stm32mp1_ddr_setup(void)
 		}
 	}
 
-	if (!stm32mp1_clk_is_enabled(RTCAPB)) {
-		tamp_clk_off = 1;
-		if (stm32mp1_clk_enable(RTCAPB) != 0) {
-			return -EINVAL;
-		}
-	}
-
-	if (tamp_clk_off != 0U) {
-		if (stm32mp1_clk_disable(RTCAPB) != 0) {
-			return -EINVAL;
-		}
-	}
-
 	/* Disable axidcg clock gating during init */
 	mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_AXIDCGEN);
 
@@ -301,12 +285,12 @@ int stm32mp1_ddr_probe(void)
 
 	VERBOSE("STM32MP DDR probe\n");
 
-	priv->ctl = (struct stm32mp1_ddrctl *)DDRCTRL_BASE;
-	priv->phy = (struct stm32mp1_ddrphy *)DDRPHYC_BASE;
-	priv->pwr = PWR_BASE;
-	priv->rcc = RCC_BASE;
+	priv->ctl = (struct stm32mp1_ddrctl *)stm32mp_ddrctrl_base();
+	priv->phy = (struct stm32mp1_ddrphy *)stm32mp_ddrphyc_base();
+	priv->pwr = stm32mp_pwr_base();
+	priv->rcc = stm32mp_rcc_base();
 
-	priv->info.base = STM32MP1_DDR_BASE;
+	priv->info.base = STM32MP_DDR_BASE;
 	priv->info.size = 0;
 
 	return stm32mp1_ddr_setup();

drivers/st/gpio/stm32_gpio.c

@@ -15,8 +15,7 @@
 #include <common/bl_common.h>
 #include <common/debug.h>
 #include <drivers/st/stm32_gpio.h>
-#include <drivers/st/stm32mp1_clk.h>
-#include <drivers/st/stm32mp1_clkfunc.h>
+#include <drivers/st/stm32mp_clkfunc.h>
 #include <lib/mmio.h>
 #include <lib/utils_def.h>
 
@@ -208,7 +207,7 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
 
 	assert(pin <= GPIO_PIN_MAX);
 
-	stm32mp1_clk_enable(clock);
+	stm32mp_clk_enable(clock);
 
 	mmio_clrbits_32(base + GPIO_MODE_OFFSET,
 			((uint32_t)GPIO_MODE_MASK << (pin << 1)));
@@ -254,17 +253,17 @@ void set_gpio(uint32_t bank, uint32_t pin, uint32_t mode, uint32_t speed,
 	VERBOSE("GPIO %u mode alternate high to 0x%x\n", bank,
 		mmio_read_32(base + GPIO_AFRH_OFFSET));
 
-	stm32mp1_clk_disable((unsigned long)clock);
+	stm32mp_clk_disable(clock);
 }
 
 void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
 {
 	uintptr_t base = stm32_get_gpio_bank_base(bank);
-	int clock = stm32_get_gpio_bank_clock(bank);
+	unsigned long clock = stm32_get_gpio_bank_clock(bank);
 
 	assert(pin <= GPIO_PIN_MAX);
 
-	stm32mp1_clk_enable((unsigned long)clock);
+	stm32mp_clk_enable(clock);
 
 	if (secure) {
 		mmio_setbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
@@ -272,5 +271,5 @@ void set_gpio_secure_cfg(uint32_t bank, uint32_t pin, bool secure)
 		mmio_clrbits_32(base + GPIO_SECR_OFFSET, BIT(pin));
 	}
 
-	stm32mp1_clk_disable((unsigned long)clock);
+	stm32mp_clk_disable(clock);
 }

drivers/st/mmc/stm32_sdmmc2.c

@@ -19,11 +19,7 @@
 #include <drivers/mmc.h>
 #include <drivers/st/stm32_gpio.h>
 #include <drivers/st/stm32_sdmmc2.h>
-#include <drivers/st/stm32mp1_clk.h>
-#include <drivers/st/stm32mp1_rcc.h>
-#include <drivers/st/stm32mp1_reset.h>
-#include <dt-bindings/clock/stm32mp1-clks.h>
-#include <dt-bindings/reset/stm32mp1-resets.h>
+#include <drivers/st/stm32mp_reset.h>
 #include <lib/mmio.h>
 #include <lib/utils.h>
 #include <plat/common/platform.h>
@@ -123,8 +119,8 @@
 					 SDMMC_STAR_IDMATE   | \
 					 SDMMC_STAR_IDMABTC)
 
-#define TIMEOUT_10_MS			(plat_get_syscnt_freq2() / 100U)
-#define TIMEOUT_1_S			plat_get_syscnt_freq2()
+#define TIMEOUT_US_10_MS		10000U
+#define TIMEOUT_US_1_S			1000000U
 
 #define DT_SDMMC2_COMPAT		"st,stm32-sdmmc2"
 
@@ -159,7 +155,7 @@ static void stm32_sdmmc2_init(void)
 	uintptr_t base = sdmmc2_params.reg_base;
 
 	clock_div = div_round_up(sdmmc2_params.clk_rate,
-				 STM32MP1_MMC_INIT_FREQ * 2);
+				 STM32MP_MMC_INIT_FREQ * 2);
 
 	mmio_write_32(base + SDMMC_CLKCR, SDMMC_CLKCR_HWFC_EN | clock_div |
 		      sdmmc2_params.negedge |
@@ -185,11 +181,12 @@ static int stm32_sdmmc2_stop_transfer(void)
 
 static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
 {
+	uint64_t timeout;
 	uint32_t flags_cmd, status;
 	uint32_t flags_data = 0;
 	int err = 0;
 	uintptr_t base = sdmmc2_params.reg_base;
-	unsigned int cmd_reg, arg_reg, start;
+	unsigned int cmd_reg, arg_reg;
 
 	if (cmd == NULL) {
 		return -EINVAL;
@@ -272,10 +269,10 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
 
 	status = mmio_read_32(base + SDMMC_STAR);
 
-	start = get_timer(0);
+	timeout = timeout_init_us(TIMEOUT_US_10_MS);
 
 	while ((status & flags_cmd) == 0U) {
-		if (get_timer(start) > TIMEOUT_10_MS) {
+		if (timeout_elapsed(timeout)) {
 			err = -ETIMEDOUT;
 			ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
 			      __func__, cmd->cmd_idx, status);
@@ -339,10 +336,10 @@ static int stm32_sdmmc2_send_cmd_req(struct mmc_cmd *cmd)
 
 	status = mmio_read_32(base + SDMMC_STAR);
 
-	start = get_timer(0);
+	timeout = timeout_init_us(TIMEOUT_US_10_MS);
 
 	while ((status & flags_data) == 0U) {
-		if (get_timer(start) > TIMEOUT_10_MS) {
+		if (timeout_elapsed(timeout)) {
 			ERROR("%s: timeout 10ms (cmd = %d,status = %x)\n",
 			      __func__, cmd->cmd_idx, status);
 			err = -ETIMEDOUT;
@@ -364,7 +361,7 @@ err_exit:
 	mmio_write_32(base + SDMMC_ICR, SDMMC_STATIC_FLAGS);
 	mmio_clrbits_32(base + SDMMC_CMDR, SDMMC_CMDR_CMDTRANS);
 
-	if (err != 0) {
+	if ((err != 0) && ((status & SDMMC_STAR_DPSMACT) != 0U)) {
 		int ret_stop = stm32_sdmmc2_stop_transfer();
 
 		if (ret_stop != 0) {
@@ -429,15 +426,15 @@ static int stm32_sdmmc2_set_ios(unsigned int clk, unsigned int width)
 
 	if (sdmmc2_params.device_info->mmc_dev_type == MMC_IS_EMMC) {
 		if (max_bus_freq >= 52000000U) {
-			max_freq = STM32MP1_EMMC_HIGH_SPEED_MAX_FREQ;
+			max_freq = STM32MP_EMMC_HIGH_SPEED_MAX_FREQ;
 		} else {
-			max_freq = STM32MP1_EMMC_NORMAL_SPEED_MAX_FREQ;
+			max_freq = STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ;
 		}
 	} else {
 		if (max_bus_freq >= 50000000U) {
-			max_freq = STM32MP1_SD_HIGH_SPEED_MAX_FREQ;
+			max_freq = STM32MP_SD_HIGH_SPEED_MAX_FREQ;
 		} else {
-			max_freq = STM32MP1_SD_NORMAL_SPEED_MAX_FREQ;
+			max_freq = STM32MP_SD_NORMAL_SPEED_MAX_FREQ;
 		}
 	}
 
@@ -523,7 +520,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
 	uint32_t *buffer;
 	uintptr_t base = sdmmc2_params.reg_base;
 	uintptr_t fifo_reg = base + SDMMC_FIFOR;
-	unsigned int start;
+	uint64_t timeout;
 	int ret;
 
 	/* Assert buf is 4 bytes aligned */
@@ -541,7 +538,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
 		flags |= SDMMC_STAR_DBCKEND;
 	}
 
-	start = get_timer(0);
+	timeout = timeout_init_us(TIMEOUT_US_1_S);
 
 	do {
 		status = mmio_read_32(base + SDMMC_STAR);
@@ -563,7 +560,7 @@ static int stm32_sdmmc2_read(int lba, uintptr_t buf, size_t size)
 			return -EIO;
 		}
 
-		if (get_timer(start) > TIMEOUT_1_S) {
+		if (timeout_elapsed(timeout)) {
 			ERROR("%s: timeout 1s (status = %x)\n",
 			      __func__, status);
 			mmio_write_32(base + SDMMC_ICR,
@@ -705,8 +702,6 @@ unsigned long long stm32_sdmmc2_mmc_get_device_size(void)
 
 int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
 {
-	int ret;
-
 	assert((params != NULL) &&
 	       ((params->reg_base & MMC_BLOCK_MASK) == 0U) &&
 	       ((params->bus_width == MMC_BUS_WIDTH_1) ||
@@ -720,19 +715,14 @@ int stm32_sdmmc2_mmc_init(struct stm32_sdmmc2_params *params)
 		return -ENOMEM;
 	}
 
-	ret = stm32mp1_clk_enable(sdmmc2_params.clock_id);
-	if (ret != 0) {
-		ERROR("%s: clock %d failed\n", __func__,
-		      sdmmc2_params.clock_id);
-		return ret;
-	}
+	stm32mp_clk_enable(sdmmc2_params.clock_id);
 
-	stm32mp1_reset_assert(sdmmc2_params.reset_id);
+	stm32mp_reset_assert(sdmmc2_params.reset_id);
 	udelay(2);
-	stm32mp1_reset_deassert(sdmmc2_params.reset_id);
+	stm32mp_reset_deassert(sdmmc2_params.reset_id);
 	mdelay(1);
 
-	sdmmc2_params.clk_rate = stm32mp1_clk_get_rate(sdmmc2_params.clock_id);
+	sdmmc2_params.clk_rate = stm32mp_clk_get_rate(sdmmc2_params.clock_id);
 
 	return mmc_init(&stm32_sdmmc2_ops, sdmmc2_params.clk_rate,
 			sdmmc2_params.bus_width, sdmmc2_params.flags,

drivers/st/pmic/stm32mp_pmic.c

@@ -5,7 +5,6 @@
  */
 
 #include <errno.h>
-#include <stdbool.h>
 
 #include <libfdt.h>
 
@@ -13,20 +12,12 @@
 
 #include <common/debug.h>
 #include <drivers/delay_timer.h>
+#include <drivers/st/stm32_i2c.h>
 #include <drivers/st/stm32mp_pmic.h>
-#include <drivers/st/stm32_gpio.h>
-#include <drivers/st/stm32mp1_clk.h>
 #include <drivers/st/stpmic1.h>
 #include <lib/mmio.h>
 #include <lib/utils_def.h>
 
-/* I2C Timing hard-coded value, for I2C clock source is HSI at 64MHz */
-#define I2C_TIMING			0x10D07DB5
-
-#define I2C_TIMEOUT			0xFFFFF
-
-#define MASK_RESET_BUCK3		BIT(2)
-
 #define STPMIC1_LDO12356_OUTPUT_MASK	(uint8_t)(GENMASK(6, 2))
 #define STPMIC1_LDO12356_OUTPUT_SHIFT	2
 #define STPMIC1_LDO3_MODE		(uint8_t)(BIT(7))
@@ -46,25 +37,29 @@ static int dt_get_pmic_node(void *fdt)
 	return fdt_node_offset_by_compatible(fdt, -1, "st,stpmic1");
 }
 
-bool dt_check_pmic(void)
+int dt_pmic_status(void)
 {
 	int node;
 	void *fdt;
 
 	if (fdt_get_address(&fdt) == 0) {
-		return false;
+		return -ENOENT;
 	}
 
 	node = dt_get_pmic_node(fdt);
-	if (node < 0) {
-		VERBOSE("%s: No PMIC node found in DT\n", __func__);
-		return false;
+	if (node <= 0) {
+		return -FDT_ERR_NOTFOUND;
 	}
 
 	return fdt_get_status(node);
 }
 
-static int dt_pmic_i2c_config(struct dt_node_info *i2c_info)
+/*
+ * Get PMIC and its I2C bus configuration from the device tree.
+ * Return 0 on success, negative on error, 1 if no PMIC node is found.
+ */
+static int dt_pmic_i2c_config(struct dt_node_info *i2c_info,
+			      struct stm32_i2c_init_s *init)
 {
 	int pmic_node, i2c_node;
 	void *fdt;
@@ -76,7 +71,7 @@ static int dt_pmic_i2c_config(struct dt_node_info *i2c_info)
 
 	pmic_node = dt_get_pmic_node(fdt);
 	if (pmic_node < 0) {
-		return -FDT_ERR_NOTFOUND;
+		return 1;
 	}
 
 	cuint = fdt_getprop(fdt, pmic_node, "reg", NULL);
@@ -99,10 +94,10 @@ static int dt_pmic_i2c_config(struct dt_node_info *i2c_info)
 		return -FDT_ERR_NOTFOUND;
 	}
 
-	return dt_set_pinctrl_config(i2c_node);
+	return stm32_i2c_get_setup_from_fdt(fdt, i2c_node, init);
 }
 
-int dt_pmic_enable_boot_on_regulators(void)
+int dt_pmic_configure_boot_on_regulators(void)
 {
 	int pmic_node, regulators_node, regulator_node;
 	void *fdt;
@@ -120,14 +115,40 @@ int dt_pmic_enable_boot_on_regulators(void)
 
 	fdt_for_each_subnode(regulator_node, fdt, regulators_node) {
 		const fdt32_t *cuint;
-		const char *node_name;
+		const char *node_name = fdt_get_name(fdt, regulator_node, NULL);
 		uint16_t voltage;
-
+		int status;
+
+#if defined(IMAGE_BL2)
+		if ((fdt_getprop(fdt, regulator_node, "regulator-boot-on",
+				 NULL) == NULL) &&
+		    (fdt_getprop(fdt, regulator_node, "regulator-always-on",
+				 NULL) == NULL)) {
+#else
 		if (fdt_getprop(fdt, regulator_node, "regulator-boot-on",
 				NULL) == NULL) {
+#endif
 			continue;
 		}
 
+		if (fdt_getprop(fdt, regulator_node, "regulator-pull-down",
+				NULL) != NULL) {
+
+			status = stpmic1_regulator_pull_down_set(node_name);
+			if (status != 0) {
+				return status;
+			}
+		}
+
+		if (fdt_getprop(fdt, regulator_node, "st,mask-reset",
+				NULL) != NULL) {
+
+			status = stpmic1_regulator_mask_reset_set(node_name);
+			if (status != 0) {
+				return status;
+			}
+		}
+
 		cuint = fdt_getprop(fdt, regulator_node,
 				    "regulator-min-microvolt", NULL);
 		if (cuint == NULL) {
@@ -136,17 +157,13 @@ int dt_pmic_enable_boot_on_regulators(void)
 
 		/* DT uses microvolts, whereas driver awaits millivolts */
 		voltage = (uint16_t)(fdt32_to_cpu(*cuint) / 1000U);
-		node_name = fdt_get_name(fdt, regulator_node, NULL);
-
-		if (stpmic1_is_regulator_enabled(node_name) == 0U) {
-			int status;
 
-			status = stpmic1_regulator_voltage_set(node_name,
-							       voltage);
-			if (status != 0) {
-				return status;
-			}
+		status = stpmic1_regulator_voltage_set(node_name, voltage);
+		if (status != 0) {
+			return status;
+		}
 
+		if (stpmic1_is_regulator_enabled(node_name) == 0U) {
 			status = stpmic1_regulator_enable(node_name);
 			if (status != 0) {
 				return status;
@@ -157,77 +174,77 @@ int dt_pmic_enable_boot_on_regulators(void)
 	return 0;
 }
 
-void initialize_pmic_i2c(void)
+bool initialize_pmic_i2c(void)
 {
 	int ret;
 	struct dt_node_info i2c_info;
+	struct i2c_handle_s *i2c = &i2c_handle;
+	struct stm32_i2c_init_s i2c_init;
 
-	if (dt_pmic_i2c_config(&i2c_info) != 0) {
-		ERROR("I2C configuration failed\n");
+	ret = dt_pmic_i2c_config(&i2c_info, &i2c_init);
+	if (ret < 0) {
+		ERROR("I2C configuration failed %d\n", ret);
 		panic();
 	}
 
-	if (stm32mp1_clk_enable((uint32_t)i2c_info.clock) < 0) {
-		ERROR("I2C clock enable failed\n");
-		panic();
+	if (ret != 0) {
+		return false;
 	}
 
 	/* Initialize PMIC I2C */
-	i2c_handle.i2c_base_addr		= i2c_info.base;
-	i2c_handle.i2c_init.timing		= I2C_TIMING;
-	i2c_handle.i2c_init.own_address1	= pmic_i2c_addr;
-	i2c_handle.i2c_init.addressing_mode	= I2C_ADDRESSINGMODE_7BIT;
-	i2c_handle.i2c_init.dual_address_mode	= I2C_DUALADDRESS_DISABLE;
-	i2c_handle.i2c_init.own_address2	= 0;
-	i2c_handle.i2c_init.own_address2_masks	= I2C_OAR2_OA2NOMASK;
-	i2c_handle.i2c_init.general_call_mode	= I2C_GENERALCALL_DISABLE;
-	i2c_handle.i2c_init.no_stretch_mode	= I2C_NOSTRETCH_DISABLE;
-
-	ret = stm32_i2c_init(&i2c_handle);
+	i2c->i2c_base_addr		= i2c_info.base;
+	i2c->dt_status			= i2c_info.status;
+	i2c->clock			= i2c_info.clock;
+	i2c_init.own_address1		= pmic_i2c_addr;
+	i2c_init.addressing_mode	= I2C_ADDRESSINGMODE_7BIT;
+	i2c_init.dual_address_mode	= I2C_DUALADDRESS_DISABLE;
+	i2c_init.own_address2		= 0;
+	i2c_init.own_address2_masks	= I2C_OAR2_OA2NOMASK;
+	i2c_init.general_call_mode	= I2C_GENERALCALL_DISABLE;
+	i2c_init.no_stretch_mode	= I2C_NOSTRETCH_DISABLE;
+	i2c_init.analog_filter		= 1;
+	i2c_init.digital_filter_coef	= 0;
+
+	ret = stm32_i2c_init(i2c, &i2c_init);
 	if (ret != 0) {
 		ERROR("Cannot initialize I2C %x (%d)\n",
-		      i2c_handle.i2c_base_addr, ret);
+		      i2c->i2c_base_addr, ret);
 		panic();
 	}
 
-	ret = stm32_i2c_config_analog_filter(&i2c_handle,
-					     I2C_ANALOGFILTER_ENABLE);
-	if (ret != 0) {
-		ERROR("Cannot initialize I2C analog filter (%d)\n", ret);
+	if (!stm32_i2c_is_device_ready(i2c, pmic_i2c_addr, 1,
+				       I2C_TIMEOUT_BUSY_MS)) {
+		ERROR("I2C device not ready\n");
 		panic();
 	}
 
-	ret = stm32_i2c_is_device_ready(&i2c_handle, (uint16_t)pmic_i2c_addr, 1,
-					I2C_TIMEOUT);
-	if (ret != 0) {
-		ERROR("I2C device not ready (%d)\n", ret);
-		panic();
-	}
+	stpmic1_bind_i2c(i2c, (uint16_t)pmic_i2c_addr);
 
-	stpmic1_bind_i2c(&i2c_handle, (uint16_t)pmic_i2c_addr);
+	return true;
 }
 
 void initialize_pmic(void)
 {
-	int status;
-	uint8_t read_val;
+	unsigned long pmic_version;
 
-	initialize_pmic_i2c();
+	if (!initialize_pmic_i2c()) {
+		VERBOSE("No PMIC\n");
+		return;
+	}
 
-	status = stpmic1_register_read(VERSION_STATUS_REG, &read_val);
-	if (status != 0) {
+	if (stpmic1_get_version(&pmic_version) != 0) {
+		ERROR("Failed to access PMIC\n");
 		panic();
 	}
 
-	INFO("PMIC version = 0x%x\n", read_val);
+	INFO("PMIC version = 0x%02lx\n", pmic_version);
+	stpmic1_dump_regulators();
 
-	/* Keep VDD on during the reset cycle */
-	status = stpmic1_register_update(MASK_RESET_BUCK_REG,
-					MASK_RESET_BUCK3,
-					MASK_RESET_BUCK3);
-	if (status != 0) {
+#if defined(IMAGE_BL2)
+	if (dt_pmic_configure_boot_on_regulators() != 0) {
 		panic();
-	}
+	};
+#endif
 }
 
 int pmic_ddr_power_init(enum ddr_type ddr_type)

drivers/st/pmic/stpmic1.c

@@ -8,7 +8,8 @@
 
 #include <common/debug.h>
 #include <drivers/st/stpmic1.h>
-#include <plat/common/platform.h>
+
+#define I2C_TIMEOUT_MS		25
 
 struct regul_struct {
 	const char *dt_node_name;
@@ -677,8 +678,9 @@ int stpmic1_regulator_voltage_get(const char *name)
 int stpmic1_register_read(uint8_t register_id,  uint8_t *value)
 {
 	return stm32_i2c_mem_read(pmic_i2c_handle, pmic_i2c_addr,
-				  (uint16_t)register_id, I2C_MEMADD_SIZE_8BIT,
-				  value, 1, 100000);
+				  (uint16_t)register_id,
+				  I2C_MEMADD_SIZE_8BIT, value,
+				  1, I2C_TIMEOUT_MS);
 }
 
 int stpmic1_register_write(uint8_t register_id, uint8_t value)
@@ -687,7 +689,8 @@ int stpmic1_register_write(uint8_t register_id, uint8_t value)
 
 	status = stm32_i2c_mem_write(pmic_i2c_handle, pmic_i2c_addr,
 				     (uint16_t)register_id,
-				     I2C_MEMADD_SIZE_8BIT, &value, 1, 100000);
+				     I2C_MEMADD_SIZE_8BIT, &value,
+				     1, I2C_TIMEOUT_MS);
 
 #if ENABLE_ASSERTIONS
 	if (status != 0) {

drivers/st/reset/stm32mp1_reset.c

 /*
- * Copyright (c) 2018, STMicroelectronics - All Rights Reserved
+ * Copyright (c) 2018-2019, STMicroelectronics - All Rights Reserved
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,32 +10,53 @@
 
 #include <common/bl_common.h>
 #include <common/debug.h>
-#include <drivers/st/stm32mp1_rcc.h>
-#include <drivers/st/stm32mp1_reset.h>
+#include <drivers/delay_timer.h>
+#include <drivers/st/stm32mp_reset.h>
 #include <lib/mmio.h>
 #include <lib/utils_def.h>
 
-#define RST_CLR_OFFSET	4U
+#define RESET_TIMEOUT_US_1MS	U(1000)
 
-void stm32mp1_reset_assert(uint32_t id)
+static uint32_t id2reg_offset(unsigned int reset_id)
 {
-	uint32_t offset = (id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t);
-	uint32_t bit = id % (uint32_t)__LONG_BIT;
+	return ((reset_id & GENMASK(31, 5)) >> 5) * sizeof(uint32_t);
+}
 
-	mmio_write_32(RCC_BASE + offset, BIT(bit));
-	while ((mmio_read_32(RCC_BASE + offset) & BIT(bit)) == 0U) {
-		;
-	}
+static uint8_t id2reg_bit_pos(unsigned int reset_id)
+{
+	return (uint8_t)(reset_id & GENMASK(4, 0));
 }
 
-void stm32mp1_reset_deassert(uint32_t id)
+void stm32mp_reset_assert(uint32_t id)
 {
-	uint32_t offset = ((id / (uint32_t)__LONG_BIT) * sizeof(uintptr_t)) +
-			  RST_CLR_OFFSET;
-	uint32_t bit = id % (uint32_t)__LONG_BIT;
+	uint32_t offset = id2reg_offset(id);
+	uint32_t bitmsk = BIT(id2reg_bit_pos(id));
+	uint64_t timeout_ref;
+	uintptr_t rcc_base = stm32mp_rcc_base();
+
+	mmio_write_32(rcc_base + offset, bitmsk);
+
+	timeout_ref = timeout_init_us(RESET_TIMEOUT_US_1MS);
+	while ((mmio_read_32(rcc_base + offset) & bitmsk) == 0U) {
+		if (timeout_elapsed(timeout_ref)) {
+			panic();
+		}
+	}
+}
 
-	mmio_write_32(RCC_BASE + offset, BIT(bit));
-	while ((mmio_read_32(RCC_BASE + offset) & BIT(bit)) != 0U) {
-		;
+void stm32mp_reset_deassert(uint32_t id)
+{
+	uint32_t offset = id2reg_offset(id) + RCC_RSTCLRR_OFFSET;
+	uint32_t bitmsk = BIT(id2reg_bit_pos(id));
+	uint64_t timeout_ref;
+	uintptr_t rcc_base = stm32mp_rcc_base();
+
+	mmio_write_32(rcc_base + offset, bitmsk);
+
+	timeout_ref = timeout_init_us(RESET_TIMEOUT_US_1MS);
+	while ((mmio_read_32(rcc_base + offset) & bitmsk) != 0U) {
+		if (timeout_elapsed(timeout_ref)) {
+			panic();
+		}
 	}
 }

fdts/stm32mp157c-dk2.dts

+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>.
+ */
+
+/dts-v1/;
+
+#include "stm32mp157a-dk1.dts"
+
+/ {
+	model = "STMicroelectronics STM32MP157C-DK2 Discovery Board";
+	compatible = "st,stm32mp157c-dk2", "st,stm32mp157";
+
+};
+

fdts/stm32mp157c-ed1.dts

@@ -55,7 +55,7 @@
 
 			vddcore: buck1 {
 				regulator-name = "vddcore";
-				regulator-min-microvolt = <800000>;
+				regulator-min-microvolt = <1200000>;
 				regulator-max-microvolt = <1350000>;
 				regulator-always-on;
 				regulator-initial-mode = <0>;

fdts/stm32mp157cac-pinctrl.dtsi

+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
+/*
+ * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
+ * Author: Alexandre Torgue <alexandre.torgue@st.com>
+ */
+
+#include "stm32mp157-pinctrl.dtsi"
+/ {
+	soc {
+		pinctrl: pin-controller@50002000 {
+			st,package = <STM32MP157CAC>;
+
+			gpioa: gpio@50002000 {
+				status = "okay";
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 0 16>;
+			};
+
+			gpiob: gpio@50003000 {
+				status = "okay";
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 16 16>;
+			};
+
+			gpioc: gpio@50004000 {
+				status = "okay";
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 32 16>;
+			};
+
+			gpiod: gpio@50005000 {
+				status = "okay";
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 48 16>;
+			};
+
+			gpioe: gpio@50006000 {
+				status = "okay";
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 64 16>;
+			};
+
+			gpiof: gpio@50007000 {
+				status = "okay";
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 80 16>;
+			};
+
+			gpiog: gpio@50008000 {
+				status = "okay";
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 96 16>;
+			};
+
+			gpioh: gpio@50009000 {
+				status = "okay";
+				ngpios = <16>;
+				gpio-ranges = <&pinctrl 0 112 16>;
+			};
+
+			gpioi: gpio@5000a000 {
+				status = "okay";
+				ngpios = <12>;
+				gpio-ranges = <&pinctrl 0 128 12>;
+			};
+		};
+
+		pinctrl_z: pin-controller-z@54004000 {
+			st,package = <STM32MP157CAC>;
+
+			gpioz: gpio@54004000 {
+				status = "okay";
+				ngpios = <8>;
+				gpio-ranges = <&pinctrl_z 0 400 8>;
+			};
+		};
+	};
+};