Merge pull request #1821 from Yann-lms/stm32mp1_2019-02-14

Series of new patches for STM32MP1

plat/st/stm32mp1/stm32mp1_gic.c

@@ -15,9 +15,6 @@
 #include <lib/utils.h>
 #include <plat/common/platform.h>
 
-#include <stm32mp1_dt.h>
-#include <stm32mp1_private.h>
-
 struct stm32_gic_instance {
 	uint32_t cells;
 	uint32_t phandle_node;

plat/st/stm32mp1/stm32mp1_helper.S

@@ -10,7 +10,6 @@
 #include <asm_macros.S>
 #include <common/bl_common.h>
 #include <drivers/st/stm32_gpio.h>
-#include <drivers/st/stm32mp1_rcc.h>
 
 #define GPIO_TX_SHIFT		(DEBUG_UART_TX_GPIO_PORT << 1)
 #define GPIO_TX_ALT_SHIFT	((DEBUG_UART_TX_GPIO_PORT - GPIO_ALT_LOWER_LIMIT) << 2)
@@ -74,7 +73,7 @@ func plat_is_my_cpu_primary
 	ldcopr	r0, MPIDR
 	ldr	r1, =(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
 	and	r0, r1
-	cmp	r0, #STM32MP1_PRIMARY_CPU
+	cmp	r0, #STM32MP_PRIMARY_CPU
 	moveq	r0, #1
 	movne	r0, #0
 	bx	lr
@@ -143,9 +142,9 @@ func plat_crash_console_init
 	orr	r2, r2, #DEBUG_UART_TX_EN
 	str	r2, [r1]
 
-	ldr	r0, =STM32MP1_DEBUG_USART_BASE
-	ldr	r1, =STM32MP1_DEBUG_USART_CLK_FRQ
-	ldr	r2, =STM32MP1_UART_BAUDRATE
+	ldr	r0, =STM32MP_DEBUG_USART_BASE
+	ldr	r1, =STM32MP_DEBUG_USART_CLK_FRQ
+	ldr	r2, =STM32MP_UART_BAUDRATE
 	b	console_stm32_core_init
 endfunc plat_crash_console_init
 
@@ -156,7 +155,7 @@ endfunc plat_crash_console_init
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_flush
-	ldr	r1, =STM32MP1_DEBUG_USART_BASE
+	ldr	r1, =STM32MP_DEBUG_USART_BASE
 	b	console_stm32_core_flush
 endfunc plat_crash_console_flush
 
@@ -172,6 +171,6 @@ endfunc plat_crash_console_flush
 	 * ---------------------------------------------
 	 */
 func plat_crash_console_putc
-	ldr	r1, =STM32MP1_DEBUG_USART_BASE
+	ldr	r1, =STM32MP_DEBUG_USART_BASE
 	b	console_stm32_core_putc
 endfunc plat_crash_console_putc

plat/st/stm32mp1/stm32mp1_pm.c

@@ -14,15 +14,11 @@
 #include <drivers/arm/gic_common.h>
 #include <drivers/arm/gicv2.h>
 #include <drivers/st/stm32mp1_clk.h>
-#include <drivers/st/stm32mp1_rcc.h>
 #include <dt-bindings/clock/stm32mp1-clks.h>
 #include <lib/mmio.h>
 #include <lib/psci/psci.h>
 #include <plat/common/platform.h>
 
-#include <boot_api.h>
-#include <stm32mp1_private.h>
-
 static uintptr_t stm32_sec_entrypoint;
 static uint32_t cntfrq_core0;
 
@@ -63,7 +59,6 @@ static void stm32_cpu_standby(plat_local_state_t cpu_state)
 static int stm32_pwr_domain_on(u_register_t mpidr)
 {
 	unsigned long current_cpu_mpidr = read_mpidr_el1();
-	uint32_t tamp_clk_off = 0;
 	uint32_t bkpr_core1_addr =
 		tamp_bkpr(BOOT_API_CORE1_BRANCH_ADDRESS_TAMP_BCK_REG_IDX);
 	uint32_t bkpr_core1_magic =
@@ -73,18 +68,13 @@ static int stm32_pwr_domain_on(u_register_t mpidr)
 		return PSCI_E_INVALID_PARAMS;
 	}
 
-	if ((stm32_sec_entrypoint < STM32MP1_SRAM_BASE) ||
-	    (stm32_sec_entrypoint > (STM32MP1_SRAM_BASE +
-				     (STM32MP1_SRAM_SIZE - 1)))) {
+	if ((stm32_sec_entrypoint < STM32MP_SYSRAM_BASE) ||
+	    (stm32_sec_entrypoint > (STM32MP_SYSRAM_BASE +
+				     (STM32MP_SYSRAM_SIZE - 1)))) {
 		return PSCI_E_INVALID_ADDRESS;
 	}
 
-	if (!stm32mp1_clk_is_enabled(RTCAPB)) {
-		tamp_clk_off = 1;
-		if (stm32mp1_clk_enable(RTCAPB) != 0) {
-			panic();
-		}
-	}
+	stm32mp_clk_enable(RTCAPB);
 
 	cntfrq_core0 = read_cntfrq_el0();
 
@@ -94,14 +84,10 @@ static int stm32_pwr_domain_on(u_register_t mpidr)
 	/* Write magic number in backup register */
 	mmio_write_32(bkpr_core1_magic, BOOT_API_A7_CORE1_MAGIC_NUMBER);
 
-	if (tamp_clk_off != 0U) {
-		if (stm32mp1_clk_disable(RTCAPB) != 0) {
-			panic();
-		}
-	}
+	stm32mp_clk_disable(RTCAPB);
 
 	/* Generate an IT to core 1 */
-	gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP1_SECONDARY_CPU);
+	gicv2_raise_sgi(ARM_IRQ_SEC_SGI_0, STM32MP_SECONDARY_CPU);
 
 	return PSCI_E_SUCCESS;
 }
@@ -163,7 +149,8 @@ static void __dead2 stm32_system_off(void)
 
 static void __dead2 stm32_system_reset(void)
 {
-	mmio_setbits_32(RCC_BASE + RCC_MP_GRSTCSETR, RCC_MP_GRSTCSETR_MPSYSRST);
+	mmio_setbits_32(stm32mp_rcc_base() + RCC_MP_GRSTCSETR,
+			RCC_MP_GRSTCSETR_MPSYSRST);
 
 	/* Loop in case system reset is not immediately caught */
 	for ( ; ; ) {
@@ -197,7 +184,7 @@ static int stm32_validate_power_state(unsigned int power_state,
 static int stm32_validate_ns_entrypoint(uintptr_t entrypoint)
 {
 	/* The non-secure entry point must be in DDR */
-	if (entrypoint < STM32MP1_DDR_BASE) {
+	if (entrypoint < STM32MP_DDR_BASE) {
 		return PSCI_E_INVALID_ADDRESS;
 	}
 

plat/st/stm32mp1/stm32mp1_common.c → plat/st/stm32mp1/stm32mp1_private.c

@@ -4,23 +4,12 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#include <assert.h>
-
 #include <platform_def.h>
 
-#include <arch_helpers.h>
-#include <common/bl_common.h>
-#include <common/debug.h>
-#include <drivers/arm/gicv2.h>
-#include <dt-bindings/clock/stm32mp1-clks.h>
-#include <lib/mmio.h>
 #include <lib/xlat_tables/xlat_tables_v2.h>
-#include <plat/common/platform.h>
-
-#include <stm32mp1_private.h>
 
-#define MAP_SRAM	MAP_REGION_FLAT(STM32MP1_SRAM_BASE, \
-					STM32MP1_SRAM_SIZE, \
+#define MAP_SRAM	MAP_REGION_FLAT(STM32MP_SYSRAM_BASE, \
+					STM32MP_SYSRAM_SIZE, \
 					MT_MEMORY | \
 					MT_RW | \
 					MT_SECURE | \
@@ -64,60 +53,3 @@ void configure_mmu(void)
 
 	enable_mmu_svc_mon(0);
 }
-
-uintptr_t plat_get_ns_image_entrypoint(void)
-{
-	return BL33_BASE;
-}
-
-unsigned int plat_get_syscnt_freq2(void)
-{
-	return read_cntfrq_el0();
-}
-
-/* Functions to save and get boot context address given by ROM code */
-static uintptr_t boot_ctx_address;
-
-void stm32mp1_save_boot_ctx_address(uintptr_t address)
-{
-	boot_ctx_address = address;
-}
-
-uintptr_t stm32mp1_get_boot_ctx_address(void)
-{
-	return boot_ctx_address;
-}
-
-uintptr_t stm32_get_gpio_bank_base(unsigned int bank)
-{
-	switch (bank) {
-	case GPIO_BANK_A ... GPIO_BANK_K:
-		return GPIOA_BASE + (bank * GPIO_BANK_OFFSET);
-	case GPIO_BANK_Z:
-		return GPIOZ_BASE;
-	default:
-		panic();
-	}
-}
-
-/* Return clock ID on success, negative value on error */
-unsigned long stm32_get_gpio_bank_clock(unsigned int bank)
-{
-	switch (bank) {
-	case GPIO_BANK_A ... GPIO_BANK_K:
-		return GPIOA + (bank - GPIO_BANK_A);
-	case GPIO_BANK_Z:
-		return GPIOZ;
-	default:
-		panic();
-	}
-}
-
-uint32_t stm32_get_gpio_bank_offset(unsigned int bank)
-{
-	if (bank == GPIO_BANK_Z) {
-		return 0;
-	} else {
-		return bank * GPIO_BANK_OFFSET;
-	}
-}

plat/st/stm32mp1/stm32mp1_security.c

@@ -11,13 +11,9 @@
 #include <common/debug.h>
 #include <drivers/arm/tzc400.h>
 #include <drivers/st/stm32mp1_clk.h>
-#include <drivers/st/stm32mp1_rcc.h>
 #include <dt-bindings/clock/stm32mp1-clks.h>
 #include <lib/mmio.h>
 
-#include <stm32mp1_dt.h>
-#include <stm32mp1_private.h>
-
 /*******************************************************************************
  * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access
  * and allow Non-Secure masters full access.
@@ -25,7 +21,7 @@
 static void init_tzc400(void)
 {
 	unsigned long long region_base, region_top;
-	unsigned long long ddr_base = STM32MP1_DDR_BASE;
+	unsigned long long ddr_base = STM32MP_DDR_BASE;
 	unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size();
 
 	tzc400_init(STM32MP1_TZC_BASE);
@@ -65,14 +61,8 @@ static void init_tzc400(void)
  ******************************************************************************/
 static void early_init_tzc400(void)
 {
-	if (stm32mp1_clk_enable(TZC1) != 0) {
-		ERROR("Cannot enable TZC1 clock\n");
-		panic();
-	}
-	if (stm32mp1_clk_enable(TZC2) != 0) {
-		ERROR("Cannot enable TZC2 clock\n");
-		panic();
-	}
+	stm32mp_clk_enable(TZC1);
+	stm32mp_clk_enable(TZC2);
 
 	tzc400_init(STM32MP1_TZC_BASE);
 
@@ -83,9 +73,9 @@ static void early_init_tzc400(void)
 	 * same configuration to all filters in the TZC.
 	 */
 	tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1,
-				STM32MP1_DDR_BASE,
-				STM32MP1_DDR_BASE +
-				(STM32MP1_DDR_MAX_SIZE - 1U),
+				STM32MP_DDR_BASE,
+				STM32MP_DDR_BASE +
+				(STM32MP_DDR_MAX_SIZE - 1U),
 				TZC_REGION_S_RDWR,
 				TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) |
 				TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID));