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adam.huang
Arm Trusted Firmware
Commits
37ebe8e5
Commit
37ebe8e5
authored
Dec 17, 2019
by
Soby Mathew
Committed by
TrustedFirmware Code Review
Dec 17, 2019
Browse files
Merge "plat/rockchip: cliam a macro to enable hdcp feature for DP" into integration
parents
044b22a0
f0063ef9
Changes
2
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plat/rockchip/rk3399/plat_sip_calls.c
View file @
37ebe8e5
...
@@ -56,17 +56,21 @@ uintptr_t rockchip_plat_sip_handler(uint32_t smc_fid,
...
@@ -56,17 +56,21 @@ uintptr_t rockchip_plat_sip_handler(uint32_t smc_fid,
void
*
handle
,
void
*
handle
,
u_register_t
flags
)
u_register_t
flags
)
{
{
#ifdef PLAT_RK_DP_HDCP
uint64_t
x5
,
x6
;
uint64_t
x5
,
x6
;
#endif
switch
(
smc_fid
)
{
switch
(
smc_fid
)
{
case
RK_SIP_DDR_CFG
:
case
RK_SIP_DDR_CFG
:
SMC_RET1
(
handle
,
ddr_smc_handler
(
x1
,
x2
,
x3
,
x4
));
SMC_RET1
(
handle
,
ddr_smc_handler
(
x1
,
x2
,
x3
,
x4
));
#ifdef PLAT_RK_DP_HDCP
case
RK_SIP_HDCP_CONTROL
:
case
RK_SIP_HDCP_CONTROL
:
SMC_RET1
(
handle
,
dp_hdcp_ctrl
(
x1
));
SMC_RET1
(
handle
,
dp_hdcp_ctrl
(
x1
));
case
RK_SIP_HDCP_KEY_DATA64
:
case
RK_SIP_HDCP_KEY_DATA64
:
x5
=
read_ctx_reg
(
get_gpregs_ctx
(
handle
),
CTX_GPREG_X5
);
x5
=
read_ctx_reg
(
get_gpregs_ctx
(
handle
),
CTX_GPREG_X5
);
x6
=
read_ctx_reg
(
get_gpregs_ctx
(
handle
),
CTX_GPREG_X6
);
x6
=
read_ctx_reg
(
get_gpregs_ctx
(
handle
),
CTX_GPREG_X6
);
SMC_RET1
(
handle
,
dp_hdcp_store_key
(
x1
,
x2
,
x3
,
x4
,
x5
,
x6
));
SMC_RET1
(
handle
,
dp_hdcp_store_key
(
x1
,
x2
,
x3
,
x4
,
x5
,
x6
));
#endif
default:
default:
ERROR
(
"%s: unhandled SMC (0x%x)
\n
"
,
__func__
,
smc_fid
);
ERROR
(
"%s: unhandled SMC (0x%x)
\n
"
,
__func__
,
smc_fid
);
SMC_RET1
(
handle
,
SMC_UNK
);
SMC_RET1
(
handle
,
SMC_UNK
);
...
...
plat/rockchip/rk3399/platform.mk
View file @
37ebe8e5
...
@@ -56,7 +56,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \
...
@@ -56,7 +56,6 @@ BL31_SOURCES += ${RK_GIC_SOURCES} \
${RK_PLAT_COMMON}
/aarch64/platform_common.c
\
${RK_PLAT_COMMON}
/aarch64/platform_common.c
\
${RK_PLAT_COMMON}
/rockchip_sip_svc.c
\
${RK_PLAT_COMMON}
/rockchip_sip_svc.c
\
${RK_PLAT_SOC}
/plat_sip_calls.c
\
${RK_PLAT_SOC}
/plat_sip_calls.c
\
${RK_PLAT_SOC}
/drivers/dp/cdn_dp.c
\
${RK_PLAT_SOC}
/drivers/gpio/rk3399_gpio.c
\
${RK_PLAT_SOC}
/drivers/gpio/rk3399_gpio.c
\
${RK_PLAT_SOC}
/drivers/pmu/pmu.c
\
${RK_PLAT_SOC}
/drivers/pmu/pmu.c
\
${RK_PLAT_SOC}
/drivers/pmu/pmu_fw.c
\
${RK_PLAT_SOC}
/drivers/pmu/pmu_fw.c
\
...
@@ -87,17 +86,21 @@ $(eval $(call add_define_val,RK3399M0FW,\"$(RK3399M0FW)\"))
...
@@ -87,17 +86,21 @@ $(eval $(call add_define_val,RK3399M0FW,\"$(RK3399M0FW)\"))
RK3399M0PMUFW
=
${BUILD_M0}
/
${PLAT_M0}
pmu.bin
RK3399M0PMUFW
=
${BUILD_M0}
/
${PLAT_M0}
pmu.bin
$(eval
$(call
add_define_val,RK3399M0PMUFW,\"$(RK3399M0PMUFW)\"))
$(eval
$(call
add_define_val,RK3399M0PMUFW,\"$(RK3399M0PMUFW)\"))
ifdef
PLAT_RK_DP_HDCP
BL31_SOURCES
+=
${RK_PLAT_SOC}
/drivers/dp/cdn_dp.c
HDCPFW
=
${RK_PLAT_SOC}
/drivers/dp/hdcp.bin
HDCPFW
=
${RK_PLAT_SOC}
/drivers/dp/hdcp.bin
$(eval
$(call
add_define_val,HDCPFW,\"$(HDCPFW)\"))
$(eval
$(call
add_define_val,HDCPFW,\"$(HDCPFW)\"))
${BUILD_PLAT}/bl31/cdn_dp.o
:
CCACHE_EXTRAFILES=$(HDCPFW)
${RK_PLAT_SOC}/drivers/dp/cdn_dp.c
:
$(HDCPFW)
endif
# CCACHE_EXTRAFILES is needed because ccache doesn't handle .incbin
# CCACHE_EXTRAFILES is needed because ccache doesn't handle .incbin
export
CCACHE_EXTRAFILES
export
CCACHE_EXTRAFILES
${BUILD_PLAT}/bl31/pmu_fw.o
:
CCACHE_EXTRAFILES=$(RK3399M0FW):$(RK3399M0PMUFW)
${BUILD_PLAT}/bl31/pmu_fw.o
:
CCACHE_EXTRAFILES=$(RK3399M0FW):$(RK3399M0PMUFW)
${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c
:
$(RK3399M0FW)
${RK_PLAT_SOC}/drivers/pmu/pmu_fw.c
:
$(RK3399M0FW)
${BUILD_PLAT}/bl31/cdn_dp.o
:
CCACHE_EXTRAFILES=$(HDCPFW)
${RK_PLAT_SOC}/drivers/dp/cdn_dp.c
:
$(HDCPFW)
$(eval
$(call
MAKE_PREREQ_DIR,${BUILD_M0},${BUILD_PLAT}))
$(eval
$(call
MAKE_PREREQ_DIR,${BUILD_M0},${BUILD_PLAT}))
.PHONY
:
$(RK3399M0FW)
.PHONY
:
$(RK3399M0FW)
$(RK3399M0FW)
:
| ${BUILD_M0}
$(RK3399M0FW)
:
| ${BUILD_M0}
...
...
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