NXP: SFP driver support for NXP SoC

NXP Security Fuse Processor is used to read and write
fuses.
- Fuses once written, are cannot be un-done.
- Used as trust anchor for monotonic counter,
  different platform keys etc.
Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com>
Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
Change-Id: I347e806dd87078150fbbbfc28355bb44d9eacb9c

drivers/nxp/sfp/fuse_prov.c

+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <caam.h>
+#include <common/debug.h>
+#include <dcfg.h>
+#include <drivers/delay_timer.h>
+#include <fuse_prov.h>
+#include <sfp.h>
+#include <sfp_error_codes.h>
+
+
+static int write_a_fuse(uint32_t *fuse_addr, uint32_t *fuse_hdr_val,
+			uint32_t mask)
+{
+	uint32_t last_stored_val = sfp_read32(fuse_addr);
+
+	 /* Check if fuse already blown or not */
+	if ((last_stored_val & mask) == mask) {
+		return ERROR_ALREADY_BLOWN;
+	}
+
+	 /* Write fuse in mirror registers */
+	sfp_write32(fuse_addr, last_stored_val | (*fuse_hdr_val & mask));
+
+	 /* Read back to check if write success */
+	if (sfp_read32(fuse_addr) != (last_stored_val | (*fuse_hdr_val & mask))) {
+		return ERROR_WRITE;
+	}
+
+	return 0;
+}
+
+static int write_fuses(uint32_t *fuse_addr, uint32_t *fuse_hdr_val, uint8_t len)
+{
+	int i;
+
+	 /* Check if fuse already blown or not */
+	for (i = 0; i < len; i++) {
+		if (sfp_read32(&fuse_addr[i]) != 0) {
+			return ERROR_ALREADY_BLOWN;
+		}
+	}
+
+	 /* Write fuse in mirror registers */
+	for (i = 0; i < len; i++) {
+		sfp_write32(&fuse_addr[i], fuse_hdr_val[i]);
+	}
+
+	 /* Read back to check if write success */
+	for (i = 0; i < len; i++) {
+		if (sfp_read32(&fuse_addr[i]) != fuse_hdr_val[i]) {
+			return ERROR_WRITE;
+		}
+	}
+
+	return 0;
+}
+
+/*
+ * This function program Super Root Key Hash (SRKH) in fuse
+ * registers.
+ */
+static int prog_srkh(struct fuse_hdr_t *fuse_hdr,
+		     struct sfp_ccsr_regs_t *sfp_ccsr_regs)
+{
+	int ret = 0;
+
+	ret = write_fuses(sfp_ccsr_regs->srk_hash, fuse_hdr->srkh, 8);
+
+	if (ret != 0) {
+		ret = (ret == ERROR_ALREADY_BLOWN) ?
+			ERROR_SRKH_ALREADY_BLOWN : ERROR_SRKH_WRITE;
+	}
+
+	return ret;
+}
+
+/* This function program OEMUID[0-4] in fuse registers. */
+static int prog_oemuid(struct fuse_hdr_t *fuse_hdr,
+		       struct sfp_ccsr_regs_t *sfp_ccsr_regs)
+{
+	int i, ret = 0;
+
+	for (i = 0; i < 5; i++) {
+		 /* Check OEMUIDx to be blown or not */
+		if (((fuse_hdr->flags >> (FLAG_OUID0_SHIFT + i)) & 0x1) != 0) {
+			 /* Check if OEMUID[i] already blown or not */
+			ret = write_fuses(&sfp_ccsr_regs->oem_uid[i],
+					 &fuse_hdr->oem_uid[i], 1);
+
+			if (ret != 0) {
+				ret = (ret == ERROR_ALREADY_BLOWN) ?
+					ERROR_OEMUID_ALREADY_BLOWN
+					: ERROR_OEMUID_WRITE;
+			}
+		}
+	}
+	return ret;
+}
+
+/* This function program DCV[0-1], DRV[0-1] in fuse registers. */
+static int prog_debug(struct fuse_hdr_t *fuse_hdr,
+		      struct sfp_ccsr_regs_t *sfp_ccsr_regs)
+{
+	int ret;
+
+	 /* Check DCV to be blown or not */
+	if (((fuse_hdr->flags >> (FLAG_DCV0_SHIFT)) & 0x3) != 0) {
+		 /* Check if DCV[i] already blown or not */
+		ret = write_fuses(sfp_ccsr_regs->dcv, fuse_hdr->dcv, 2);
+
+		if (ret != 0) {
+			ret = (ret == ERROR_ALREADY_BLOWN) ?
+				ERROR_DCV_ALREADY_BLOWN
+				: ERROR_DCV_WRITE;
+		}
+	}
+
+	 /* Check DRV to be blown or not */
+	if ((((fuse_hdr->flags >> (FLAG_DRV0_SHIFT)) & 0x3)) != 0) {
+		 /* Check if DRV[i] already blown or not */
+		ret = write_fuses(sfp_ccsr_regs->drv, fuse_hdr->drv, 2);
+
+		if (ret != 0) {
+			ret = (ret == ERROR_ALREADY_BLOWN) ?
+				ERROR_DRV_ALREADY_BLOWN
+				: ERROR_DRV_WRITE;
+		} else {
+			 /* Check for DRV hamming error */
+			if (sfp_read32((void *)(get_sfp_addr()
+							+ SFP_SVHESR_OFFSET))
+				& SFP_SVHESR_DRV_MASK) {
+				return ERROR_DRV_HAMMING_ERROR;
+			}
+		}
+	}
+
+	return 0;
+}
+
+ /*
+  * Turn a 256-bit random value (32 bytes) into an OTPMK code word
+  * modifying the input data array in place
+  */
+static void otpmk_make_code_word_256(uint8_t *otpmk, bool minimal_flag)
+{
+	int i;
+	uint8_t parity_bit;
+	uint8_t code_bit;
+
+	if (minimal_flag == true) {
+		 /*
+		  * Force bits 252, 253, 254 and 255 to 1
+		  * This is because these fuses may have already been blown
+		  * and the OTPMK cannot force them back to 0
+		  */
+		otpmk[252/8] |= (1 << (252%8));
+		otpmk[253/8] |= (1 << (253%8));
+		otpmk[254/8] |= (1 << (254%8));
+		otpmk[255/8] |= (1 << (255%8));
+	}
+
+	 /* Generate the hamming code for the code word */
+	parity_bit = 0;
+	code_bit = 0;
+	for (i = 0; i < 256; i += 1) {
+		if ((otpmk[i/8] & (1 << (i%8))) != 0) {
+			parity_bit ^= 1;
+			code_bit   ^= i;
+		}
+	}
+
+	 /* Inverting otpmk[code_bit] will cause the otpmk
+	  * to become a valid code word (except for overall parity)
+	  */
+	if (code_bit < 252) {
+		otpmk[code_bit/8] ^= (1 << (code_bit % 8));
+		parity_bit  ^= 1;  // account for flipping a bit changing parity
+	} else {
+		 /* Invert two bits:  (code_bit - 4) and 4
+		  * Because we invert two bits, no need to touch the parity bit
+		  */
+		otpmk[(code_bit - 4)/8] ^= (1 << ((code_bit - 4) % 8));
+		otpmk[4/8] ^= (1 << (4 % 8));
+	}
+
+	 /* Finally, adjust the overall parity of the otpmk
+	  * otpmk bit 0
+	  */
+	otpmk[0] ^= parity_bit;
+}
+
+/* This function program One Time Programmable Master Key (OTPMK)
+ *  in fuse registers.
+ */
+static int prog_otpmk(struct fuse_hdr_t *fuse_hdr,
+		      struct sfp_ccsr_regs_t *sfp_ccsr_regs)
+{
+	int ret = 0;
+	uint32_t otpmk_flags;
+	uint32_t otpmk_random[8] __aligned(CACHE_WRITEBACK_GRANULE);
+
+	otpmk_flags = (fuse_hdr->flags >> (FLAG_OTPMK_SHIFT)) & FLAG_OTPMK_MASK;
+
+	switch (otpmk_flags) {
+	case PROG_OTPMK_MIN:
+		memset(fuse_hdr->otpmk, 0, sizeof(fuse_hdr->otpmk));
+
+		 /* Minimal OTPMK value (252-255 bits set to 1) */
+		fuse_hdr->otpmk[0] |= OTPMK_MIM_BITS_MASK;
+		break;
+
+	case PROG_OTPMK_RANDOM:
+		if (is_sec_enabled() == false) {
+			ret = ERROR_OTPMK_SEC_DISABLED;
+			goto out;
+		}
+
+		 /* Generate Random number using CAAM for OTPMK */
+		memset(otpmk_random, 0, sizeof(otpmk_random));
+		if (get_rand_bytes_hw((uint8_t *)otpmk_random,
+				      sizeof(otpmk_random)) != 0) {
+			ret = ERROR_OTPMK_SEC_ERROR;
+			goto out;
+		}
+
+		 /* Run hamming over random no. to make OTPMK */
+		otpmk_make_code_word_256((uint8_t *)otpmk_random, false);
+
+		 /* Swap OTPMK */
+		fuse_hdr->otpmk[0] = otpmk_random[7];
+		fuse_hdr->otpmk[1] = otpmk_random[6];
+		fuse_hdr->otpmk[2] = otpmk_random[5];
+		fuse_hdr->otpmk[3] = otpmk_random[4];
+		fuse_hdr->otpmk[4] = otpmk_random[3];
+		fuse_hdr->otpmk[5] = otpmk_random[2];
+		fuse_hdr->otpmk[6] = otpmk_random[1];
+		fuse_hdr->otpmk[7] = otpmk_random[0];
+		break;
+
+	case PROG_OTPMK_USER:
+		break;
+
+	case PROG_OTPMK_RANDOM_MIN:
+		 /* Here assumption is that user is aware of minimal OTPMK
+		  * already blown.
+		  */
+
+		 /* Generate Random number using CAAM for OTPMK */
+		if (is_sec_enabled() == false) {
+			ret = ERROR_OTPMK_SEC_DISABLED;
+			goto out;
+		}
+
+		memset(otpmk_random, 0, sizeof(otpmk_random));
+		if (get_rand_bytes_hw((uint8_t *)otpmk_random,
+				      sizeof(otpmk_random)) != 0) {
+			ret = ERROR_OTPMK_SEC_ERROR;
+			goto out;
+		}
+
+		 /* Run hamming over random no. to make OTPMK */
+		otpmk_make_code_word_256((uint8_t *)otpmk_random, true);
+
+		 /* Swap OTPMK */
+		fuse_hdr->otpmk[0] = otpmk_random[7];
+		fuse_hdr->otpmk[1] = otpmk_random[6];
+		fuse_hdr->otpmk[2] = otpmk_random[5];
+		fuse_hdr->otpmk[3] = otpmk_random[4];
+		fuse_hdr->otpmk[4] = otpmk_random[3];
+		fuse_hdr->otpmk[5] = otpmk_random[2];
+		fuse_hdr->otpmk[6] = otpmk_random[1];
+		fuse_hdr->otpmk[7] = otpmk_random[0];
+		break;
+
+	case PROG_OTPMK_USER_MIN:
+		 /*
+		  * Here assumption is that user is aware of minimal OTPMK
+		  * already blown. Check if minimal bits are set in user
+		  * supplied OTPMK.
+		  */
+		if ((fuse_hdr->otpmk[0] & OTPMK_MIM_BITS_MASK) !=
+							OTPMK_MIM_BITS_MASK) {
+			ret = ERROR_OTPMK_USER_MIN;
+			goto out;
+		}
+		break;
+
+	default:
+		ret = 0;
+		goto out;
+	}
+
+	ret = write_fuses(sfp_ccsr_regs->otpmk, fuse_hdr->otpmk, 8);
+
+	if (ret != 0) {
+		ret = (ret == ERROR_ALREADY_BLOWN) ?
+			ERROR_OTPMK_ALREADY_BLOWN
+			: ERROR_OTPMK_WRITE;
+	} else {
+		 /* Check for DRV hamming error */
+		if ((sfp_read32((void *)(get_sfp_addr() + SFP_SVHESR_OFFSET))
+			& SFP_SVHESR_OTPMK_MASK) != 0) {
+			ret = ERROR_OTPMK_HAMMING_ERROR;
+		}
+	}
+
+out:
+	return ret;
+}
+
+/* This function program OSPR1 in fuse registers.
+ */
+static int prog_ospr1(struct fuse_hdr_t *fuse_hdr,
+		      struct sfp_ccsr_regs_t *sfp_ccsr_regs)
+{
+	int ret;
+	uint32_t mask;
+
+#ifdef NXP_SFP_VER_3_4
+	if (((fuse_hdr->flags >> FLAG_MC_SHIFT) & 0x1) != 0) {
+		mask = OSPR1_MC_MASK;
+	}
+#endif
+	if (((fuse_hdr->flags >> FLAG_DBG_LVL_SHIFT) & 0x1) != 0) {
+		mask = mask | OSPR1_DBG_LVL_MASK;
+	}
+
+	ret = write_a_fuse(&sfp_ccsr_regs->ospr1, &fuse_hdr->ospr1, mask);
+
+	if (ret != 0) {
+		ret = (ret == ERROR_ALREADY_BLOWN) ?
+				ERROR_OSPR1_ALREADY_BLOWN
+				: ERROR_OSPR1_WRITE;
+	}
+
+	return ret;
+}
+
+/* This function program SYSCFG in fuse registers.
+ */
+static int prog_syscfg(struct fuse_hdr_t *fuse_hdr,
+		       struct sfp_ccsr_regs_t *sfp_ccsr_regs)
+{
+	int ret;
+
+	 /* Check if SYSCFG already blown or not */
+	ret = write_a_fuse(&sfp_ccsr_regs->ospr, &fuse_hdr->sc, OSPR0_SC_MASK);
+
+	if (ret != 0) {
+		ret = (ret == ERROR_ALREADY_BLOWN) ?
+				ERROR_SC_ALREADY_BLOWN
+				: ERROR_SC_WRITE;
+	}
+
+	return ret;
+}
+
+/* This function does fuse provisioning.
+ */
+int provision_fuses(unsigned long long fuse_scr_addr,
+		    bool en_povdd_status)
+{
+	struct fuse_hdr_t *fuse_hdr = NULL;
+	struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(get_sfp_addr()
+							+ SFP_FUSE_REGS_OFFSET);
+	int ret = 0;
+
+	fuse_hdr = (struct fuse_hdr_t *)fuse_scr_addr;
+
+	/*
+	 * Check for Write Protect (WP) fuse. If blown then do
+	 *  no fuse provisioning.
+	 */
+	if ((sfp_read32(&sfp_ccsr_regs->ospr) & 0x1) != 0) {
+		goto out;
+	}
+
+	 /* Check if SRKH to be blown or not */
+	if (((fuse_hdr->flags >> FLAG_SRKH_SHIFT) & 0x1) != 0) {
+		INFO("Fuse: Program SRKH\n");
+		ret = prog_srkh(fuse_hdr, sfp_ccsr_regs);
+		if (ret != 0) {
+			error_handler(ret);
+			goto out;
+		}
+	}
+
+	 /* Check if OEMUID to be blown or not */
+	if (((fuse_hdr->flags >> FLAG_OUID0_SHIFT) & FLAG_OUID_MASK) != 0) {
+		INFO("Fuse: Program OEMUIDs\n");
+		ret = prog_oemuid(fuse_hdr, sfp_ccsr_regs);
+		if (ret != 0) {
+			error_handler(ret);
+			goto out;
+		}
+	}
+
+	 /* Check if Debug values to be blown or not */
+	if (((fuse_hdr->flags >> FLAG_DCV0_SHIFT) & FLAG_DEBUG_MASK) != 0) {
+		INFO("Fuse: Program Debug values\n");
+		ret = prog_debug(fuse_hdr, sfp_ccsr_regs);
+		if (ret != 0) {
+			error_handler(ret);
+			goto out;
+		}
+	}
+
+	 /* Check if OTPMK values to be blown or not */
+	if (((fuse_hdr->flags >> FLAG_OTPMK_SHIFT) & PROG_NO_OTPMK) !=
+		PROG_NO_OTPMK) {
+		INFO("Fuse: Program OTPMK\n");
+		ret = prog_otpmk(fuse_hdr, sfp_ccsr_regs);
+		if (ret != 0) {
+			error_handler(ret);
+			goto out;
+		}
+	}
+
+
+	 /* Check if MC or DBG LVL to be blown or not */
+	if ((((fuse_hdr->flags >> FLAG_MC_SHIFT) & 0x1) != 0) ||
+		(((fuse_hdr->flags >> FLAG_DBG_LVL_SHIFT) & 0x1) != 0)) {
+		INFO("Fuse: Program OSPR1\n");
+		ret = prog_ospr1(fuse_hdr, sfp_ccsr_regs);
+		if (ret != 0) {
+			error_handler(ret);
+			goto out;
+		}
+	}
+
+	 /* Check if SYSCFG to be blown or not */
+	if (((fuse_hdr->flags >> FLAG_SYSCFG_SHIFT) & 0x1) != 0) {
+		INFO("Fuse: Program SYSCFG\n");
+		ret = prog_syscfg(fuse_hdr, sfp_ccsr_regs);
+		if (ret != 0) {
+			error_handler(ret);
+			goto out;
+		}
+	}
+
+	if (en_povdd_status) {
+		ret = sfp_program_fuses();
+		if (ret != 0) {
+			error_handler(ret);
+			goto out;
+		}
+	}
+out:
+	return ret;
+}

drivers/nxp/sfp/fuse_prov.h

+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#if !defined(FUSE_PROV_H) && defined(POLICY_FUSE_PROVISION)
+#define FUSE_PROV_H
+
+#include <endian.h>
+#include <lib/mmio.h>
+
+#define MASK_NONE		U(0xFFFFFFFF)
+#define ERROR_WRITE		U(0xA)
+#define ERROR_ALREADY_BLOWN	U(0xB)
+
+/* Flag bit shifts */
+#define FLAG_POVDD_SHIFT	U(0)
+#define FLAG_SYSCFG_SHIFT	U(1)
+#define FLAG_SRKH_SHIFT		U(2)
+#define FLAG_MC_SHIFT		U(3)
+#define FLAG_DCV0_SHIFT		U(4)
+#define FLAG_DCV1_SHIFT		U(5)
+#define FLAG_DRV0_SHIFT		U(6)
+#define FLAG_DRV1_SHIFT		U(7)
+#define FLAG_OUID0_SHIFT	U(8)
+#define FLAG_OUID1_SHIFT	U(9)
+#define FLAG_OUID2_SHIFT	U(10)
+#define FLAG_OUID3_SHIFT	U(11)
+#define FLAG_OUID4_SHIFT	U(12)
+#define FLAG_DBG_LVL_SHIFT	U(13)
+#define FLAG_OTPMK_SHIFT	U(16)
+#define FLAG_OUID_MASK		U(0x1F)
+#define FLAG_DEBUG_MASK		U(0xF)
+#define FLAG_OTPMK_MASK		U(0xF)
+
+/* OTPMK flag values */
+#define PROG_OTPMK_MIN		U(0x0)
+#define PROG_OTPMK_RANDOM	U(0x1)
+#define PROG_OTPMK_USER		U(0x2)
+#define PROG_OTPMK_RANDOM_MIN	U(0x5)
+#define PROG_OTPMK_USER_MIN	U(0x6)
+#define PROG_NO_OTPMK		U(0x8)
+
+#define OTPMK_MIM_BITS_MASK	U(0xF0000000)
+
+/* System configuration bit shifts */
+#define SCB_WP_SHIFT		U(0)
+#define SCB_ITS_SHIFT		U(2)
+#define SCB_NSEC_SHIFT		U(4)
+#define SCB_ZD_SHIFT		U(5)
+#define SCB_K0_SHIFT		U(15)
+#define SCB_K1_SHIFT		U(14)
+#define SCB_K2_SHIFT		U(13)
+#define SCB_K3_SHIFT		U(12)
+#define SCB_K4_SHIFT		U(11)
+#define SCB_K5_SHIFT		U(10)
+#define SCB_K6_SHIFT		U(9)
+#define SCB_FR0_SHIFT		U(30)
+#define SCB_FR1_SHIFT		U(31)
+
+/* Fuse Header Structure */
+struct fuse_hdr_t {
+	uint8_t barker[4];          /* 0x00 Barker code */
+	uint32_t flags;             /* 0x04 Script flags */
+	uint32_t povdd_gpio;        /* 0x08 GPIO for POVDD */
+	uint32_t otpmk[8];          /* 0x0C-0x2B OTPMK */
+	uint32_t srkh[8];           /* 0x2C-0x4B SRKH */
+	uint32_t oem_uid[5];        /* 0x4C-0x5F OEM unique id's */
+	uint32_t dcv[2];            /* 0x60-0x67 Debug Challenge */
+	uint32_t drv[2];            /* 0x68-0x6F Debug Response */
+	uint32_t ospr1;             /* 0x70 OSPR1 */
+	uint32_t sc;                /* 0x74 OSPR0 (System Configuration) */
+	uint32_t reserved[2];       /* 0x78-0x7F Reserved */
+};
+
+/* Function to do fuse provisioning */
+int provision_fuses(unsigned long long fuse_scr_addr,
+		    bool en_povdd_status);
+
+#define EFUSE_POWERUP_DELAY_mSec	U(25)
+#endif	/* FUSE_PROV_H  */

drivers/nxp/sfp/sfp.c

+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+#include <caam.h>
+#include <common/debug.h>
+#include <drivers/delay_timer.h>
+#include <sfp.h>
+#include <sfp_error_codes.h>
+
+static uintptr_t g_nxp_sfp_addr;
+static uint32_t srk_hash[SRK_HASH_SIZE/sizeof(uint32_t)]
+					__aligned(CACHE_WRITEBACK_GRANULE);
+
+void sfp_init(uintptr_t nxp_sfp_addr)
+{
+	g_nxp_sfp_addr = nxp_sfp_addr;
+}
+
+uintptr_t get_sfp_addr(void)
+{
+	return g_nxp_sfp_addr;
+}
+
+uint32_t *get_sfp_srk_hash(void)
+{
+	struct sfp_ccsr_regs_t *sfp_ccsr_regs =
+			(void *) (g_nxp_sfp_addr + SFP_FUSE_REGS_OFFSET);
+	int i = 0;
+
+	/* Add comparison of hash with SFP hash here */
+	for (i = 0; i < SRK_HASH_SIZE/sizeof(uint32_t); i++)
+		srk_hash[i] =
+			mmio_read_32((uintptr_t)&sfp_ccsr_regs->srk_hash[i]);
+
+	return srk_hash;
+}
+
+void set_sfp_wr_disable(void)
+{
+	/*
+	 * Mark SFP Write Disable and Write Disable Lock
+	 * Bit to prevent write to SFP fuses like
+	 * OUID's, Key Revocation fuse etc
+	 */
+	void *sfpcr = (void *)(g_nxp_sfp_addr + SFP_SFPCR_OFFSET);
+	uint32_t sfpcr_val;
+
+	sfpcr_val = sfp_read32(sfpcr);
+	sfpcr_val |= (SFP_SFPCR_WD | SFP_SFPCR_WDL);
+	sfp_write32(sfpcr, sfpcr_val);
+}
+
+int sfp_program_fuses(void)
+{
+	uint32_t ingr;
+	uint32_t sfp_cmd_status = 0U;
+	int ret = 0;
+
+	/* Program SFP fuses from mirror registers */
+	sfp_write32((void *)(g_nxp_sfp_addr + SFP_INGR_OFFSET),
+		    SFP_INGR_PROGFB_CMD);
+
+	/* Wait until fuse programming is successful */
+	do {
+		ingr = sfp_read32(g_nxp_sfp_addr + SFP_INGR_OFFSET);
+	} while (ingr & SFP_INGR_PROGFB_CMD);
+
+	/* Check for SFP fuse programming error */
+	sfp_cmd_status = sfp_read32(g_nxp_sfp_addr + SFP_INGR_OFFSET)
+			 & SFP_INGR_ERROR_MASK;
+
+	if (sfp_cmd_status != 0U) {
+		return ERROR_PROGFB_CMD;
+	}
+
+	return ret;
+}
+
+uint32_t sfp_read_oem_uid(uint8_t oem_uid)
+{
+	uint32_t val = 0U;
+	struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(g_nxp_sfp_addr
+							+ SFP_FUSE_REGS_OFFSET);
+
+	if (oem_uid > MAX_OEM_UID) {
+		ERROR("Invalid OEM UID received.\n");
+		return ERROR_OEMUID_WRITE;
+	}
+
+	val = sfp_read32(&sfp_ccsr_regs->oem_uid[oem_uid]);
+
+	return val;
+}
+
+/*
+ * return val:  0 - No update required.
+ *              1 - successful update done.
+ *              ERROR_OEMUID_WRITE - Invalid OEM UID
+ */
+uint32_t sfp_write_oem_uid(uint8_t oem_uid, uint32_t sfp_val)
+{
+	uint32_t val = 0U;
+	struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(g_nxp_sfp_addr
+							+ SFP_FUSE_REGS_OFFSET);
+
+	val = sfp_read_oem_uid(oem_uid);
+
+	if (val == ERROR_OEMUID_WRITE) {
+		return ERROR_OEMUID_WRITE;
+	}
+
+	/* Counter already set. No need to do anything */
+	if ((val & sfp_val) != 0U) {
+		return 0U;
+	}
+
+	val |= sfp_val;
+
+	INFO("SFP Value is %x for setting sfp_val = %d\n", val, sfp_val);
+
+	sfp_write32(&sfp_ccsr_regs->oem_uid[oem_uid], val);
+
+	return 1U;
+}
+
+int sfp_check_its(void)
+{
+	struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(g_nxp_sfp_addr
+							+ SFP_FUSE_REGS_OFFSET);
+
+	if ((sfp_read32(&sfp_ccsr_regs->ospr) & OSPR_ITS_MASK) != 0) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+int sfp_check_oem_wp(void)
+{
+	struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(g_nxp_sfp_addr
+							+ SFP_FUSE_REGS_OFFSET);
+
+	if ((sfp_read32(&sfp_ccsr_regs->ospr) & OSPR_WP_MASK) != 0) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+/* This function returns ospr's key_revoc values.*/
+uint32_t get_key_revoc(void)
+{
+	struct sfp_ccsr_regs_t *sfp_ccsr_regs = (void *)(g_nxp_sfp_addr
+							+ SFP_FUSE_REGS_OFFSET);
+
+	return (sfp_read32(&sfp_ccsr_regs->ospr) & OSPR_KEY_REVOC_MASK) >>
+						OSPR_KEY_REVOC_SHIFT;
+}

drivers/nxp/sfp/sfp.h

+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SFP_H
+#define SFP_H
+
+#include <endian.h>
+#include <lib/mmio.h>
+
+/* SFP Configuration Register Offsets */
+#define SFP_INGR_OFFSET		U(0x20)
+#define SFP_SVHESR_OFFSET	U(0x24)
+#define SFP_SFPCR_OFFSET	U(0x28)
+#define SFP_VER_OFFSET		U(0x38)
+
+/* SFP Hamming register masks for OTPMK and DRV */
+#define SFP_SVHESR_DRV_MASK	U(0x7F)
+#define SFP_SVHESR_OTPMK_MASK	U(0x7FC00)
+
+/* SFP commands */
+#define SFP_INGR_READFB_CMD	U(0x1)
+#define SFP_INGR_PROGFB_CMD	U(0x2)
+#define SFP_INGR_ERROR_MASK	U(0x100)
+
+/* SFPCR Masks */
+#define SFP_SFPCR_WD		U(0x80000000)
+#define SFP_SFPCR_WDL		U(0x40000000)
+
+/* SFPCR Masks */
+#define SFP_SFPCR_WD		U(0x80000000)
+#define SFP_SFPCR_WDL		U(0x40000000)
+
+#define SFP_FUSE_REGS_OFFSET	U(0x200)
+
+#ifdef NXP_SFP_VER_3_4
+#define OSPR0_SC_MASK		U(0xC000FE35)
+#elif defined(NXP_SFP_VER_3_2)
+#define OSPR0_SC_MASK		U(0x0000E035)
+#endif
+
+#if defined(NXP_SFP_VER_3_4)
+#define OSPR_KEY_REVOC_SHIFT	U(9)
+#define OSPR_KEY_REVOC_MASK	U(0x0000fe00)
+#elif defined(NXP_SFP_VER_3_2)
+#define OSPR_KEY_REVOC_SHIFT	U(13)
+#define OSPR_KEY_REVOC_MASK	U(0x0000e000)
+#endif /* NXP_SFP_VER_3_4 */
+
+#define OSPR1_MC_MASK		U(0xFFFF0000)
+#define OSPR1_DBG_LVL_MASK	U(0x00000007)
+
+#define OSPR_ITS_MASK		U(0x00000004)
+#define OSPR_WP_MASK		U(0x00000001)
+
+#define MAX_OEM_UID		U(5)
+#define SRK_HASH_SIZE		U(32)
+
+/* SFP CCSR Register Map */
+struct sfp_ccsr_regs_t {
+	uint32_t ospr;			/* 0x200 OSPR0 */
+	uint32_t ospr1;			/* 0x204 OSPR1 */
+	uint32_t dcv[2];		/* 0x208 Debug Challenge Value */
+	uint32_t drv[2];		/* 0x210 Debug Response Value */
+	uint32_t fswpr;			/* 0x218 FSL Section Write Protect */
+	uint32_t fsl_uid[2];		/* 0x21c FSL UID 0 */
+	uint32_t isbcr;			/* 0x224 ISBC Configuration */
+	uint32_t fsspr[3];		/* 0x228 FSL Scratch Pad */
+	uint32_t otpmk[8];		/* 0x234 OTPMK */
+	uint32_t srk_hash[SRK_HASH_SIZE/sizeof(uint32_t)];
+					/* 0x254 Super Root Key Hash */
+	uint32_t oem_uid[MAX_OEM_UID];	/* 0x274 OEM UID 0 */
+};
+
+uintptr_t get_sfp_addr(void);
+void sfp_init(uintptr_t nxp_sfp_addr);
+uint32_t *get_sfp_srk_hash(void);
+int sfp_check_its(void);
+int sfp_check_oem_wp(void);
+uint32_t get_key_revoc(void);
+void set_sfp_wr_disable(void);
+int sfp_program_fuses(void);
+
+uint32_t sfp_read_oem_uid(uint8_t oem_uid);
+uint32_t sfp_write_oem_uid(uint8_t oem_uid, uint32_t sfp_val);
+
+#ifdef NXP_SFP_BE
+#define sfp_read32(a)           bswap32(mmio_read_32((uintptr_t)(a)))
+#define sfp_write32(a, v)       mmio_write_32((uintptr_t)(a), bswap32(v))
+#elif defined(NXP_SFP_LE)
+#define sfp_read32(a)           mmio_read_32((uintptr_t)(a))
+#define sfp_write32(a, v)       mmio_write_32((uintptr_t)(a), (v))
+#else
+#error Please define CCSR SFP register endianness
+#endif
+
+#endif/* SFP_H */

drivers/nxp/sfp/sfp.mk

+#
+# Copyright 2020 NXP
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+#-----------------------------------------------------------------------------
+ifeq (${SFP_ADDED},)
+
+SFP_ADDED		:= 1
+$(eval $(call add_define, NXP_SFP_ENABLED))
+
+SFP_DRIVERS_PATH	:=  ${PLAT_DRIVERS_PATH}/sfp
+
+PLAT_INCLUDES		+= -I$(SFP_DRIVERS_PATH)
+
+SFP_SOURCES		+= $(SFP_DRIVERS_PATH)/sfp.c
+
+ifeq (${FUSE_PROG}, 1)
+SFP_BL2_SOURCES		+= $(SFP_DRIVERS_PATH)/fuse_prov.c
+endif
+
+ifeq (${BL_COMM_SFP_NEEDED},yes)
+BL_COMMON_SOURCES	+= ${SFP_SOURCES}
+BL2_SOURCES		+= ${SFP_BL2_SOURCES}
+else
+ifeq (${BL2_SFP_NEEDED},yes)
+BL2_SOURCES		+= ${SFP_SOURCES}\
+			   ${SFP_BL2_SOURCES}
+endif
+ifeq (${BL31_SFP_NEEDED},yes)
+BL31_SOURCES		+= ${SFP_SOURCES}
+endif
+endif
+endif
+#------------------------------------------------

drivers/nxp/sfp/sfp_error_codes.h

+/*
+ * Copyright 2021 NXP
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ *
+ */
+
+#ifndef SFP_ERROR_CODES_H
+#define SFP_ERROR_CODES_H
+
+ /* Error codes */
+#define ERROR_FUSE_BARKER		0x1
+#define ERROR_READFB_CMD		0x2
+#define ERROR_PROGFB_CMD		0x3
+#define ERROR_SRKH_ALREADY_BLOWN	0x4
+#define ERROR_SRKH_WRITE		0x5
+#define ERROR_OEMUID_ALREADY_BLOWN	0x6
+#define ERROR_OEMUID_WRITE		0x7
+#define ERROR_DCV_ALREADY_BLOWN		0x8
+#define ERROR_DCV_WRITE			0x9
+#define ERROR_DRV_ALREADY_BLOWN		0xa
+#define ERROR_DRV_HAMMING_ERROR		0xb
+#define ERROR_DRV_WRITE			0x18
+#define ERROR_OTPMK_ALREADY_BLOWN	0xc
+#define ERROR_OTPMK_HAMMING_ERROR	0xd
+#define ERROR_OTPMK_USER_MIN		0xe
+#define ERROR_OSPR1_ALREADY_BLOWN	0xf
+#define ERROR_OSPR1_WRITE		0x10
+#define ERROR_SC_ALREADY_BLOWN		0x11
+#define ERROR_SC_WRITE			0x12
+#define ERROR_POVDD_GPIO_FAIL		0x13
+#define ERROR_GPIO_SET_FAIL		0x14
+#define ERROR_GPIO_RESET_FAIL		0x15
+#define ERROR_OTPMK_SEC_DISABLED	0x16
+#define ERROR_OTPMK_SEC_ERROR		0x17
+#define ERROR_OTPMK_WRITE		0x19
+#define PLAT_ERROR_ENABLE_POVDD		0x20
+#define PLAT_ERROR_DISABLE_POVDD	0x21
+
+#endif /* SFP_ERROR_CODES_H */