Change comments in assembler files to help ctags

Ctags seem to have a problem with generating tags for assembler symbols
when a comment immediately follows an assembly label.

This patch inserts a single space character between the label
definition and the following comments to help ctags.

The patch is generated by the command:

  git ls-files -- \*.S | xargs sed -i 's/^\([^:]\+\):;/\1: ;/1'

Change-Id: If7a3c9d0f51207ea033cc8b8e1b34acaa0926475

arch/aarch64/cpu/cpu_helpers.S

@@ -35,7 +35,7 @@
 
 	.section	.text, "ax"; .align 3
 
-cpu_reset_handler:; .type cpu_reset_handler, %function
+cpu_reset_handler: ; .type cpu_reset_handler, %function
 	mov	x19, x30 // lr
 
 	/* ---------------------------------------------

arch/system/gic/aarch64/gic_v3_sysregs.S

@@ -50,40 +50,40 @@
 
 	.section	.text, "ax"; .align 3
 
-read_icc_sre_el1:; .type read_icc_sre_el1, %function
+read_icc_sre_el1: ; .type read_icc_sre_el1, %function
 	mrs	x0, ICC_SRE_EL1
 	ret
 
 
-read_icc_sre_el2:; .type read_icc_sre_el2, %function
+read_icc_sre_el2: ; .type read_icc_sre_el2, %function
 	mrs	x0, ICC_SRE_EL2
 	ret
 
 
-read_icc_sre_el3:; .type read_icc_sre_el3, %function
+read_icc_sre_el3: ; .type read_icc_sre_el3, %function
 	mrs	x0, ICC_SRE_EL3
 	ret
 
 
-write_icc_sre_el1:; .type write_icc_sre_el1, %function
+write_icc_sre_el1: ; .type write_icc_sre_el1, %function
 	msr	ICC_SRE_EL1, x0
 	isb
 	ret
 
 
-write_icc_sre_el2:; .type write_icc_sre_el2, %function
+write_icc_sre_el2: ; .type write_icc_sre_el2, %function
 	msr	ICC_SRE_EL2, x0
 	isb
 	ret
 
 
-write_icc_sre_el3:; .type write_icc_sre_el3, %function
+write_icc_sre_el3: ; .type write_icc_sre_el3, %function
 	msr	ICC_SRE_EL3, x0
 	isb
 	ret
 
 
-write_icc_pmr_el1:; .type write_icc_pmr_el1, %function
+write_icc_pmr_el1: ; .type write_icc_pmr_el1, %function
 	msr	ICC_PMR_EL1, x0
 	isb
 	ret

bl1/aarch64/bl1_entrypoint.S

@@ -42,7 +42,7 @@
 	 * -----------------------------------------------------
 	 */
 
-reset_handler:; .type reset_handler, %function
+reset_handler: ; .type reset_handler, %function
 	/* ---------------------------------------------
 	 * Perform any processor specific actions upon
 	 * reset e.g. cache, tlb invalidations etc.

bl2/aarch64/bl2_entrypoint.S

@@ -38,7 +38,7 @@
 	.section	.text, "ax"; .align 3
 
 
-bl2_entrypoint:; .type bl2_entrypoint, %function
+bl2_entrypoint: ; .type bl2_entrypoint, %function
 	/*---------------------------------------------
 	 * Store the extents of the tzram available to
 	 * BL2 for future use. Use the opcode param to

bl31/aarch64/bl31_entrypoint.S

@@ -44,7 +44,7 @@
 	 * -----------------------------------------------------
 	 */
 
-bl31_entrypoint:; .type bl31_entrypoint, %function
+bl31_entrypoint: ; .type bl31_entrypoint, %function
 	/* ---------------------------------------------
 	 * BL2 has populated x0,x3,x4 with the opcode
 	 * indicating BL31 should be run, memory layout

lib/arch/aarch64/cache_helpers.S

@@ -46,56 +46,56 @@
 
 	.section	.text, "ax"; .align 3
 
-dcisw:; .type dcisw, %function
+dcisw: ; .type dcisw, %function
 	dc	isw, x0
 	dsb	sy
 	isb
 	ret
 
 
-dccisw:; .type dccisw, %function
+dccisw: ; .type dccisw, %function
 	dc	cisw, x0
 	dsb	sy
 	isb
 	ret
 
 
-dccsw:; .type dccsw, %function
+dccsw: ; .type dccsw, %function
 	dc	csw, x0
 	dsb	sy
 	isb
 	ret
 
 
-dccvac:; .type dccvac, %function
+dccvac: ; .type dccvac, %function
 	dc	cvac, x0
 	dsb	sy
 	isb
 	ret
 
 
-dcivac:; .type dcivac, %function
+dcivac: ; .type dcivac, %function
 	dc	ivac, x0
 	dsb	sy
 	isb
 	ret
 
 
-dccivac:; .type dccivac, %function
+dccivac: ; .type dccivac, %function
 	dc	civac, x0
 	dsb	sy
 	isb
 	ret
 
 
-dccvau:; .type dccvau, %function
+dccvau: ; .type dccvau, %function
 	dc	cvau, x0
 	dsb	sy
 	isb
 	ret
 
 
-dczva:; .type dczva, %function
+dczva: ; .type dczva, %function
 	dc	zva, x0
 	dsb	sy
 	isb
@@ -107,7 +107,7 @@ dczva:; .type dczva, %function
 	 * size. 'x0' = addr, 'x1' = size
 	 * ------------------------------------------
 	 */
-flush_dcache_range:; .type flush_dcache_range, %function
+flush_dcache_range: ; .type flush_dcache_range, %function
 	dcache_line_size x2, x3
 	add	x1, x0, x1
 	sub	x3, x2, #1
@@ -126,7 +126,7 @@ flush_loop:
 	 * size. 'x0' = addr, 'x1' = size
 	 * ------------------------------------------
 	 */
-inv_dcache_range:; .type inv_dcache_range, %function
+inv_dcache_range: ; .type inv_dcache_range, %function
 	dcache_line_size x2, x3
 	add	x1, x0, x1
 	sub	x3, x2, #1
@@ -151,7 +151,7 @@ inv_loop:
 	 * x14
 	 * ----------------------------------
 	 */
-dcsw_op:; .type dcsw_op, %function
+dcsw_op: ; .type dcsw_op, %function
 all_start_at_level:
 	add	x2, x10, x10, lsr #1            // work out 3x current cache level
 	lsr	x1, x0, x2                      // extract cache type bits from clidr
@@ -197,7 +197,7 @@ finished:
 	ret
 
 
-do_dcsw_op:; .type do_dcsw_op, %function
+do_dcsw_op: ; .type do_dcsw_op, %function
 	cbz	x3, exit
 	cmp	x0, #DCISW
 	b.eq	dc_isw
@@ -221,13 +221,13 @@ exit:
 	ret
 
 
-dcsw_op_louis:; .type dcsw_op_louis, %function
+dcsw_op_louis: ; .type dcsw_op_louis, %function
 	dsb	sy
 	setup_dcsw_op_args x10, x3, x9, #LOUIS_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
 	b	do_dcsw_op
 
 
-dcsw_op_all:; .type dcsw_op_all, %function
+dcsw_op_all: ; .type dcsw_op_all, %function
 	dsb	sy
 	setup_dcsw_op_args x10, x3, x9, #LOC_SHIFT, #CLIDR_FIELD_WIDTH, #LEVEL_SHIFT
 	b	do_dcsw_op

lib/arch/aarch64/misc_helpers.S

@@ -84,7 +84,7 @@
 
 	.section	.text, "ax"
 
-save_regs:; .type save_regs, %function
+save_regs: ; .type save_regs, %function
 	sub	sp, sp, #GPREGS_FP_OFF
 	stp	x0, x1, [sp, #GPREGS_X0_OFF]
 	stp	x2, x3, [sp, #GPREGS_X2_OFF]
@@ -107,7 +107,7 @@ save_regs:; .type save_regs, %function
 	ret
 
 
-restore_regs:; .type restore_regs, %function
+restore_regs: ; .type restore_regs, %function
 	ldr	w9, [sp, #GPREGS_SPSR_OFF]
 	msr	spsr_el3, x9
 	ldp	x28, x9, [sp, #GPREGS_X28_OFF]
@@ -129,14 +129,14 @@ restore_regs:; .type restore_regs, %function
 	add	sp, sp, #GPREGS_FP_OFF
 	ret
 
-get_afflvl_shift:; .type get_afflvl_shift, %function
+get_afflvl_shift: ; .type get_afflvl_shift, %function
 	cmp	x0, #3
 	cinc	x0, x0, eq
 	mov	x1, #MPIDR_AFFLVL_SHIFT
 	lsl	x0, x0, x1
 	ret
 
-mpidr_mask_lower_afflvls:; .type mpidr_mask_lower_afflvls, %function
+mpidr_mask_lower_afflvls: ; .type mpidr_mask_lower_afflvls, %function
 	cmp	x1, #3
 	cinc	x1, x1, eq
 	mov	x2, #MPIDR_AFFLVL_SHIFT
@@ -149,17 +149,17 @@ mpidr_mask_lower_afflvls:; .type mpidr_mask_lower_afflvls, %function
 	 * Asynchronous exception manipulation accessors
 	 * -----------------------------------------------------
 	 */
-enable_irq:; .type enable_irq, %function
+enable_irq: ; .type enable_irq, %function
 	msr	daifclr, #DAIF_IRQ_BIT
 	ret
 
 
-enable_fiq:; .type enable_fiq, %function
+enable_fiq: ; .type enable_fiq, %function
 	msr	daifclr, #DAIF_FIQ_BIT
 	ret
 
 
-enable_serror:; .type enable_serror, %function
+enable_serror: ; .type enable_serror, %function
 	msr	daifclr, #DAIF_ABT_BIT
 	ret
 
@@ -169,17 +169,17 @@ enable_debug_exceptions:
 	ret
 
 
-disable_irq:; .type disable_irq, %function
+disable_irq: ; .type disable_irq, %function
 	msr	daifset, #DAIF_IRQ_BIT
 	ret
 
 
-disable_fiq:; .type disable_fiq, %function
+disable_fiq: ; .type disable_fiq, %function
 	msr	daifset, #DAIF_FIQ_BIT
 	ret
 
 
-disable_serror:; .type disable_serror, %function
+disable_serror: ; .type disable_serror, %function
 	msr	daifset, #DAIF_ABT_BIT
 	ret
 
@@ -189,17 +189,17 @@ disable_debug_exceptions:
 	ret
 
 
-read_daif:; .type read_daif, %function
+read_daif: ; .type read_daif, %function
 	mrs	x0, daif
 	ret
 
 
-write_daif:; .type write_daif, %function
+write_daif: ; .type write_daif, %function
 	msr	daif, x0
 	ret
 
 
-read_spsr:; .type read_spsr, %function
+read_spsr: ; .type read_spsr, %function
 	mrs	x0, CurrentEl
 	cmp	x0, #(MODE_EL1 << MODE_EL_SHIFT)
 	b.eq	read_spsr_el1
@@ -209,22 +209,22 @@ read_spsr:; .type read_spsr, %function
 	b.eq	read_spsr_el3
 
 
-read_spsr_el1:; .type read_spsr_el1, %function
+read_spsr_el1: ; .type read_spsr_el1, %function
 	mrs	x0, spsr_el1
 	ret
 
 
-read_spsr_el2:; .type read_spsr_el2, %function
+read_spsr_el2: ; .type read_spsr_el2, %function
 	mrs	x0, spsr_el2
 	ret
 
 
-read_spsr_el3:; .type read_spsr_el3, %function
+read_spsr_el3: ; .type read_spsr_el3, %function
 	mrs	x0, spsr_el3
 	ret
 
 
-write_spsr:; .type write_spsr, %function
+write_spsr: ; .type write_spsr, %function
 	mrs	x1, CurrentEl
 	cmp	x1, #(MODE_EL1 << MODE_EL_SHIFT)
 	b.eq	write_spsr_el1
@@ -234,25 +234,25 @@ write_spsr:; .type write_spsr, %function
 	b.eq	write_spsr_el3
 
 
-write_spsr_el1:; .type write_spsr_el1, %function
+write_spsr_el1: ; .type write_spsr_el1, %function
 	msr	spsr_el1, x0
 	isb
 	ret
 
 
-write_spsr_el2:; .type write_spsr_el2, %function
+write_spsr_el2: ; .type write_spsr_el2, %function
 	msr	spsr_el2, x0
 	isb
 	ret
 
 
-write_spsr_el3:; .type write_spsr_el3, %function
+write_spsr_el3: ; .type write_spsr_el3, %function
 	msr	spsr_el3, x0
 	isb
 	ret
 
 
-read_elr:; .type read_elr, %function
+read_elr: ; .type read_elr, %function
 	mrs	x0, CurrentEl
 	cmp	x0, #(MODE_EL1 << MODE_EL_SHIFT)
 	b.eq	read_elr_el1
@@ -262,22 +262,22 @@ read_elr:; .type read_elr, %function
 	b.eq	read_elr_el3
 
 
-read_elr_el1:; .type read_elr_el1, %function
+read_elr_el1: ; .type read_elr_el1, %function
 	mrs	x0, elr_el1
 	ret
 
 
-read_elr_el2:; .type read_elr_el2, %function
+read_elr_el2: ; .type read_elr_el2, %function
 	mrs	x0, elr_el2
 	ret
 
 
-read_elr_el3:; .type read_elr_el3, %function
+read_elr_el3: ; .type read_elr_el3, %function
 	mrs	x0, elr_el3
 	ret
 
 
-write_elr:; .type write_elr, %function
+write_elr: ; .type write_elr, %function
 	mrs	x1, CurrentEl
 	cmp	x1, #(MODE_EL1 << MODE_EL_SHIFT)
 	b.eq	write_elr_el1
@@ -287,54 +287,54 @@ write_elr:; .type write_elr, %function
 	b.eq	write_elr_el3
 
 
-write_elr_el1:; .type write_elr_el1, %function
+write_elr_el1: ; .type write_elr_el1, %function
 	msr	elr_el1, x0
 	isb
 	ret
 
 
-write_elr_el2:; .type write_elr_el2, %function
+write_elr_el2: ; .type write_elr_el2, %function
 	msr	elr_el2, x0
 	isb
 	ret
 
 
-write_elr_el3:; .type write_elr_el3, %function
+write_elr_el3: ; .type write_elr_el3, %function
 	msr	elr_el3, x0
 	isb
 	ret
 
 
-dsb:; .type dsb, %function
+dsb: ; .type dsb, %function
 	dsb	sy
 	ret
 
 
-isb:; .type isb, %function
+isb: ; .type isb, %function
 	isb
 	ret
 
 
-sev:; .type sev, %function
+sev: ; .type sev, %function
 	sev
 	ret
 
 
-wfe:; .type wfe, %function
+wfe: ; .type wfe, %function
 	wfe
 	ret
 
 
-wfi:; .type wfi, %function
+wfi: ; .type wfi, %function
 	wfi
 	ret
 
 
-eret:; .type eret, %function
+eret: ; .type eret, %function
 	eret
 
 
-smc:; .type smc, %function
+smc: ; .type smc, %function
 	smc	#0
 
 /* -----------------------------------------------------------------------

lib/arch/aarch64/tlb_helpers.S

@@ -41,48 +41,48 @@
 
 	.section	.text, "ax"
 
-tlbialle1:; .type tlbialle1, %function
+tlbialle1: ; .type tlbialle1, %function
 	tlbi	alle1
 	dsb	sy
 	isb
 	ret
 
 
-tlbialle1is:; .type tlbialle1is, %function
+tlbialle1is: ; .type tlbialle1is, %function
 	tlbi	alle1is
 	dsb	sy
 	isb
 	ret
 
 
-tlbialle2:; .type tlbialle2, %function
+tlbialle2: ; .type tlbialle2, %function
 	tlbi	alle2
 	dsb	sy
 	isb
 	ret
 
 
-tlbialle2is:; .type tlbialle2is, %function
+tlbialle2is: ; .type tlbialle2is, %function
 	tlbi	alle2is
 	dsb	sy
 	isb
 	ret
 
 
-tlbialle3:; .type tlbialle3, %function
+tlbialle3: ; .type tlbialle3, %function
 	tlbi	alle3
 	dsb	sy
 	isb
 	ret
 
 
-tlbialle3is:; .type tlbialle3is, %function
+tlbialle3is: ; .type tlbialle3is, %function
 	tlbi	alle3is
 	dsb	sy
 	isb
 	ret
 
-tlbivmalle1:; .type tlbivmalle1, %function
+tlbivmalle1: ; .type tlbivmalle1, %function
 	tlbi	vmalle1
 	dsb	sy
 	isb

lib/semihosting/aarch64/semihosting_call.S

@@ -32,6 +32,6 @@
 
 	.section	.text, "ax"
 
-semihosting_call:; .type semihosting_call, %function
+semihosting_call: ; .type semihosting_call, %function
 	hlt	#0xf000
 	ret

lib/sync/locks/exclusive/spinlock.S

@@ -34,7 +34,7 @@
 
 	.section	.text, "ax";
 
-spin_lock:; .type spin_lock, %function
+spin_lock: ; .type spin_lock, %function
 	mov	w2, #1
 	sevl
 l1:	wfe
@@ -45,6 +45,6 @@ l2:	ldaxr	w1, [x0]
 	ret
 
 
-spin_unlock:; .type spin_unlock, %function
+spin_unlock: ; .type spin_unlock, %function
 	stlr	wzr, [x0]
 	ret

plat/common/aarch64/platform_helpers.S

@@ -59,7 +59,7 @@
 	 * SCTLR.C bit e.g. while powering down a cpu
 	 * -----------------------------------------------------
 	 */
-platform_set_coherent_stack:; .type platform_set_coherent_stack, %function
+platform_set_coherent_stack: ; .type platform_set_coherent_stack, %function
 	mov	x5, x30 // lr
 	bl	platform_get_core_pos
 	add	x0, x0, #1
@@ -76,7 +76,7 @@ platform_set_coherent_stack:; .type platform_set_coherent_stack, %function
 	 *  				  CoreId
 	 * -----------------------------------------------------
 	 */
-platform_get_core_pos:; .type platform_get_core_pos, %function
+platform_get_core_pos: ; .type platform_get_core_pos, %function
 	and	x1, x0, #MPIDR_CPU_MASK
 	and	x0, x0, #MPIDR_CLUSTER_MASK
 	add	x0, x1, x0, LSR #6
@@ -90,7 +90,7 @@ platform_get_core_pos:; .type platform_get_core_pos, %function
 	 * cpu (applicable ony after a cold boot)
 	 * -----------------------------------------------------
 	 */
-platform_is_primary_cpu:; .type platform_is_primary_cpu, %function
+platform_is_primary_cpu: ; .type platform_is_primary_cpu, %function
 	and	x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
 	cmp	x0, #PRIMARY_CPU
 	cset	x0, eq
@@ -100,7 +100,7 @@ platform_is_primary_cpu:; .type platform_is_primary_cpu, %function
 	 * void platform_get_stack (unsigned long mpidr)
 	 * -----------------------------------------------------
 	 */
-platform_get_stack:; .type platform_get_stack, %function
+platform_get_stack: ; .type platform_get_stack, %function
 	mov	x10, x30 // lr
 	bl	platform_get_core_pos
 	add	x0, x0, #1
@@ -114,7 +114,7 @@ platform_get_stack:; .type platform_get_stack, %function
 	 * void platform_set_stack (unsigned long mpidr)
 	 * -----------------------------------------------------
 	 */
-platform_set_stack:; .type platform_set_stack, %function
+platform_set_stack: ; .type platform_set_stack, %function
 	mov	x9, x30 // lr
 	bl	platform_get_stack
 	mov	sp, x0
@@ -125,7 +125,7 @@ platform_set_stack:; .type platform_set_stack, %function
 	 * each platform.
 	 * -----------------------------------------------------
 	 */
-platform_check_mpidr:; .type platform_check_mpidr, %function
+platform_check_mpidr: ; .type platform_check_mpidr, %function
 	mov	x0, xzr
 	ret
 

plat/fvp/aarch64/bl1_plat_helpers.S

@@ -60,7 +60,7 @@
 	 * that the request has gone through.
 	 * -----------------------------------------------------
 	 */
-plat_secondary_cold_boot_setup:; .type plat_secondary_cold_boot_setup, %function
+plat_secondary_cold_boot_setup: ; .type plat_secondary_cold_boot_setup, %function
 	bl	read_mpidr
 	mov	x19, x0
 	bl	platform_get_core_pos
@@ -136,7 +136,7 @@ cb_panic:
 	 * 	reset all cpus will read the same WK field
 	 * -----------------------------------------------------
 	 */
-platform_get_entrypoint:; .type platform_get_entrypoint, %function
+platform_get_entrypoint: ; .type platform_get_entrypoint, %function
 	mov	x9, x30 // lr
 	mov	x2, x0
 	ldr	x1, =PWRC_BASE
@@ -176,7 +176,7 @@ _panic:	b	_panic
 	 * BL1 will always read the mailboxes with the MMU off
 	 * -----------------------------------------------------
 	 */
-platform_mem_init:; .type platform_mem_init, %function
+platform_mem_init: ; .type platform_mem_init, %function
 	ldr	x0, =TZDRAM_BASE + MBOX_OFF
 	stp	xzr, xzr, [x0, #0]
 	stp	xzr, xzr, [x0, #0x10]
@@ -192,7 +192,7 @@ platform_mem_init:; .type platform_mem_init, %function
 	 * boot to perform early platform initialization
 	 * -----------------------------------------------------
 	 */
-platform_cold_boot_init:; .type platform_cold_boot_init, %function
+platform_cold_boot_init: ; .type platform_cold_boot_init, %function
 	mov	x20, x0
 	bl	platform_mem_init
 	bl	read_mpidr