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Commit 3c0024cc authored by Grzegorz Jaszczyk's avatar Grzegorz Jaszczyk Committed by Konstantin Porotchkin
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mvebu: cp110: fix spelling in register definition 



Use PF instead of PP post-fix, since it is referring to "Phase Final"
(only G3 related register had correct spelling for relevant bit).

Change-Id: Ia5a9c9c78b74b15f7f8adde2c3ef4784c513da2c
Signed-off-by: default avatarGrzegorz Jaszczyk <jaz@semihalf.com>
Reviewed-by: default avatarIgal Liberman <igall@marvell.com>
Reviewed-by: default avatarKostya Porotchkin <kostap@marvell.com>
parent f858e989
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Inline Side-by-side
drivers/marvell/comphy/comphy-cp110.h
View file @ 3c0024cc
...@@ -217,9 +217,9 @@ ...@@ -217,9 +217,9 @@
#define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0 #define HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET 0
#define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \ #define HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK \
(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET) (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET)
#define HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET 3 #define HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET 3
#define HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK \ #define HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK \
(0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET) (0x7 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET)
#define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6 #define HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET 6
#define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \ #define HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK \
(0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET) (0x3 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET)
...@@ -251,9 +251,9 @@ ...@@ -251,9 +251,9 @@
#define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0 #define HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET 0
#define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \ #define HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK \
(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET) (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET)
#define HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET 3 #define HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET 3
#define HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK \ #define HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK \
(0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET) (0x7 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET)
#define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6 #define HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET 6
#define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \ #define HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK \
(0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET) (0x3 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET)
......
drivers/marvell/comphy/phy-comphy-cp110.c
View file @ 3c0024cc
...@@ -481,8 +481,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, ...@@ -481,8 +481,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
/* G1 settings */ /* G1 settings */
mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; data = 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
...@@ -506,8 +506,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base, ...@@ -506,8 +506,8 @@ static int mvebu_cp110_comphy_sata_power_on(uint64_t comphy_base,
/* G2 settings */ /* G2 settings */
mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK;
data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET;
mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK; mask |= HPIPE_G2_SET_1_G2_RX_SELMUFF_MASK;
...@@ -1000,13 +1000,13 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base, ...@@ -1000,13 +1000,13 @@ static int mvebu_cp110_comphy_xfi_power_on(uint64_t comphy_base,
if (speed == COMPHY_SPEED_5_15625G) { if (speed == COMPHY_SPEED_5_15625G) {
mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
} else { } else {
mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; mask |= HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; data |= 0x2 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK; mask |= HPIPE_G1_SET_1_G1_RX_SELMUFI_MASK;
data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET; data |= 0x0 << HPIPE_G1_SET_1_G1_RX_SELMUFI_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK; mask |= HPIPE_G1_SET_1_G1_RX_SELMUFF_MASK;
...@@ -1504,8 +1504,8 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base, ...@@ -1504,8 +1504,8 @@ static int mvebu_cp110_comphy_pcie_power_on(uint64_t comphy_base,
/* Genration 2 setting 1*/ /* Genration 2 setting 1*/
mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK; mask = HPIPE_G2_SET_1_G2_RX_SELMUPI_MASK;
data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET; data = 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUPI_OFFSET;
mask |= HPIPE_G2_SET_1_G2_RX_SELMUPP_MASK; mask |= HPIPE_G2_SET_1_G2_RX_SELMUPF_MASK;
data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPP_OFFSET; data |= 0x1 << HPIPE_G2_SET_1_G2_RX_SELMUPF_OFFSET;
mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK; mask |= HPIPE_G2_SET_1_G2_RX_SELMUFI_MASK;
data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET; data |= 0x0 << HPIPE_G2_SET_1_G2_RX_SELMUFI_OFFSET;
reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask); reg_set(hpipe_addr + HPIPE_G2_SET_1_REG, data, mask);
...@@ -1741,8 +1741,8 @@ static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base, ...@@ -1741,8 +1741,8 @@ static int mvebu_cp110_comphy_rxaui_power_on(uint64_t comphy_base,
/* 0xE-G1_Setting_1 */ /* 0xE-G1_Setting_1 */
mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK; mask = HPIPE_G1_SET_1_G1_RX_SELMUPI_MASK;
data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET; data = 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPI_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_SELMUPP_MASK; mask |= HPIPE_G1_SET_1_G1_RX_SELMUPF_MASK;
data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPP_OFFSET; data |= 0x1 << HPIPE_G1_SET_1_G1_RX_SELMUPF_OFFSET;
mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK; mask |= HPIPE_G1_SET_1_G1_RX_DFE_EN_MASK;
data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET; data |= 0x1 << HPIPE_G1_SET_1_G1_RX_DFE_EN_OFFSET;
reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask); reg_set(hpipe_addr + HPIPE_G1_SET_1_REG, data, mask);
......
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