rockchip: Use coreboot-supplied serial console on coreboot systems

This patch changes all Rockchip platforms to initialize the serial
console with information supplied by coreboot rather than hardcoded
base address and divisor values if BL31 is run on top of coreboot.
Moving the BL2-to-BL31 parameter parsing as early as possible to ensure
that the console is available for all following code.

Also update the Rockchip platform to use MULTI_CONSOLE_API.

Change-Id: I670d350fa2f8b8133539f91ac14977ab47db60d9
Signed-off-by: Julius Werner <jwerner@chromium.org>

plat/rockchip/common/bl31_plat_setup.c

@@ -8,12 +8,14 @@
 #include <assert.h>
 #include <bl_common.h>
 #include <console.h>
+#include <coreboot.h>
 #include <debug.h>
 #include <generic_delay_timer.h>
 #include <mmio.h>
 #include <plat_private.h>
 #include <platform.h>
 #include <platform_def.h>
+#include <uart_16550.h>
 
 /*******************************************************************************
  * Declarations of linker defined symbols which will help us find the layout
@@ -69,8 +71,16 @@ void params_early_setup(void *plat_param_from_bl2)
 void bl31_early_platform_setup(bl31_params_t *from_bl2,
 			       void *plat_params_from_bl2)
 {
+	params_early_setup(plat_params_from_bl2);
+
+#if COREBOOT
+	if (coreboot_serial.type)
+		console_init(coreboot_serial.baseaddr,
+			     coreboot_serial.input_hertz, coreboot_serial.baud);
+#else
 	console_init(PLAT_RK_UART_BASE, PLAT_RK_UART_CLOCK,
 		     PLAT_RK_UART_BAUDRATE);
+#endif
 
 	VERBOSE("bl31_setup\n");
 
@@ -82,9 +92,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
 
 	bl32_ep_info = *from_bl2->bl32_ep_info;
 	bl33_ep_info = *from_bl2->bl33_ep_info;
-
-	/* there may have some board sepcific message need to initialize */
-	params_early_setup(plat_params_from_bl2);
 }
 
 /*******************************************************************************

plat/rockchip/common/include/plat_params.h

@@ -56,6 +56,7 @@ enum {
 	PARAM_POWEROFF,
 	PARAM_SUSPEND_GPIO,
 	PARAM_SUSPEND_APIO,
+	PARAM_COREBOOT_TABLE,
 };
 
 struct apio_info {
@@ -89,4 +90,9 @@ struct bl31_apio_param {
 	struct apio_info apio;
 };
 
+struct bl31_u64_param {
+	struct bl31_plat_param h;
+	uint64_t value;
+};
+
 #endif /* __PLAT_PARAMS_H__ */

plat/rockchip/common/params_setup.c

@@ -8,6 +8,7 @@
 #include <assert.h>
 #include <bl_common.h>
 #include <console.h>
+#include <coreboot.h>
 #include <debug.h>
 #include <gpio.h>
 #include <mmio.h>
@@ -84,6 +85,12 @@ void params_early_setup(void *plat_param_from_bl2)
 			       sizeof(struct bl31_apio_param));
 			suspend_apio = &param_apio.apio;
 			break;
+#if COREBOOT
+		case PARAM_COREBOOT_TABLE:
+			coreboot_table_setup((void *)
+				((struct bl31_u64_param *)bl2_param)->value);
+			break;
+#endif
 		default:
 			ERROR("not expected type found %ld\n",
 			      bl2_param->type);

plat/rockchip/rk3328/platform.mk

@@ -50,6 +50,8 @@ BL31_SOURCES		+=	${RK_GIC_SOURCES}				\
 
 ENABLE_PLAT_COMPAT 	:=	0
 
+include lib/coreboot/coreboot.mk
+
 $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
 $(eval $(call add_define,PLAT_SKIP_OPTEE_S_EL1_INT_REGISTER))
 

plat/rockchip/rk3368/platform.mk

@@ -50,6 +50,8 @@ BL31_SOURCES		+=	${RK_GIC_SOURCES}				\
 
 ENABLE_PLAT_COMPAT	:=	0
 
+include lib/coreboot/coreboot.mk
+
 $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
 
 # Do not enable SVE

plat/rockchip/rk3399/platform.mk

@@ -65,6 +65,8 @@ BL31_SOURCES	+=	${RK_GIC_SOURCES}				\
 
 ENABLE_PLAT_COMPAT	:=	0
 
+include lib/coreboot/coreboot.mk
+
 $(eval $(call add_define,PLAT_EXTRA_LD_SCRIPT))
 
 # Enable workarounds for selected Cortex-A53 erratas.