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Commit 3d21c945 authored by davidcunado-arm's avatar davidcunado-arm Committed by GitHub
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Merge pull request #899 from vwadekar/tegra186-platform-support-v6 

Tegra186 platform support v6
parents ea69a93e 50e91633
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with 1390 additions and 1497 deletions
+1390 -1497
include/lib/aarch64/arch.h
View file @ 3d21c945
......@@ -419,6 +419,10 @@
#define EC_BITS(x) (x >> ESR_EC_SHIFT) & ESR_EC_MASK
/* Reset bit inside the Reset management register for EL3 (RMR_EL3) */
#define RMR_RESET_REQUEST_SHIFT 0x1u
#define RMR_WARM_RESET_CPU (1u << RMR_RESET_REQUEST_SHIFT)
/*******************************************************************************
* Definitions of register offsets, fields and macros for CPU system
* instructions.
......
plat/nvidia/tegra/common/aarch64/tegra_helpers.S
View file @ 3d21c945
......@@ -243,11 +243,12 @@ endfunc platform_mem_init
* ---------------------------------------------
*/
func plat_crash_console_init
adr x0, tegra_console_base
ldr x0, [x0]
mov_imm x1, TEGRA_BOOT_UART_CLK_IN_HZ
mov_imm x2, TEGRA_CONSOLE_BAUDRATE
b console_core_init
mov x0, #0
adr x1, tegra_console_base
ldr x1, [x1]
cbz x1, 1f
mov w0, #1
1: ret
endfunc plat_crash_console_init
/* ---------------------------------------------
......
plat/nvidia/tegra/common/drivers/memctrl/memctrl_v1.c
View file @ 3d21c945
......@@ -217,3 +217,29 @@ done:
video_mem_base = phys_base;
video_mem_size = size_in_bytes >> 20;
}
/*
* During boot, USB3 and flash media (SDMMC/SATA) devices need access to
* IRAM. Because these clients connect to the MC and do not have a direct
* path to the IRAM, the MC implements AHB redirection during boot to allow
* path to IRAM. In this mode, accesses to a programmed memory address aperture
* are directed to the AHB bus, allowing access to the IRAM. The AHB aperture
* is defined by the IRAM_BASE_LO and IRAM_BASE_HI registers, which are
* initialized to disable this aperture.
*
* Once bootup is complete, we must program IRAM base to 0xffffffff and
* IRAM top to 0x00000000, thus disabling access to IRAM. DRAM is then
* potentially accessible in this address range. These aperture registers
* also have an access_control/lock bit. After disabling the aperture, the
* access_control register should be programmed to lock the registers.
*/
void tegra_memctrl_disable_ahb_redirection(void)
{
/* program the aperture registers */
tegra_mc_write_32(MC_IRAM_BASE_LO, 0xFFFFFFFF);
tegra_mc_write_32(MC_IRAM_TOP_LO, 0);
tegra_mc_write_32(MC_IRAM_BASE_TOP_HI, 0);
/* lock the aperture registers */
tegra_mc_write_32(MC_IRAM_REG_CTRL, MC_DISABLE_IRAM_CFG_WRITES);
}
plat/nvidia/tegra/common/drivers/memctrl/memctrl_v2.c
View file @ 3d21c945
......@@ -30,6 +30,7 @@
#include <arch_helpers.h>
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
#include <mce.h>
#include <memctrl.h>
......@@ -305,6 +306,58 @@ static void tegra_memctrl_reconfig_mss_clients(void)
#endif
}
static void tegra_memctrl_set_overrides(void)
{
tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
const mc_txn_override_cfg_t *mc_txn_override_cfgs;
uint32_t num_txn_override_cfgs;
uint32_t i, val;
/* Get the settings from the platform */
assert(plat_mc_settings);
mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
/*
* Set the MC_TXN_OVERRIDE registers for write clients.
*/
if ((tegra_chipid_is_t186()) &&
(!tegra_platform_is_silicon() ||
(tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1)))) {
/*
* GPU and NVENC settings for Tegra186 simulation and
* Silicon rev. A01
*/
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2,
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR,
val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
} else {
/*
* Settings for Tegra186 silicon rev. A02 and onwards.
*/
for (i = 0; i < num_txn_override_cfgs; i++) {
val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
val | mc_txn_override_cfgs[i].cgid_tag);
}
}
}
/*
* Init Memory controller during boot.
*/
......@@ -315,10 +368,8 @@ void tegra_memctrl_setup(void)
uint32_t num_streamid_override_regs;
const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs;
uint32_t num_streamid_sec_cfgs;
const mc_txn_override_cfg_t *mc_txn_override_cfgs;
uint32_t num_txn_override_cfgs;
tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
int i;
uint32_t i;
INFO("Tegra Memory Controller (v2)\n");
......@@ -332,8 +383,6 @@ void tegra_memctrl_setup(void)
num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs;
mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg;
num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs;
mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
/* Program all the Stream ID overrides */
for (i = 0; i < num_streamid_override_regs; i++)
......@@ -372,39 +421,8 @@ void tegra_memctrl_setup(void)
*/
tegra_memctrl_reconfig_mss_clients();
/*
* Set the MC_TXN_OVERRIDE registers for write clients.
*/
if (!tegra_platform_is_silicon() ||
(tegra_platform_is_silicon() && tegra_get_chipid_minor() == 1)) {
/* GPU and NVENC settings for rev. A01 */
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2,
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR,
val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
} else {
/* settings for rev. A02 */
for (i = 0; i < num_txn_override_cfgs; i++) {
val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
val | mc_txn_override_cfgs[i].cgid_tag);
}
}
/* Program overrides for MC transactions */
tegra_memctrl_set_overrides();
}
/*
......@@ -420,6 +438,9 @@ void tegra_memctrl_restore_settings(void)
*/
tegra_memctrl_reconfig_mss_clients();
/* Program overrides for MC transactions */
tegra_memctrl_set_overrides();
/* video memory carveout region */
if (video_mem_base) {
tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
......@@ -575,3 +596,11 @@ void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes)
*/
mce_update_gsc_videomem();
}
/*
* This feature exists only for v1 of the Tegra Memory Controller.
*/
void tegra_memctrl_disable_ahb_redirection(void)
{
; /* do nothing */
}
plat/nvidia/tegra/common/drivers/smmu/smmu.c
View file @ 3d21c945
......@@ -31,400 +31,56 @@
#include <assert.h>
#include <bl_common.h>
#include <debug.h>
#include <memctrl_v2.h>
#include <platform_def.h>
#include <smmu.h>
#include <string.h>
#include <tegra_private.h>
typedef struct smmu_regs {
uint32_t reg;
uint32_t val;
} smmu_regs_t;
#define mc_make_sid_override_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
.val = 0x00000000, \
}
#define mc_make_sid_security_cfg(name) \
{ \
.reg = TEGRA_MC_STREAMID_BASE + \
MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
MC_STREAMID_OVERRIDE_CFG_ ## name), \
.val = 0x00000000, \
}
#define smmu_make_gnsr0_sec_cfg(name) \
{ \
.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_ ## name, \
.val = 0x00000000, \
}
/*
* On ARM-SMMU, conditional offset to access secure aliases of non-secure registers
* is 0x400. So, add it to register address
*/
#define smmu_make_gnsr0_nsec_cfg(name) \
{ \
.reg = TEGRA_SMMU_BASE + 0x400 + SMMU_GNSR0_ ## name, \
.val = 0x00000000, \
}
#define smmu_make_gnsr0_smr_cfg(n) \
{ \
.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_SMR ## n, \
.val = 0x00000000, \
}
#define smmu_make_gnsr0_s2cr_cfg(n) \
{ \
.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_S2CR ## n, \
.val = 0x00000000, \
}
#define smmu_make_gnsr1_cbar_cfg(n) \
{ \
.reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \
.val = 0x00000000, \
}
#define smmu_make_gnsr1_cba2r_cfg(n) \
{ \
.reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \
.val = 0x00000000, \
}
/* SMMU IDs currently supported by the driver */
enum {
TEGRA_SMMU0,
TEGRA_SMMU1,
TEGRA_SMMU2
};
#define make_smmu_cb_cfg(name, n) \
{ \
.reg = TEGRA_SMMU_BASE + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \
+ SMMU_CBn_ ## name, \
.val = 0x00000000, \
}
static uint32_t tegra_smmu_read_32(uint32_t smmu_id, uint32_t off)
{
#if defined(TEGRA_SMMU0_BASE)
if (smmu_id == TEGRA_SMMU0)
return mmio_read_32(TEGRA_SMMU0_BASE + off);
#endif
#define smmu_make_smrg_group(n) \
smmu_make_gnsr0_smr_cfg(n), \
smmu_make_gnsr0_s2cr_cfg(n), \
smmu_make_gnsr1_cbar_cfg(n), \
smmu_make_gnsr1_cba2r_cfg(n) /* don't put "," here. */
#if defined(TEGRA_SMMU1_BASE)
if (smmu_id == TEGRA_SMMU1)
return mmio_read_32(TEGRA_SMMU1_BASE + off);
#endif
#define smmu_make_cb_group(n) \
make_smmu_cb_cfg(SCTLR, n), \
make_smmu_cb_cfg(TCR2, n), \
make_smmu_cb_cfg(TTBR0_LO, n), \
make_smmu_cb_cfg(TTBR0_HI, n), \
make_smmu_cb_cfg(TCR, n), \
make_smmu_cb_cfg(PRRR_MAIR0, n),\
make_smmu_cb_cfg(FSR, n), \
make_smmu_cb_cfg(FAR_LO, n), \
make_smmu_cb_cfg(FAR_HI, n), \
make_smmu_cb_cfg(FSYNR0, n) /* don't put "," here. */
#if defined(TEGRA_SMMU2_BASE)
if (smmu_id == TEGRA_SMMU2)
return mmio_read_32(TEGRA_SMMU2_BASE + off);
#endif
#define smmu_bypass_cfg \
{ \
.reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
.val = 0x00000000, \
}
return 0;
}
#define _START_OF_TABLE_ \
{ \
.reg = 0xCAFE05C7, \
.val = 0x00000000, \
}
static void tegra_smmu_write_32(uint32_t smmu_id,
uint32_t off, uint32_t val)
{
#if defined(TEGRA_SMMU0_BASE)
if (smmu_id == TEGRA_SMMU0)
mmio_write_32(TEGRA_SMMU0_BASE + off, val);
#endif
#define _END_OF_TABLE_ \
{ \
.reg = 0xFFFFFFFF, \
.val = 0xFFFFFFFF, \
}
#if defined(TEGRA_SMMU1_BASE)
if (smmu_id == TEGRA_SMMU1)
mmio_write_32(TEGRA_SMMU1_BASE + off, val);
#endif
static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = {
_START_OF_TABLE_,
mc_make_sid_security_cfg(SCEW),
mc_make_sid_security_cfg(AFIR),
mc_make_sid_security_cfg(NVDISPLAYR1),
mc_make_sid_security_cfg(XUSB_DEVR),
mc_make_sid_security_cfg(VICSRD1),
mc_make_sid_security_cfg(NVENCSWR),
mc_make_sid_security_cfg(TSECSRDB),
mc_make_sid_security_cfg(AXISW),
mc_make_sid_security_cfg(SDMMCWAB),
mc_make_sid_security_cfg(AONDMAW),
mc_make_sid_security_cfg(GPUSWR2),
mc_make_sid_security_cfg(SATAW),
mc_make_sid_security_cfg(UFSHCW),
mc_make_sid_security_cfg(AFIW),
mc_make_sid_security_cfg(SDMMCR),
mc_make_sid_security_cfg(SCEDMAW),
mc_make_sid_security_cfg(UFSHCR),
mc_make_sid_security_cfg(SDMMCWAA),
mc_make_sid_security_cfg(APEDMAW),
mc_make_sid_security_cfg(SESWR),
mc_make_sid_security_cfg(MPCORER),
mc_make_sid_security_cfg(PTCR),
mc_make_sid_security_cfg(BPMPW),
mc_make_sid_security_cfg(ETRW),
mc_make_sid_security_cfg(GPUSRD),
mc_make_sid_security_cfg(VICSWR),
mc_make_sid_security_cfg(SCEDMAR),
mc_make_sid_security_cfg(HDAW),
mc_make_sid_security_cfg(ISPWA),
mc_make_sid_security_cfg(EQOSW),
mc_make_sid_security_cfg(XUSB_HOSTW),
mc_make_sid_security_cfg(TSECSWR),
mc_make_sid_security_cfg(SDMMCRAA),
mc_make_sid_security_cfg(APER),
mc_make_sid_security_cfg(VIW),
mc_make_sid_security_cfg(APEW),
mc_make_sid_security_cfg(AXISR),
mc_make_sid_security_cfg(SDMMCW),
mc_make_sid_security_cfg(BPMPDMAW),
mc_make_sid_security_cfg(ISPRA),
mc_make_sid_security_cfg(NVDECSWR),
mc_make_sid_security_cfg(XUSB_DEVW),
mc_make_sid_security_cfg(NVDECSRD),
mc_make_sid_security_cfg(MPCOREW),
mc_make_sid_security_cfg(NVDISPLAYR),
mc_make_sid_security_cfg(BPMPDMAR),
mc_make_sid_security_cfg(NVJPGSWR),
mc_make_sid_security_cfg(NVDECSRD1),
mc_make_sid_security_cfg(TSECSRD),
mc_make_sid_security_cfg(NVJPGSRD),
mc_make_sid_security_cfg(SDMMCWA),
mc_make_sid_security_cfg(SCER),
mc_make_sid_security_cfg(XUSB_HOSTR),
mc_make_sid_security_cfg(VICSRD),
mc_make_sid_security_cfg(AONDMAR),
mc_make_sid_security_cfg(AONW),
mc_make_sid_security_cfg(SDMMCRA),
mc_make_sid_security_cfg(HOST1XDMAR),
mc_make_sid_security_cfg(EQOSR),
mc_make_sid_security_cfg(SATAR),
mc_make_sid_security_cfg(BPMPR),
mc_make_sid_security_cfg(HDAR),
mc_make_sid_security_cfg(SDMMCRAB),
mc_make_sid_security_cfg(ETRR),
mc_make_sid_security_cfg(AONR),
mc_make_sid_security_cfg(APEDMAR),
mc_make_sid_security_cfg(SESRD),
mc_make_sid_security_cfg(NVENCSRD),
mc_make_sid_security_cfg(GPUSWR),
mc_make_sid_security_cfg(TSECSWRB),
mc_make_sid_security_cfg(ISPWB),
mc_make_sid_security_cfg(GPUSRD2),
mc_make_sid_override_cfg(APER),
mc_make_sid_override_cfg(VICSRD),
mc_make_sid_override_cfg(NVENCSRD),
mc_make_sid_override_cfg(NVJPGSWR),
mc_make_sid_override_cfg(AONW),
mc_make_sid_override_cfg(BPMPR),
mc_make_sid_override_cfg(BPMPW),
mc_make_sid_override_cfg(HDAW),
mc_make_sid_override_cfg(NVDISPLAYR1),
mc_make_sid_override_cfg(APEDMAR),
mc_make_sid_override_cfg(AFIR),
mc_make_sid_override_cfg(AXISR),
mc_make_sid_override_cfg(VICSRD1),
mc_make_sid_override_cfg(TSECSRD),
mc_make_sid_override_cfg(BPMPDMAW),
mc_make_sid_override_cfg(MPCOREW),
mc_make_sid_override_cfg(XUSB_HOSTR),
mc_make_sid_override_cfg(GPUSWR),
mc_make_sid_override_cfg(XUSB_DEVR),
mc_make_sid_override_cfg(UFSHCW),
mc_make_sid_override_cfg(XUSB_HOSTW),
mc_make_sid_override_cfg(SDMMCWAB),
mc_make_sid_override_cfg(SATAW),
mc_make_sid_override_cfg(SCEDMAR),
mc_make_sid_override_cfg(HOST1XDMAR),
mc_make_sid_override_cfg(SDMMCWA),
mc_make_sid_override_cfg(APEDMAW),
mc_make_sid_override_cfg(SESWR),
mc_make_sid_override_cfg(AXISW),
mc_make_sid_override_cfg(AONDMAW),
mc_make_sid_override_cfg(TSECSWRB),
mc_make_sid_override_cfg(MPCORER),
mc_make_sid_override_cfg(ISPWB),
mc_make_sid_override_cfg(AONR),
mc_make_sid_override_cfg(BPMPDMAR),
mc_make_sid_override_cfg(HDAR),
mc_make_sid_override_cfg(SDMMCRA),
mc_make_sid_override_cfg(ETRW),
mc_make_sid_override_cfg(GPUSWR2),
mc_make_sid_override_cfg(EQOSR),
mc_make_sid_override_cfg(TSECSWR),
mc_make_sid_override_cfg(ETRR),
mc_make_sid_override_cfg(NVDECSRD),
mc_make_sid_override_cfg(TSECSRDB),
mc_make_sid_override_cfg(SDMMCRAA),
mc_make_sid_override_cfg(NVDECSRD1),
mc_make_sid_override_cfg(SDMMCR),
mc_make_sid_override_cfg(NVJPGSRD),
mc_make_sid_override_cfg(SCEDMAW),
mc_make_sid_override_cfg(SDMMCWAA),
mc_make_sid_override_cfg(APEW),
mc_make_sid_override_cfg(AONDMAR),
mc_make_sid_override_cfg(PTCR),
mc_make_sid_override_cfg(SCER),
mc_make_sid_override_cfg(ISPRA),
mc_make_sid_override_cfg(ISPWA),
mc_make_sid_override_cfg(VICSWR),
mc_make_sid_override_cfg(SESRD),
mc_make_sid_override_cfg(SDMMCW),
mc_make_sid_override_cfg(SDMMCRAB),
mc_make_sid_override_cfg(EQOSW),
mc_make_sid_override_cfg(GPUSRD2),
mc_make_sid_override_cfg(SCEW),
mc_make_sid_override_cfg(GPUSRD),
mc_make_sid_override_cfg(NVDECSWR),
mc_make_sid_override_cfg(XUSB_DEVW),
mc_make_sid_override_cfg(SATAR),
mc_make_sid_override_cfg(NVDISPLAYR),
mc_make_sid_override_cfg(VIW),
mc_make_sid_override_cfg(UFSHCR),
mc_make_sid_override_cfg(NVENCSWR),
mc_make_sid_override_cfg(AFIW),
smmu_make_gnsr0_nsec_cfg(CR0),
smmu_make_gnsr0_sec_cfg(IDR0),
smmu_make_gnsr0_sec_cfg(IDR1),
smmu_make_gnsr0_sec_cfg(IDR2),
smmu_make_gnsr0_nsec_cfg(GFSR),
smmu_make_gnsr0_nsec_cfg(GFSYNR0),
smmu_make_gnsr0_nsec_cfg(GFSYNR1),
smmu_make_gnsr0_nsec_cfg(TLBGSTATUS),
smmu_make_gnsr0_nsec_cfg(PIDR2),
smmu_make_smrg_group(0),
smmu_make_smrg_group(1),
smmu_make_smrg_group(2),
smmu_make_smrg_group(3),
smmu_make_smrg_group(4),
smmu_make_smrg_group(5),
smmu_make_smrg_group(6),
smmu_make_smrg_group(7),
smmu_make_smrg_group(8),
smmu_make_smrg_group(9),
smmu_make_smrg_group(10),
smmu_make_smrg_group(11),
smmu_make_smrg_group(12),
smmu_make_smrg_group(13),
smmu_make_smrg_group(14),
smmu_make_smrg_group(15),
smmu_make_smrg_group(16),
smmu_make_smrg_group(17),
smmu_make_smrg_group(18),
smmu_make_smrg_group(19),
smmu_make_smrg_group(20),
smmu_make_smrg_group(21),
smmu_make_smrg_group(22),
smmu_make_smrg_group(23),
smmu_make_smrg_group(24),
smmu_make_smrg_group(25),
smmu_make_smrg_group(26),
smmu_make_smrg_group(27),
smmu_make_smrg_group(28),
smmu_make_smrg_group(29),
smmu_make_smrg_group(30),
smmu_make_smrg_group(31),
smmu_make_smrg_group(32),
smmu_make_smrg_group(33),
smmu_make_smrg_group(34),
smmu_make_smrg_group(35),
smmu_make_smrg_group(36),
smmu_make_smrg_group(37),
smmu_make_smrg_group(38),
smmu_make_smrg_group(39),
smmu_make_smrg_group(40),
smmu_make_smrg_group(41),
smmu_make_smrg_group(42),
smmu_make_smrg_group(43),
smmu_make_smrg_group(44),
smmu_make_smrg_group(45),
smmu_make_smrg_group(46),
smmu_make_smrg_group(47),
smmu_make_smrg_group(48),
smmu_make_smrg_group(49),
smmu_make_smrg_group(50),
smmu_make_smrg_group(51),
smmu_make_smrg_group(52),
smmu_make_smrg_group(53),
smmu_make_smrg_group(54),
smmu_make_smrg_group(55),
smmu_make_smrg_group(56),
smmu_make_smrg_group(57),
smmu_make_smrg_group(58),
smmu_make_smrg_group(59),
smmu_make_smrg_group(60),
smmu_make_smrg_group(61),
smmu_make_smrg_group(62),
smmu_make_smrg_group(63),
smmu_make_cb_group(0),
smmu_make_cb_group(1),
smmu_make_cb_group(2),
smmu_make_cb_group(3),
smmu_make_cb_group(4),
smmu_make_cb_group(5),
smmu_make_cb_group(6),
smmu_make_cb_group(7),
smmu_make_cb_group(8),
smmu_make_cb_group(9),
smmu_make_cb_group(10),
smmu_make_cb_group(11),
smmu_make_cb_group(12),
smmu_make_cb_group(13),
smmu_make_cb_group(14),
smmu_make_cb_group(15),
smmu_make_cb_group(16),
smmu_make_cb_group(17),
smmu_make_cb_group(18),
smmu_make_cb_group(19),
smmu_make_cb_group(20),
smmu_make_cb_group(21),
smmu_make_cb_group(22),
smmu_make_cb_group(23),
smmu_make_cb_group(24),
smmu_make_cb_group(25),
smmu_make_cb_group(26),
smmu_make_cb_group(27),
smmu_make_cb_group(28),
smmu_make_cb_group(29),
smmu_make_cb_group(30),
smmu_make_cb_group(31),
smmu_make_cb_group(32),
smmu_make_cb_group(33),
smmu_make_cb_group(34),
smmu_make_cb_group(35),
smmu_make_cb_group(36),
smmu_make_cb_group(37),
smmu_make_cb_group(38),
smmu_make_cb_group(39),
smmu_make_cb_group(40),
smmu_make_cb_group(41),
smmu_make_cb_group(42),
smmu_make_cb_group(43),
smmu_make_cb_group(44),
smmu_make_cb_group(45),
smmu_make_cb_group(46),
smmu_make_cb_group(47),
smmu_make_cb_group(48),
smmu_make_cb_group(49),
smmu_make_cb_group(50),
smmu_make_cb_group(51),
smmu_make_cb_group(52),
smmu_make_cb_group(53),
smmu_make_cb_group(54),
smmu_make_cb_group(55),
smmu_make_cb_group(56),
smmu_make_cb_group(57),
smmu_make_cb_group(58),
smmu_make_cb_group(59),
smmu_make_cb_group(60),
smmu_make_cb_group(61),
smmu_make_cb_group(62),
smmu_make_cb_group(63),
smmu_bypass_cfg, /* TBU settings */
_END_OF_TABLE_,
};
#if defined(TEGRA_SMMU2_BASE)
if (smmu_id == TEGRA_SMMU2)
mmio_write_32(TEGRA_SMMU2_BASE + off, val);
#endif
}
/*
* Save SMMU settings before "System Suspend" to TZDRAM
......@@ -432,6 +88,7 @@ static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = {
void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
{
uint32_t i;
smmu_regs_t *smmu_ctx_regs;
#if DEBUG
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t tzdram_base = params_from_bl2->tzdram_base;
......@@ -439,7 +96,7 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
uint32_t reg_id1, pgshift, cb_size;
/* sanity check SMMU settings c*/
reg_id1 = mmio_read_32((TEGRA_SMMU_BASE + SMMU_GNSR0_IDR1));
reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1));
pgshift = (reg_id1 & ID1_PAGESIZE) ? 16 : 12;
cb_size = (2 << pgshift) * \
(1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1));
......@@ -449,11 +106,12 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
/* index of _END_OF_TABLE_ */
smmu_ctx_regs[0].val = ARRAY_SIZE(smmu_ctx_regs) - 1;
/* get SMMU context table */
smmu_ctx_regs = plat_get_smmu_ctx();
assert(smmu_ctx_regs);
/* save SMMU register values */
for (i = 1; i < ARRAY_SIZE(smmu_ctx_regs) - 1; i++)
for (i = 1; i < smmu_ctx_regs[0].val; i++)
smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
/* Save SMMU config settings */
......@@ -475,34 +133,39 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
*/
void tegra_smmu_init(void)
{
uint32_t val, i, ctx_base;
/* Program the SMMU pagesize and reset CACHE_LOCK bit */
val = tegra_smmu_read_32(SMMU_GSR0_SECURE_ACR);
val |= SMMU_GSR0_PGSIZE_64K;
val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(SMMU_GSR0_SECURE_ACR, val);
/* reset CACHE LOCK bit for NS Aux. Config. Register */
val = tegra_smmu_read_32(SMMU_GNSR_ACR);
val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(SMMU_GNSR_ACR, val);
/* disable TCU prefetch for all contexts */
ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS) + SMMU_CBn_ACTLR;
for (i = 0; i < SMMU_CONTEXT_BANK_MAX_IDX; i++) {
val = tegra_smmu_read_32(ctx_base + (SMMU_GSR0_PGSIZE_64K * i));
val &= ~SMMU_CBn_ACTLR_CPRE_BIT;
tegra_smmu_write_32(ctx_base + (SMMU_GSR0_PGSIZE_64K * i), val);
uint32_t val, cb_idx, smmu_id, ctx_base;
for (smmu_id = 0; smmu_id < NUM_SMMU_DEVICES; smmu_id++) {
/* Program the SMMU pagesize and reset CACHE_LOCK bit */
val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
val |= SMMU_GSR0_PGSIZE_64K;
val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
/* reset CACHE LOCK bit for NS Aux. Config. Register */
val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
/* disable TCU prefetch for all contexts */
ctx_base = (SMMU_GSR0_PGSIZE_64K * SMMU_NUM_CONTEXTS)
+ SMMU_CBn_ACTLR;
for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
val = tegra_smmu_read_32(smmu_id,
ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
val &= ~SMMU_CBn_ACTLR_CPRE_BIT;
tegra_smmu_write_32(smmu_id, ctx_base +
(SMMU_GSR0_PGSIZE_64K * cb_idx), val);
}
/* set CACHE LOCK bit for NS Aux. Config. Register */
val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
/* set CACHE LOCK bit for S Aux. Config. Register */
val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
}
/* set CACHE LOCK bit for NS Aux. Config. Register */
val = tegra_smmu_read_32(SMMU_GNSR_ACR);
val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(SMMU_GNSR_ACR, val);
/* set CACHE LOCK bit for S Aux. Config. Register */
val = tegra_smmu_read_32(SMMU_GSR0_SECURE_ACR);
val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
tegra_smmu_write_32(SMMU_GSR0_SECURE_ACR, val);
}
plat/nvidia/tegra/common/tegra_bl31_setup.c
View file @ 3d21c945
......@@ -202,9 +202,6 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
*/
console_init(tegra_console_base, TEGRA_BOOT_UART_CLK_IN_HZ,
TEGRA_CONSOLE_BAUDRATE);
/* Initialise crash console */
plat_crash_console_init();
}
/*
......@@ -299,7 +296,16 @@ void bl31_platform_setup(void)
******************************************************************************/
void bl31_plat_runtime_setup(void)
{
; /* do nothing */
/*
* During boot, USB3 and flash media (SDMMC/SATA) devices need
* access to IRAM. Because these clients connect to the MC and
* do not have a direct path to the IRAM, the MC implements AHB
* redirection during boot to allow path to IRAM. In this mode
* accesses to a programmed memory address aperture are directed
* to the AHB bus, allowing access to the IRAM. This mode must be
* disabled before we jump to the non-secure world.
*/
tegra_memctrl_disable_ahb_redirection();
}
/*******************************************************************************
......
plat/nvidia/tegra/common/tegra_platform.c
View file @ 3d21c945
......@@ -69,6 +69,7 @@ typedef enum tegra_platform {
typedef enum tegra_chipid {
TEGRA_CHIPID_TEGRA13 = 0x13,
TEGRA_CHIPID_TEGRA21 = 0x21,
TEGRA_CHIPID_TEGRA18 = 0x18,
} tegra_chipid_t;
/*
......@@ -109,6 +110,13 @@ uint8_t tegra_chipid_is_t210(void)
return (chip_id == TEGRA_CHIPID_TEGRA21);
}
uint8_t tegra_chipid_is_t186(void)
{
uint32_t chip_id = (tegra_get_chipid() >> CHIP_ID_SHIFT) & CHIP_ID_MASK;
return (chip_id == TEGRA_CHIPID_TEGRA18);
}
/*
* Read the chip ID value and derive the platform
*/
......
plat/nvidia/tegra/common/tegra_pm.c
View file @ 3d21c945
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -48,6 +48,14 @@ extern uint64_t tegra_bl31_phys_base;
extern uint64_t tegra_sec_entry_point;
extern uint64_t tegra_console_base;
/*
* tegra_fake_system_suspend acts as a boolean var controlling whether
* we are going to take fake system suspend code or normal system suspend code
* path. This variable is set inside the sip call handlers,when the kernel
* requests a SIP call to set the suspend debug flags.
*/
uint8_t tegra_fake_system_suspend;
/*
* The following platform setup functions are weakly defined. They
* provide typical implementations that will be overridden by a SoC.
......@@ -182,14 +190,31 @@ void tegra_pwr_domain_suspend(const psci_power_state_t *target_state)
__dead2 void tegra_pwr_domain_power_down_wfi(const psci_power_state_t
*target_state)
{
uint8_t pwr_state = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
uint64_t rmr_el3 = 0;
/* call the chip's power down handler */
tegra_soc_pwr_domain_power_down_wfi(target_state);
/* enter power down state */
wfi();
/*
* If we are in fake system suspend mode, ensure we start doing
* procedures that help in looping back towards system suspend exit
* instead of calling WFI by requesting a warm reset.
* Else, just call WFI to enter low power state.
*/
if ((tegra_fake_system_suspend != 0U) &&
(pwr_state == (uint8_t)PSTATE_ID_SOC_POWERDN)) {
/* warm reboot */
rmr_el3 = read_rmr_el3();
write_rmr_el3(rmr_el3 | RMR_WARM_RESET_CPU);
} else {
/* enter power down state */
wfi();
}
/* we can never reach here */
ERROR("%s: operation not handled.\n", __func__);
panic();
}
......
plat/nvidia/tegra/common/tegra_sip_calls.c
View file @ 3d21c945
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -37,6 +37,7 @@
#include <memctrl.h>
#include <runtime_svc.h>
#include <tegra_private.h>
#include <tegra_platform.h>
/*******************************************************************************
* Common Tegra SiP SMCs
......@@ -44,6 +45,13 @@
#define TEGRA_SIP_NEW_VIDEOMEM_REGION 0x82000003
#define TEGRA_SIP_FIQ_NS_ENTRYPOINT 0x82000005
#define TEGRA_SIP_FIQ_NS_GET_CONTEXT 0x82000006
#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2000007
/*******************************************************************************
* Fake system suspend mode control var
******************************************************************************/
extern uint8_t tegra_fake_system_suspend;
/*******************************************************************************
* SoC specific SiP handler
......@@ -144,6 +152,26 @@ uint64_t tegra_sip_handler(uint32_t smc_fid,
SMC_RET0(handle);
break;
case TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND:
/*
* System suspend fake mode is set if we are on VDK and we make
* a debug SIP call. This mode ensures that we excercise debug
* path instead of the regular code path to suit the pre-silicon
* platform needs. These include replacing the call to WFI by
* a warm reset request.
*/
if (tegra_platform_is_emulation() != 0U) {
tegra_fake_system_suspend = 1;
SMC_RET1(handle, 0);
}
/*
* We return to the external world as if this SIP is not
* implemented in case, we are not running on VDK.
*/
break;
default:
ERROR("%s: unhandled SMC (0x%x)\n", __func__, smc_fid);
break;
......
plat/nvidia/tegra/include/drivers/flowctrl.h
View file @ 3d21c945
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -34,34 +34,34 @@
#include <mmio.h>
#include <tegra_def.h>
#define FLOWCTRL_HALT_CPU0_EVENTS 0x0
#define FLOWCTRL_WAITEVENT (2 << 29)
#define FLOWCTRL_WAIT_FOR_INTERRUPT (4 << 29)
#define FLOWCTRL_JTAG_RESUME (1 << 28)
#define FLOWCTRL_HALT_SCLK (1 << 27)
#define FLOWCTRL_HALT_LIC_IRQ (1 << 11)
#define FLOWCTRL_HALT_LIC_FIQ (1 << 10)
#define FLOWCTRL_HALT_GIC_IRQ (1 << 9)
#define FLOWCTRL_HALT_GIC_FIQ (1 << 8)
#define FLOWCTRL_HALT_BPMP_EVENTS 0x4
#define FLOWCTRL_CPU0_CSR 0x8
#define FLOW_CTRL_CSR_PWR_OFF_STS (1 << 16)
#define FLOWCTRL_CSR_INTR_FLAG (1 << 15)
#define FLOWCTRL_CSR_EVENT_FLAG (1 << 14)
#define FLOWCTRL_CSR_IMMEDIATE_WAKE (1 << 3)
#define FLOWCTRL_CSR_ENABLE (1 << 0)
#define FLOWCTRL_HALT_CPU1_EVENTS 0x14
#define FLOWCTRL_CPU1_CSR 0x18
#define FLOWCTRL_CC4_CORE0_CTRL 0x6c
#define FLOWCTRL_WAIT_WFI_BITMAP 0x100
#define FLOWCTRL_L2_FLUSH_CONTROL 0x94
#define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98
#define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1 << 2)
#define FLOWCTRL_HALT_CPU0_EVENTS 0x0U
#define FLOWCTRL_WAITEVENT (2U << 29)
#define FLOWCTRL_WAIT_FOR_INTERRUPT (4U << 29)
#define FLOWCTRL_JTAG_RESUME (1U << 28)
#define FLOWCTRL_HALT_SCLK (1U << 27)
#define FLOWCTRL_HALT_LIC_IRQ (1U << 11)
#define FLOWCTRL_HALT_LIC_FIQ (1U << 10)
#define FLOWCTRL_HALT_GIC_IRQ (1U << 9)
#define FLOWCTRL_HALT_GIC_FIQ (1U << 8)
#define FLOWCTRL_HALT_BPMP_EVENTS 0x4U
#define FLOWCTRL_CPU0_CSR 0x8U
#define FLOW_CTRL_CSR_PWR_OFF_STS (1U << 16)
#define FLOWCTRL_CSR_INTR_FLAG (1U << 15)
#define FLOWCTRL_CSR_EVENT_FLAG (1U << 14)
#define FLOWCTRL_CSR_IMMEDIATE_WAKE (1U << 3)
#define FLOWCTRL_CSR_ENABLE (1U << 0)
#define FLOWCTRL_HALT_CPU1_EVENTS 0x14U
#define FLOWCTRL_CPU1_CSR 0x18U
#define FLOWCTRL_CC4_CORE0_CTRL 0x6cU
#define FLOWCTRL_WAIT_WFI_BITMAP 0x100U
#define FLOWCTRL_L2_FLUSH_CONTROL 0x94U
#define FLOWCTRL_BPMP_CLUSTER_CONTROL 0x98U
#define FLOWCTRL_BPMP_CLUSTER_PWRON_LOCK (1U << 2)
#define FLOWCTRL_ENABLE_EXT 12
#define FLOWCTRL_ENABLE_EXT_MASK 3
#define FLOWCTRL_PG_CPU_NONCPU 0x1
#define FLOWCTRL_TURNOFF_CPURAIL 0x2
#define FLOWCTRL_ENABLE_EXT 12U
#define FLOWCTRL_ENABLE_EXT_MASK 3U
#define FLOWCTRL_PG_CPU_NONCPU 0x1U
#define FLOWCTRL_TURNOFF_CPURAIL 0x2U
static inline uint32_t tegra_fc_read_32(uint32_t off)
{
......
plat/nvidia/tegra/include/drivers/mce.h
View file @ 3d21c945
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -38,35 +38,35 @@
* MCE commands
******************************************************************************/
typedef enum mce_cmd {
MCE_CMD_ENTER_CSTATE = 0,
MCE_CMD_UPDATE_CSTATE_INFO = 1,
MCE_CMD_UPDATE_CROSSOVER_TIME = 2,
MCE_CMD_READ_CSTATE_STATS = 3,
MCE_CMD_WRITE_CSTATE_STATS = 4,
MCE_CMD_IS_SC7_ALLOWED = 5,
MCE_CMD_ONLINE_CORE = 6,
MCE_CMD_CC3_CTRL = 7,
MCE_CMD_ECHO_DATA = 8,
MCE_CMD_READ_VERSIONS = 9,
MCE_CMD_ENUM_FEATURES = 10,
MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11,
MCE_CMD_ENUM_READ_MCA = 12,
MCE_CMD_ENUM_WRITE_MCA = 13,
MCE_CMD_ROC_FLUSH_CACHE = 14,
MCE_CMD_ROC_CLEAN_CACHE = 15,
MCE_CMD_ENABLE_LATIC = 16,
MCE_CMD_UNCORE_PERFMON_REQ = 17,
MCE_CMD_MISC_CCPLEX = 18,
MCE_CMD_IS_CCX_ALLOWED = 0xFE,
MCE_CMD_MAX = 0xFF,
MCE_CMD_ENTER_CSTATE = 0U,
MCE_CMD_UPDATE_CSTATE_INFO = 1U,
MCE_CMD_UPDATE_CROSSOVER_TIME = 2U,
MCE_CMD_READ_CSTATE_STATS = 3U,
MCE_CMD_WRITE_CSTATE_STATS = 4U,
MCE_CMD_IS_SC7_ALLOWED = 5U,
MCE_CMD_ONLINE_CORE = 6U,
MCE_CMD_CC3_CTRL = 7U,
MCE_CMD_ECHO_DATA = 8U,
MCE_CMD_READ_VERSIONS = 9U,
MCE_CMD_ENUM_FEATURES = 10U,
MCE_CMD_ROC_FLUSH_CACHE_TRBITS = 11U,
MCE_CMD_ENUM_READ_MCA = 12U,
MCE_CMD_ENUM_WRITE_MCA = 13U,
MCE_CMD_ROC_FLUSH_CACHE = 14U,
MCE_CMD_ROC_CLEAN_CACHE = 15U,
MCE_CMD_ENABLE_LATIC = 16U,
MCE_CMD_UNCORE_PERFMON_REQ = 17U,
MCE_CMD_MISC_CCPLEX = 18U,
MCE_CMD_IS_CCX_ALLOWED = 0xFEU,
MCE_CMD_MAX = 0xFFU,
} mce_cmd_t;
#define MCE_CMD_MASK 0xFF
#define MCE_CMD_MASK 0xFFU
/*******************************************************************************
* Timeout value used to powerdown a core
******************************************************************************/
#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFF
#define MCE_CORE_SLEEP_TIME_INFINITE 0xFFFFFFFFU
/*******************************************************************************
* Struct to prepare UPDATE_CSTATE_INFO request
......
plat/nvidia/tegra/include/drivers/memctrl.h
View file @ 3d21c945
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -36,5 +36,6 @@ void tegra_memctrl_restore_settings(void);
void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes);
void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes);
void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes);
void tegra_memctrl_disable_ahb_redirection(void);
#endif /* __MEMCTRL_H__ */
plat/nvidia/tegra/include/drivers/memctrl_v1.h
View file @ 3d21c945
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -35,31 +35,38 @@
#include <tegra_def.h>
/* SMMU registers */
#define MC_SMMU_CONFIG_0 0x10
#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0
#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1
#define MC_SMMU_TLB_CONFIG_0 0x14
#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010
#define MC_SMMU_PTC_CONFIG_0 0x18
#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003f
#define MC_SMMU_TLB_FLUSH_0 0x30
#define TLB_FLUSH_VA_MATCH_ALL 0
#define TLB_FLUSH_ASID_MATCH_DISABLE 0
#define TLB_FLUSH_ASID_MATCH_SHIFT 31
#define MC_SMMU_CONFIG_0 0x10U
#define MC_SMMU_CONFIG_0_SMMU_ENABLE_DISABLE 0U
#define MC_SMMU_CONFIG_0_SMMU_ENABLE_ENABLE 1U
#define MC_SMMU_TLB_CONFIG_0 0x14U
#define MC_SMMU_TLB_CONFIG_0_RESET_VAL 0x20000010U
#define MC_SMMU_PTC_CONFIG_0 0x18U
#define MC_SMMU_PTC_CONFIG_0_RESET_VAL 0x2000003fU
#define MC_SMMU_TLB_FLUSH_0 0x30U
#define TLB_FLUSH_VA_MATCH_ALL 0U
#define TLB_FLUSH_ASID_MATCH_DISABLE 0U
#define TLB_FLUSH_ASID_MATCH_SHIFT 31U
#define MC_SMMU_TLB_FLUSH_ALL \
(TLB_FLUSH_VA_MATCH_ALL | \
(TLB_FLUSH_ASID_MATCH_DISABLE << TLB_FLUSH_ASID_MATCH_SHIFT))
#define MC_SMMU_PTC_FLUSH_0 0x34
#define MC_SMMU_PTC_FLUSH_ALL 0
#define MC_SMMU_ASID_SECURITY_0 0x38
#define MC_SMMU_ASID_SECURITY 0
#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228
#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22c
#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230
#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234
#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98
#define MC_SMMU_PTC_FLUSH_0 0x34U
#define MC_SMMU_PTC_FLUSH_ALL 0U
#define MC_SMMU_ASID_SECURITY_0 0x38U
#define MC_SMMU_ASID_SECURITY 0U
#define MC_SMMU_TRANSLATION_ENABLE_0_0 0x228U
#define MC_SMMU_TRANSLATION_ENABLE_1_0 0x22cU
#define MC_SMMU_TRANSLATION_ENABLE_2_0 0x230U
#define MC_SMMU_TRANSLATION_ENABLE_3_0 0x234U
#define MC_SMMU_TRANSLATION_ENABLE_4_0 0xb98U
#define MC_SMMU_TRANSLATION_ENABLE (~0)
/* MC IRAM aperture registers */
#define MC_IRAM_BASE_LO 0x65CU
#define MC_IRAM_TOP_LO 0x660U
#define MC_IRAM_BASE_TOP_HI 0x980U
#define MC_IRAM_REG_CTRL 0x964U
#define MC_DISABLE_IRAM_CFG_WRITES 1U
static inline uint32_t tegra_mc_read_32(uint32_t off)
{
return mmio_read_32(TEGRA_MC_BASE + off);
......
plat/nvidia/tegra/include/drivers/pmc.h
View file @ 3d21c945
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -34,19 +34,19 @@
#include <mmio.h>
#include <tegra_def.h>
#define PMC_CONFIG 0x0
#define PMC_PWRGATE_STATUS 0x38
#define PMC_PWRGATE_TOGGLE 0x30
#define PMC_TOGGLE_START 0x100
#define PMC_SCRATCH39 0x138
#define PMC_SECURE_DISABLE2 0x2c4
#define PMC_SECURE_DISABLE2_WRITE22_ON (1 << 28)
#define PMC_SECURE_SCRATCH22 0x338
#define PMC_SECURE_DISABLE3 0x2d8
#define PMC_SECURE_DISABLE3_WRITE34_ON (1 << 20)
#define PMC_SECURE_DISABLE3_WRITE35_ON (1 << 22)
#define PMC_SECURE_SCRATCH34 0x368
#define PMC_SECURE_SCRATCH35 0x36c
#define PMC_CONFIG 0x0U
#define PMC_PWRGATE_STATUS 0x38U
#define PMC_PWRGATE_TOGGLE 0x30U
#define PMC_TOGGLE_START 0x100U
#define PMC_SCRATCH39 0x138U
#define PMC_SECURE_DISABLE2 0x2c4U
#define PMC_SECURE_DISABLE2_WRITE22_ON (1U << 28)
#define PMC_SECURE_SCRATCH22 0x338U
#define PMC_SECURE_DISABLE3 0x2d8U
#define PMC_SECURE_DISABLE3_WRITE34_ON (1U << 20)
#define PMC_SECURE_DISABLE3_WRITE35_ON (1U << 22)
#define PMC_SECURE_SCRATCH34 0x368U
#define PMC_SECURE_SCRATCH35 0x36cU
static inline uint32_t tegra_pmc_read_32(uint32_t off)
{
......
plat/nvidia/tegra/include/drivers/smmu.h
View file @ 3d21c945
This diff is collapsed.
plat/nvidia/tegra/include/t186/tegra_def.h
View file @ 3d21c945
......@@ -272,7 +272,7 @@
/*******************************************************************************
* Tegra SMMU Controller constants
******************************************************************************/
#define TEGRA_SMMU_BASE 0x12000000
#define TEGRA_SMMU0_BASE 0x12000000
/*******************************************************************************
* Tegra TZRAM constants
......
plat/nvidia/tegra/include/tegra_platform.h
View file @ 3d21c945
......@@ -42,8 +42,10 @@ uint32_t tegra_get_chipid_minor(void);
/*
* Tegra chip identifiers
*/
uint8_t tegra_is_t132(void);
uint8_t tegra_is_t210(void);
uint8_t tegra_chipid_is_t132(void);
uint8_t tegra_chipid_is_t210(void);
uint8_t tegra_chipid_is_t186(void);
/*
* Tegra platform identifiers
......
plat/nvidia/tegra/include/tegra_private.h
View file @ 3d21c945
/*
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -39,8 +39,8 @@
/*******************************************************************************
* Tegra DRAM memory base address
******************************************************************************/
#define TEGRA_DRAM_BASE 0x80000000
#define TEGRA_DRAM_END 0x27FFFFFFF
#define TEGRA_DRAM_BASE 0x80000000ULL
#define TEGRA_DRAM_END 0x27FFFFFFFULL
/*******************************************************************************
* Struct for parameters received from BL2
......@@ -103,6 +103,8 @@ void tegra_security_setup(void);
void tegra_security_setup_videomem(uintptr_t base, uint64_t size);
/* Declarations for tegra_pm.c */
extern uint8_t tegra_fake_system_suspend;
void tegra_pm_system_suspend_entry(void);
void tegra_pm_system_suspend_exit(void);
int tegra_system_suspended(void);
......
plat/nvidia/tegra/soc/t186/drivers/include/mce_private.h
View file @ 3d21c945
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
......@@ -38,46 +38,46 @@
* Macros to prepare CSTATE info request
******************************************************************************/
/* Description of the parameters for UPDATE_CSTATE_INFO request */
#define CLUSTER_CSTATE_MASK 0x7
#define CLUSTER_CSTATE_SHIFT 0
#define CLUSTER_CSTATE_UPDATE_BIT (1 << 7)
#define CCPLEX_CSTATE_MASK 0x3
#define CCPLEX_CSTATE_SHIFT 8
#define CCPLEX_CSTATE_UPDATE_BIT (1 << 15)
#define SYSTEM_CSTATE_MASK 0xF
#define SYSTEM_CSTATE_SHIFT 16
#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22
#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1 << 22)
#define SYSTEM_CSTATE_UPDATE_BIT (1 << 23)
#define CSTATE_WAKE_MASK_UPDATE_BIT (1 << 31)
#define CSTATE_WAKE_MASK_SHIFT 32
#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFF
#define CLUSTER_CSTATE_MASK 0x7ULL
#define CLUSTER_CSTATE_SHIFT 0U
#define CLUSTER_CSTATE_UPDATE_BIT (1ULL << 7)
#define CCPLEX_CSTATE_MASK 0x3ULL
#define CCPLEX_CSTATE_SHIFT 8ULL
#define CCPLEX_CSTATE_UPDATE_BIT (1ULL << 15)
#define SYSTEM_CSTATE_MASK 0xFULL
#define SYSTEM_CSTATE_SHIFT 16ULL
#define SYSTEM_CSTATE_FORCE_UPDATE_SHIFT 22ULL
#define SYSTEM_CSTATE_FORCE_UPDATE_BIT (1ULL << 22)
#define SYSTEM_CSTATE_UPDATE_BIT (1ULL << 23)
#define CSTATE_WAKE_MASK_UPDATE_BIT (1ULL << 31)
#define CSTATE_WAKE_MASK_SHIFT 32ULL
#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU
/*******************************************************************************
* Auto-CC3 control macros
******************************************************************************/
#define MCE_AUTO_CC3_FREQ_MASK 0x1FF
#define MCE_AUTO_CC3_FREQ_SHIFT 0
#define MCE_AUTO_CC3_VTG_MASK 0x7F
#define MCE_AUTO_CC3_VTG_SHIFT 16
#define MCE_AUTO_CC3_ENABLE_BIT (1 << 31)
#define MCE_AUTO_CC3_FREQ_MASK 0x1FFU
#define MCE_AUTO_CC3_FREQ_SHIFT 0U
#define MCE_AUTO_CC3_VTG_MASK 0x7FU
#define MCE_AUTO_CC3_VTG_SHIFT 16U
#define MCE_AUTO_CC3_ENABLE_BIT (1U << 31)
/*******************************************************************************
* Macros for the 'IS_SC7_ALLOWED' command
******************************************************************************/
#define MCE_SC7_ALLOWED_MASK 0x7
#define MCE_SC7_WAKE_TIME_SHIFT 32
#define MCE_SC7_ALLOWED_MASK 0x7U
#define MCE_SC7_WAKE_TIME_SHIFT 32U
/*******************************************************************************
* Macros for 'read/write ctats' commands
******************************************************************************/
#define MCE_CSTATE_STATS_TYPE_SHIFT 32
#define MCE_CSTATE_WRITE_DATA_LO_MASK 0xF
#define MCE_CSTATE_STATS_TYPE_SHIFT 32ULL
#define MCE_CSTATE_WRITE_DATA_LO_MASK 0xFU
/*******************************************************************************
* Macros for 'update crossover threshold' command
******************************************************************************/
#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32
#define MCE_CROSSOVER_THRESHOLD_TIME_SHIFT 32U
/*******************************************************************************
* MCA command struct
......@@ -100,9 +100,10 @@ typedef union mca_cmd {
******************************************************************************/
typedef union mca_arg {
struct err {
uint64_t error:8;
uint64_t unused:48;
uint64_t finish:8;
uint32_t error:8;
uint32_t unused:24;
uint32_t unused2:24;
uint32_t finish:8;
} err;
struct arg {
uint32_t low;
......@@ -119,45 +120,45 @@ typedef union uncore_perfmon_req {
/*
* Commands: 0 = READ, 1 = WRITE
*/
uint64_t cmd:8;
uint32_t cmd:8;
/*
* The unit group: L2=0, L3=1, ROC=2, MC=3, IOB=4
*/
uint64_t grp:4;
uint32_t grp:4;
/*
* Unit selector: Selects the unit instance, with 0 = Unit
* = (number of units in group) - 1.
*/
uint64_t unit:4;
uint32_t unit:4;
/*
* Selects the uncore perfmon register to access
*/
uint64_t reg:8;
uint32_t reg:8;
/*
* Counter number. Selects which counter to use for
* registers NV_PMEVCNTR and NV_PMEVTYPER.
*/
uint64_t counter:8;
uint32_t counter:8;
} perfmon_command;
struct perfmon_status {
/*
* Resulting command status
*/
uint64_t val:8;
uint64_t unused:24;
uint32_t val:8;
uint32_t unused:24;
} perfmon_status;
uint64_t data;
} uncore_perfmon_req_t;
#define UNCORE_PERFMON_CMD_READ 0
#define UNCORE_PERFMON_CMD_WRITE 1
#define UNCORE_PERFMON_CMD_READ 0U
#define UNCORE_PERFMON_CMD_WRITE 1U
#define UNCORE_PERFMON_CMD_MASK 0xFF
#define UNCORE_PERFMON_UNIT_GRP_MASK 0xF
#define UNCORE_PERFMON_SELECTOR_MASK 0xF
#define UNCORE_PERFMON_REG_MASK 0xFF
#define UNCORE_PERFMON_CTR_MASK 0xFF
#define UNCORE_PERFMON_RESP_STATUS_MASK 0xFF
#define UNCORE_PERFMON_CMD_MASK 0xFFU
#define UNCORE_PERFMON_UNIT_GRP_MASK 0xFU
#define UNCORE_PERFMON_SELECTOR_MASK 0xFU
#define UNCORE_PERFMON_REG_MASK 0xFFU
#define UNCORE_PERFMON_CTR_MASK 0xFFU
#define UNCORE_PERFMON_RESP_STATUS_MASK 0xFFU
/*******************************************************************************
* Structure populated by arch specific code to export routines which perform
......
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