Merge changes I93ecff4d,I30dd9a95,I8207eea9,Id4197b07,Ib810125b, ... into integration

* changes:
  mediatek: mt8183: add MTK MCDI driver
  mediatek: mt8183: add MTK SSPM driver
  mediatek: mt8183: add MTK SPM driver
  mediatek: mt8183: add MTK uart driver for controlling clock gate
  mediatek: mt8183: configure MCUSYS DCM
  mediatek: mt8173: refactor RTC and PMIC drivers

plat/mediatek/mt8183/drivers/uart/uart.h

+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __UART_H__
+#define __UART_H__
+
+#include <platform_def.h>
+
+/* UART HW information */
+#define HW_SUPPORT_UART_PORTS	2
+#define DRV_SUPPORT_UART_PORTS	2
+
+/* console UART clock cg */
+#define UART_CLOCK_GATE_SET		(INFRACFG_AO_BASE + 0x80)
+#define UART_CLOCK_GATE_CLR		(INFRACFG_AO_BASE + 0x84)
+#define UART_CLOCK_GATE_STA		(INFRACFG_AO_BASE + 0x90)
+#define UART0_CLOCK_GATE_BIT		(1U<<22)
+#define UART1_CLOCK_GATE_BIT		(1U<<23)
+
+/* UART registers */
+#define UART_RBR(_baseaddr)			(_baseaddr + 0x0)
+#define UART_THR(_baseaddr)			(_baseaddr + 0x0)
+#define UART_IER(_baseaddr)			(_baseaddr + 0x4)
+#define UART_IIR(_baseaddr)			(_baseaddr + 0x8)
+#define UART_FCR(_baseaddr)			(_baseaddr + 0x8)
+#define UART_LCR(_baseaddr)			(_baseaddr + 0xc)
+#define UART_MCR(_baseaddr)			(_baseaddr + 0x10)
+#define UART_LSR(_baseaddr)			(_baseaddr + 0x14)
+#define UART_MSR(_baseaddr)			(_baseaddr + 0x18)
+#define UART_SCR(_baseaddr)			(_baseaddr + 0x1c)
+#define UART_DLL(_baseaddr)			(_baseaddr + 0x0)
+#define UART_DLH(_baseaddr)			(_baseaddr + 0x4)
+#define UART_EFR(_baseaddr)			(_baseaddr + 0x8)
+#define UART_XON1(_baseaddr)			(_baseaddr + 0x10)
+#define UART_XON2(_baseaddr)			(_baseaddr + 0x14)
+#define UART_XOFF1(_baseaddr)			(_baseaddr + 0x18)
+#define UART_XOFF2(_baseaddr)			(_baseaddr + 0x1c)
+#define UART_AUTOBAUD(_baseaddr)		(_baseaddr + 0x20)
+#define UART_HIGHSPEED(_baseaddr)		(_baseaddr + 0x24)
+#define UART_SAMPLE_COUNT(_baseaddr)		(_baseaddr + 0x28)
+#define UART_SAMPLE_POINT(_baseaddr)		(_baseaddr + 0x2c)
+#define UART_AUTOBAUD_REG(_baseaddr)		(_baseaddr + 0x30)
+#define UART_RATE_FIX_REG(_baseaddr)		(_baseaddr + 0x34)
+#define UART_AUTO_BAUDSAMPLE(_baseaddr)		(_baseaddr + 0x38)
+#define UART_GUARD(_baseaddr)			(_baseaddr + 0x3c)
+#define UART_ESCAPE_DAT(_baseaddr)		(_baseaddr + 0x40)
+#define UART_ESCAPE_EN(_baseaddr)		(_baseaddr + 0x44)
+#define UART_SLEEP_EN(_baseaddr)		(_baseaddr + 0x48)
+#define UART_DMA_EN(_baseaddr)			(_baseaddr + 0x4c)
+#define UART_RXTRI_AD(_baseaddr)		(_baseaddr + 0x50)
+#define UART_FRACDIV_L(_baseaddr)		(_baseaddr + 0x54)
+#define UART_FRACDIV_M(_baseaddr)		(_baseaddr + 0x58)
+#define UART_FCR_RD(_baseaddr)			(_baseaddr + 0x5C)
+#define UART_USB_RX_SEL(_baseaddr)		(_baseaddr + 0xB0)
+#define UART_SLEEP_REQ(_baseaddr)		(_baseaddr + 0xB4)
+#define UART_SLEEP_ACK(_baseaddr)		(_baseaddr + 0xB8)
+#define UART_SPM_SEL(_baseaddr)			(_baseaddr + 0xBC)
+#define UART_LCR_DLAB				0x0080
+#define UART_LCR_MODE_B				0x00bf
+
+enum uart_port_ID {
+	UART_PORT0 = 0,
+	UART_PORT1
+};
+
+struct mt_uart_register {
+	unsigned int dll;
+	unsigned int dlh;
+	unsigned int ier;
+	unsigned int lcr;
+	unsigned int mcr;
+	unsigned int fcr;
+	unsigned int lsr;
+	unsigned int scr;
+	unsigned int efr;
+	unsigned int highspeed;
+	unsigned int sample_count;
+	unsigned int sample_point;
+	unsigned int fracdiv_l;
+	unsigned int fracdiv_m;
+	unsigned int escape_en;
+	unsigned int guard;
+	unsigned int rx_sel;
+};
+
+struct mt_uart {
+	unsigned long base;
+	struct mt_uart_register registers;
+};
+
+/* external API */
+void mt_uart_save(void);
+void mt_uart_restore(void);
+void mt_console_uart_cg(int on);
+int mt_console_uart_cg_status(void);
+
+#endif /* __UART_H__ */

plat/mediatek/mt8183/include/plat_debug.h

@@ -24,8 +24,6 @@
 #define BIT_CA15M_L2PARITY_EN		(1 << 1)
 #define BIT_CA15M_LASTPC_DIS		(1 << 8)
 
-#define MP1_CPUTOP_PWR_CON		0x10006218
-
 #define MCU_ALL_PWR_ON_CTRL		0x0c530b58
 #define PLAT_MTK_CIRCULAR_BUFFER_UNLOCK	0xefab4133
 #define PLAT_MTK_CIRCULAR_BUFFER_LOCK	0xefab4134

plat/mediatek/mt8183/include/platform_def.h

@@ -41,6 +41,7 @@
 #define APMIXEDSYS         (IO_PHYS + 0xC000)
 #define ARMPLL_LL_CON0     (APMIXEDSYS + 0x200)
 #define ARMPLL_L_CON0      (APMIXEDSYS + 0x210)
+#define ARMPLL_L_PWR_CON0  (APMIXEDSYS + 0x21c)
 #define MAINPLL_CON0       (APMIXEDSYS + 0x220)
 #define CCIPLL_CON0        (APMIXEDSYS + 0x290)
 
@@ -74,6 +75,7 @@
 #define MT_L2_WRITE_ACCESS_RATE  (MCUCFG_BASE + 0x604)
 #define MP0_CA7L_CACHE_CONFIG    (MCUCFG_BASE + 0x7f0)
 #define MP1_CA7L_CACHE_CONFIG    (MCUCFG_BASE + 0x7f4)
+#define EMI_WFIFO                (MCUCFG_BASE + 0x0b5c)
 
 /*******************************************************************************
  * GIC related constants
@@ -87,6 +89,7 @@
  * UART related constants
  ******************************************************************************/
 #define UART0_BASE    (IO_PHYS + 0x01002000)
+#define UART1_BASE    (IO_PHYS + 0x01003000)
 
 #define UART_BAUDRATE 115200
 #define UART_CLOCK    26000000

plat/mediatek/mt8183/include/sspm_reg.h

+/*
+ * Copyright (c) 2019, ARM Limited and Contributors. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef __SSPM_REG_H__
+#define __SSPM_REG_H__
+
+#include "platform_def.h"
+
+#define SSPM_CFGREG_RSV_RW_REG0        (SSPM_CFGREG_BASE + 0x0100)
+#define SSPM_CFGREG_ACAO_INT_SET       (SSPM_CFGREG_BASE + 0x00D8)
+#define SSPM_CFGREG_ACAO_INT_CLR       (SSPM_CFGREG_BASE + 0x00DC)
+#define SSPM_CFGREG_ACAO_WAKEUP_EN     (SSPM_CFGREG_BASE + 0x0204)
+
+#define STANDBYWFI_EN(n)               (1 << (n +  8))
+#define GIC_IRQOUT_EN(n)               (1 << (n +  0))
+
+#define NF_MCDI_MBOX                            19
+#define MCDI_MBOX_CLUSTER_0_CAN_POWER_OFF       0
+#define MCDI_MBOX_CLUSTER_1_CAN_POWER_OFF       1
+#define MCDI_MBOX_BUCK_POWER_OFF_MASK           2
+#define MCDI_MBOX_CLUSTER_0_ATF_ACTION_DONE     3
+#define MCDI_MBOX_CLUSTER_1_ATF_ACTION_DONE     4
+#define MCDI_MBOX_BOOTADDR                      5
+#define MCDI_MBOX_PAUSE_ACTION                  6
+#define MCDI_MBOX_AVAIL_CPU_MASK                7
+#define MCDI_MBOX_CPU_CLUSTER_PWR_STAT          8
+#define MCDI_MBOX_ACTION_STAT                   9
+#define MCDI_MBOX_CLUSTER_0_CNT                 10
+#define MCDI_MBOX_CLUSTER_1_CNT                 11
+#define MCDI_MBOX_CPU_ISOLATION_MASK            12
+#define MCDI_MBOX_PAUSE_ACK                     13
+#define MCDI_MBOX_PENDING_ON_EVENT              14
+#define MCDI_MBOX_PROF_CMD                      15
+#define MCDI_MBOX_DRCC_CALI_DONE                16
+#define MCDI_MBOX_HP_CMD                        17
+#define MCDI_MBOX_HP_ACK                        18
+
+#endif /* __SSPM_REG_H__ */

plat/mediatek/mt8183/plat_debug.c

@@ -9,6 +9,7 @@
 #include <lib/mmio.h>
 #include <plat_debug.h>
 #include <platform_def.h>
+#include <spm.h>
 
 void circular_buffer_setup(void)
 {

plat/mediatek/mt8183/platform.mk

@@ -9,10 +9,14 @@ MTK_PLAT_SOC  := ${MTK_PLAT}/${PLAT}
 
 PLAT_INCLUDES := -I${MTK_PLAT}/common/                            \
                  -I${MTK_PLAT_SOC}/drivers/                       \
+                 -I${MTK_PLAT_SOC}/drivers/mcdi/                  \
                  -I${MTK_PLAT_SOC}/drivers/spmc/                  \
                  -I${MTK_PLAT_SOC}/drivers/gpio/                  \
                  -I${MTK_PLAT_SOC}/drivers/pmic/                  \
+                 -I${MTK_PLAT_SOC}/drivers/spm/                   \
+                 -I${MTK_PLAT_SOC}/drivers/sspm/                  \
                  -I${MTK_PLAT_SOC}/drivers/rtc/                   \
+                 -I${MTK_PLAT_SOC}/drivers/uart/                  \
                  -I${MTK_PLAT_SOC}/include/
 
 PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c       \
@@ -45,15 +49,21 @@ BL31_SOURCES    += common/desc_image_load.c                              \
                    ${MTK_PLAT_SOC}/drivers/mcsi/mcsi.c                   \
                    ${MTK_PLAT_SOC}/drivers/pmic/pmic.c                   \
                    ${MTK_PLAT_SOC}/drivers/rtc/rtc.c                     \
+                   ${MTK_PLAT_SOC}/drivers/mcdi/mtk_mcdi.c               \
                    ${MTK_PLAT_SOC}/drivers/spmc/mtspmc.c                 \
+                   ${MTK_PLAT_SOC}/drivers/spm/spm.c                     \
+                   ${MTK_PLAT_SOC}/drivers/spm/spm_pmic_wrap.c           \
+                   ${MTK_PLAT_SOC}/drivers/spm/spm_suspend.c             \
                    ${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c                 \
+                   ${MTK_PLAT_SOC}/drivers/uart/uart.c                   \
                    ${MTK_PLAT_SOC}/plat_pm.c                             \
                    ${MTK_PLAT_SOC}/plat_topology.c                       \
                    ${MTK_PLAT_SOC}/plat_mt_gic.c                         \
                    ${MTK_PLAT_SOC}/plat_dcm.c                            \
                    ${MTK_PLAT_SOC}/bl31_plat_setup.c                     \
                    ${MTK_PLAT_SOC}/plat_debug.c                          \
-                   ${MTK_PLAT_SOC}/scu.c
+                   ${MTK_PLAT_SOC}/scu.c                                 \
+                   ${MTK_PLAT_SOC}/drivers/sspm/sspm.c
 
 # Enable workarounds for selected Cortex-A53 erratas.
 ERRATA_A53_826319 := 0