Commit 3f0d4f1b authored by Siva Durga Prasad Paladugu's avatar Siva Durga Prasad Paladugu Committed by Siva Durga Prasad Paladugu
Browse files

plat: xilinx: zynqmp: Make fpga load blocking until completed



This patch makes bitstream load blocking call and waits until
bitstream is loaded successfully or return with error.
Signed-off-by: default avatarSiva Durga Prasad Paladugu <sivadur@xilinx.com>
Tested-by: default avatarAvesh Khan <aveshk@xilinx.com>
parent b84fb058
...@@ -538,7 +538,7 @@ enum pm_ret_status pm_fpga_load(uint32_t address_low, ...@@ -538,7 +538,7 @@ enum pm_ret_status pm_fpga_load(uint32_t address_low,
/* Send request to the PMU */ /* Send request to the PMU */
PM_PACK_PAYLOAD5(payload, PM_FPGA_LOAD, address_high, address_low, PM_PACK_PAYLOAD5(payload, PM_FPGA_LOAD, address_high, address_low,
size, flags); size, flags);
return pm_ipi_send(primary_proc, payload); return pm_ipi_send_sync(primary_proc, payload, NULL, 0);
} }
/** /**
......
Markdown is supported
0% or .
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment