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Commit 4213e9ba authored by Antonio Nino Diaz's avatar Antonio Nino Diaz
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drivers: cci: Fix MISRA defects 



Change-Id: Ifdb0ceec19d267b14d796b5d31f08f7342190484
Signed-off-by: default avatarAntonio Nino Diaz <antonio.ninodiaz@arm.com>
parent 6d5f0631
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drivers/arm/cci/cci.c
View file @ 4213e9ba
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -10,11 +10,12 @@ ...@@ -10,11 +10,12 @@
#include <cci.h> #include <cci.h>
#include <debug.h> #include <debug.h>
#include <mmio.h> #include <mmio.h>
#include <stdbool.h>
#include <stdint.h> #include <stdint.h>
#define MAKE_CCI_PART_NUMBER(hi, lo) ((hi << 8) | lo) #define MAKE_CCI_PART_NUMBER(hi, lo) (((hi) << 8) | (lo))
#define CCI_PART_LO_MASK 0xff #define CCI_PART_LO_MASK U(0xff)
#define CCI_PART_HI_MASK 0xf #define CCI_PART_HI_MASK U(0xf)
/* CCI part number codes read from Peripheral ID registers 0 and 1 */ /* CCI part number codes read from Peripheral ID registers 0 and 1 */
#define CCI400_PART_NUM 0x420 #define CCI400_PART_NUM 0x420
...@@ -32,14 +33,14 @@ static const int *cci_slave_if_map; ...@@ -32,14 +33,14 @@ static const int *cci_slave_if_map;
static unsigned int max_master_id; static unsigned int max_master_id;
static int cci_num_slave_ports; static int cci_num_slave_ports;
static int validate_cci_map(const int *map) static bool validate_cci_map(const int *map)
{ {
unsigned int valid_cci_map = 0; unsigned int valid_cci_map = 0U;
int slave_if_id; int slave_if_id;
int i; unsigned int i;
/* Validate the map */ /* Validate the map */
for (i = 0; i <= max_master_id; i++) { for (i = 0U; i <= max_master_id; i++) {
slave_if_id = map[i]; slave_if_id = map[i];
if (slave_if_id < 0) if (slave_if_id < 0)
...@@ -47,22 +48,22 @@ static int validate_cci_map(const int *map) ...@@ -47,22 +48,22 @@ static int validate_cci_map(const int *map)
if (slave_if_id >= cci_num_slave_ports) { if (slave_if_id >= cci_num_slave_ports) {
ERROR("Slave interface ID is invalid\n"); ERROR("Slave interface ID is invalid\n");
return 0; return false;
} }
if (valid_cci_map & (1 << slave_if_id)) { if ((valid_cci_map & (1U << slave_if_id)) != 0U) {
ERROR("Multiple masters are assigned same slave interface ID\n"); ERROR("Multiple masters are assigned same slave interface ID\n");
return 0; return false;
} }
valid_cci_map |= 1 << slave_if_id; valid_cci_map |= 1U << slave_if_id;
} }
if (!valid_cci_map) { if (valid_cci_map == 0U) {
ERROR("No master is assigned a valid slave interface\n"); ERROR("No master is assigned a valid slave interface\n");
return 0; return false;
} }
return 1; return true;
} }
/* /*
...@@ -108,8 +109,8 @@ static int get_slave_ports(unsigned int part_num) ...@@ -108,8 +109,8 @@ static int get_slave_ports(unsigned int part_num)
void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters) void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters)
{ {
assert(map); assert(map != NULL);
assert(base); assert(base != 0U);
cci_base = base; cci_base = base;
cci_slave_if_map = map; cci_slave_if_map = map;
...@@ -119,7 +120,7 @@ void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters) ...@@ -119,7 +120,7 @@ void cci_init(uintptr_t base, const int *map, unsigned int num_cci_masters)
* Master Id's are assigned from zero, So in an array of size n * Master Id's are assigned from zero, So in an array of size n
* the max master id is (n - 1). * the max master id is (n - 1).
*/ */
max_master_id = num_cci_masters - 1; max_master_id = num_cci_masters - 1U;
cci_num_slave_ports = get_slave_ports(read_cci_part_number(base)); cci_num_slave_ports = get_slave_ports(read_cci_part_number(base));
#endif #endif
assert(cci_num_slave_ports >= 0); assert(cci_num_slave_ports >= 0);
...@@ -133,7 +134,7 @@ void cci_enable_snoop_dvm_reqs(unsigned int master_id) ...@@ -133,7 +134,7 @@ void cci_enable_snoop_dvm_reqs(unsigned int master_id)
assert(master_id <= max_master_id); assert(master_id <= max_master_id);
assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0)); assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0));
assert(cci_base); assert(cci_base != 0U);
/* /*
* Enable Snoops and DVM messages, no need for Read/Modify/Write as * Enable Snoops and DVM messages, no need for Read/Modify/Write as
...@@ -150,7 +151,7 @@ void cci_enable_snoop_dvm_reqs(unsigned int master_id) ...@@ -150,7 +151,7 @@ void cci_enable_snoop_dvm_reqs(unsigned int master_id)
dsbish(); dsbish();
/* Wait for the dust to settle down */ /* Wait for the dust to settle down */
while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U)
; ;
} }
...@@ -160,7 +161,7 @@ void cci_disable_snoop_dvm_reqs(unsigned int master_id) ...@@ -160,7 +161,7 @@ void cci_disable_snoop_dvm_reqs(unsigned int master_id)
assert(master_id <= max_master_id); assert(master_id <= max_master_id);
assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0)); assert((slave_if_id < cci_num_slave_ports) && (slave_if_id >= 0));
assert(cci_base); assert(cci_base != 0U);
/* /*
* Disable Snoops and DVM messages, no need for Read/Modify/Write as * Disable Snoops and DVM messages, no need for Read/Modify/Write as
...@@ -177,7 +178,7 @@ void cci_disable_snoop_dvm_reqs(unsigned int master_id) ...@@ -177,7 +178,7 @@ void cci_disable_snoop_dvm_reqs(unsigned int master_id)
dsbish(); dsbish();
/* Wait for the dust to settle down */ /* Wait for the dust to settle down */
while (mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U)
; ;
} }
include/drivers/arm/cci.h
View file @ 4213e9ba
/* /*
* Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
...@@ -7,94 +7,96 @@ ...@@ -7,94 +7,96 @@
#ifndef __CCI_H__ #ifndef __CCI_H__
#define __CCI_H__ #define __CCI_H__
#include <utils_def.h>
/* Slave interface offsets from PERIPHBASE */ /* Slave interface offsets from PERIPHBASE */
#define SLAVE_IFACE6_OFFSET 0x7000 #define SLAVE_IFACE6_OFFSET UL(0x7000)
#define SLAVE_IFACE5_OFFSET 0x6000 #define SLAVE_IFACE5_OFFSET UL(0x6000)
#define SLAVE_IFACE4_OFFSET 0x5000 #define SLAVE_IFACE4_OFFSET UL(0x5000)
#define SLAVE_IFACE3_OFFSET 0x4000 #define SLAVE_IFACE3_OFFSET UL(0x4000)
#define SLAVE_IFACE2_OFFSET 0x3000 #define SLAVE_IFACE2_OFFSET UL(0x3000)
#define SLAVE_IFACE1_OFFSET 0x2000 #define SLAVE_IFACE1_OFFSET UL(0x2000)
#define SLAVE_IFACE0_OFFSET 0x1000 #define SLAVE_IFACE0_OFFSET UL(0x1000)
#define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \ #define SLAVE_IFACE_OFFSET(index) (SLAVE_IFACE0_OFFSET + \
(0x1000 * (index))) (UL(0x1000) * (index)))
/* Slave interface event and count register offsets from PERIPHBASE */ /* Slave interface event and count register offsets from PERIPHBASE */
#define EVENT_SELECT7_OFFSET 0x80000 #define EVENT_SELECT7_OFFSET UL(0x80000)
#define EVENT_SELECT6_OFFSET 0x70000 #define EVENT_SELECT6_OFFSET UL(0x70000)
#define EVENT_SELECT5_OFFSET 0x60000 #define EVENT_SELECT5_OFFSET UL(0x60000)
#define EVENT_SELECT4_OFFSET 0x50000 #define EVENT_SELECT4_OFFSET UL(0x50000)
#define EVENT_SELECT3_OFFSET 0x40000 #define EVENT_SELECT3_OFFSET UL(0x40000)
#define EVENT_SELECT2_OFFSET 0x30000 #define EVENT_SELECT2_OFFSET UL(0x30000)
#define EVENT_SELECT1_OFFSET 0x20000 #define EVENT_SELECT1_OFFSET UL(0x20000)
#define EVENT_SELECT0_OFFSET 0x10000 #define EVENT_SELECT0_OFFSET UL(0x10000)
#define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \ #define EVENT_OFFSET(index) (EVENT_SELECT0_OFFSET + \
(0x10000 * (index))) (UL(0x10000) * (index)))
/* Control and ID register offsets */ /* Control and ID register offsets */
#define CTRL_OVERRIDE_REG 0x0 #define CTRL_OVERRIDE_REG U(0x0)
#define SECURE_ACCESS_REG 0x8 #define SECURE_ACCESS_REG U(0x8)
#define STATUS_REG 0xc #define STATUS_REG U(0xc)
#define IMPRECISE_ERR_REG 0x10 #define IMPRECISE_ERR_REG U(0x10)
#define PERFMON_CTRL_REG 0x100 #define PERFMON_CTRL_REG U(0x100)
#define IFACE_MON_CTRL_REG 0x104 #define IFACE_MON_CTRL_REG U(0x104)
/* Component and peripheral ID registers */ /* Component and peripheral ID registers */
#define PERIPHERAL_ID0 0xFE0 #define PERIPHERAL_ID0 U(0xFE0)
#define PERIPHERAL_ID1 0xFE4 #define PERIPHERAL_ID1 U(0xFE4)
#define PERIPHERAL_ID2 0xFE8 #define PERIPHERAL_ID2 U(0xFE8)
#define PERIPHERAL_ID3 0xFEC #define PERIPHERAL_ID3 U(0xFEC)
#define PERIPHERAL_ID4 0xFD0 #define PERIPHERAL_ID4 U(0xFD0)
#define PERIPHERAL_ID5 0xFD4 #define PERIPHERAL_ID5 U(0xFD4)
#define PERIPHERAL_ID6 0xFD8 #define PERIPHERAL_ID6 U(0xFD8)
#define PERIPHERAL_ID7 0xFDC #define PERIPHERAL_ID7 U(0xFDC)
#define COMPONENT_ID0 0xFF0 #define COMPONENT_ID0 U(0xFF0)
#define COMPONENT_ID1 0xFF4 #define COMPONENT_ID1 U(0xFF4)
#define COMPONENT_ID2 0xFF8 #define COMPONENT_ID2 U(0xFF8)
#define COMPONENT_ID3 0xFFC #define COMPONENT_ID3 U(0xFFC)
#define COMPONENT_ID4 0x1000 #define COMPONENT_ID4 U(0x1000)
#define COMPONENT_ID5 0x1004 #define COMPONENT_ID5 U(0x1004)
#define COMPONENT_ID6 0x1008 #define COMPONENT_ID6 U(0x1008)
#define COMPONENT_ID7 0x100C #define COMPONENT_ID7 U(0x100C)
/* Slave interface register offsets */ /* Slave interface register offsets */
#define SNOOP_CTRL_REG 0x0 #define SNOOP_CTRL_REG U(0x0)
#define SH_OVERRIDE_REG 0x4 #define SH_OVERRIDE_REG U(0x4)
#define READ_CHNL_QOS_VAL_OVERRIDE_REG 0x100 #define READ_CHNL_QOS_VAL_OVERRIDE_REG U(0x100)
#define WRITE_CHNL_QOS_VAL_OVERRIDE_REG 0x104 #define WRITE_CHNL_QOS_VAL_OVERRIDE_REG U(0x104)
#define MAX_OT_REG 0x110 #define MAX_OT_REG U(0x110)
/* Snoop Control register bit definitions */ /* Snoop Control register bit definitions */
#define DVM_EN_BIT (1 << 1) #define DVM_EN_BIT BIT_32(1)
#define SNOOP_EN_BIT (1 << 0) #define SNOOP_EN_BIT BIT_32(0)
#define SUPPORT_SNOOPS (1 << 30) #define SUPPORT_SNOOPS BIT_32(30)
#define SUPPORT_DVM (1 << 31) #define SUPPORT_DVM BIT_32(31)
/* Status register bit definitions */ /* Status register bit definitions */
#define CHANGE_PENDING_BIT (1 << 0) #define CHANGE_PENDING_BIT BIT_32(0)
/* Event and count register offsets */ /* Event and count register offsets */
#define EVENT_SELECT_REG 0x0 #define EVENT_SELECT_REG U(0x0)
#define EVENT_COUNT_REG 0x4 #define EVENT_COUNT_REG U(0x4)
#define COUNT_CNTRL_REG 0x8 #define COUNT_CNTRL_REG U(0x8)
#define COUNT_OVERFLOW_REG 0xC #define COUNT_OVERFLOW_REG U(0xC)
/* Slave interface monitor registers */ /* Slave interface monitor registers */
#define INT_MON_REG_SI0 0x90000 #define INT_MON_REG_SI0 U(0x90000)
#define INT_MON_REG_SI1 0x90004 #define INT_MON_REG_SI1 U(0x90004)
#define INT_MON_REG_SI2 0x90008 #define INT_MON_REG_SI2 U(0x90008)
#define INT_MON_REG_SI3 0x9000C #define INT_MON_REG_SI3 U(0x9000C)
#define INT_MON_REG_SI4 0x90010 #define INT_MON_REG_SI4 U(0x90010)
#define INT_MON_REG_SI5 0x90014 #define INT_MON_REG_SI5 U(0x90014)
#define INT_MON_REG_SI6 0x90018 #define INT_MON_REG_SI6 U(0x90018)
/* Master interface monitor registers */ /* Master interface monitor registers */
#define INT_MON_REG_MI0 0x90100 #define INT_MON_REG_MI0 U(0x90100)
#define INT_MON_REG_MI1 0x90104 #define INT_MON_REG_MI1 U(0x90104)
#define INT_MON_REG_MI2 0x90108 #define INT_MON_REG_MI2 U(0x90108)
#define INT_MON_REG_MI3 0x9010c #define INT_MON_REG_MI3 U(0x9010c)
#define INT_MON_REG_MI4 0x90110 #define INT_MON_REG_MI4 U(0x90110)
#define INT_MON_REG_MI5 0x90114 #define INT_MON_REG_MI5 U(0x90114)
#define SLAVE_IF_UNUSED -1 #define SLAVE_IF_UNUSED -1
......
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