Commit 4bbb3a54 authored by Suyash Pathak's avatar Suyash Pathak
Browse files

board/rddaniel: intialize tzc400 controllers



A TZC400 controller is placed inline on DRAM channels and regulates
the secure and non-secure accesses to both secure and non-secure
regions of the DRAM memory. Configure each of the TZC controllers
accordingly.

Change-Id: I75f6d13591a7fe9e50ce15c793e35a8018041815
Signed-off-by: default avatarSuyash Pathak <suyash.pathak@arm.com>
parent 4ed16765
......@@ -21,6 +21,21 @@
#define CSS_SYSTEM_PWR_DMN_LVL ARM_PWR_LVL2
#define PLAT_MAX_PWR_LVL ARM_PWR_LVL1
/* TZC Related Constants */
#define PLAT_ARM_TZC_BASE UL(0x21830000)
#define PLAT_ARM_TZC_FILTERS TZC_400_REGION_ATTR_FILTER_BIT(0)
#define TZC400_OFFSET UL(0x1000000)
#define TZC400_COUNT 4
#define TZC400_BASE(n) (PLAT_ARM_TZC_BASE + \
(n * TZC400_OFFSET))
#define TZC_NSAID_ALL_AP U(0)
#define PLAT_ARM_TZC_NS_DEV_ACCESS \
(TZC_REGION_ACCESS_RDWR(TZC_NSAID_ALL_AP))
/*
* Physical and virtual address space limits for MMU in AARCH64 & AARCH32 modes
*/
......
......@@ -18,6 +18,8 @@ BL2_SOURCES += ${RDDANIEL_BASE}/rddaniel_plat.c \
${RDDANIEL_BASE}/rddaniel_security.c \
${RDDANIEL_BASE}/rddaniel_err.c \
lib/utils/mem_region.c \
drivers/arm/tzc/tzc400.c \
plat/arm/common/arm_tzc400.c \
plat/arm/common/arm_nor_psci_mem_protect.c
BL31_SOURCES += ${SGI_CPU_SOURCES} \
......
......@@ -4,9 +4,19 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <plat/arm/common/plat_arm.h>
#include <platform_def.h>
static const arm_tzc_regions_info_t tzc_regions[] = {
ARM_TZC_REGIONS_DEF,
{}
};
/* Initialize the secure environment */
void plat_arm_security_setup(void)
{
int i;
for (i = 0; i < TZC400_COUNT; i++)
arm_tzc400_setup(TZC400_BASE(i), tzc_regions);
}
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