Make BL1 RO and RW base addresses configurable

BL1 RO and RW base address used to be fixed, respectively to the first
address of the Trusted ROM and the first address of the Trusted RAM.

Introduce new platform defines to configure the BL1 RO and RW base
addresses.

Change-Id: If26616513a47798593a4bb845a4b0fb37c867cd6

bl1/bl1.ld.S

@@ -41,7 +41,11 @@ MEMORY {
 
 SECTIONS
 {
-    ro : {
+    . = BL1_RO_BASE;
+    ASSERT(. == ALIGN(4096),
+           "BL1_RO_BASE address is not aligned on a page boundary.")
+
+    ro . : {
         __RO_START__ = .;
         *bl1_entrypoint.o(.text*)
         *(.text*)
@@ -52,16 +56,19 @@ SECTIONS
 
     /*
      * The .data section gets copied from ROM to RAM at runtime.
-     * Its LMA and VMA must be 16-byte aligned.
+     * Its LMA must be 16-byte aligned.
+     * Its VMA must be page-aligned as it marks the first read/write page.
      */
-    . = NEXT(16);        /* Align LMA */
-    .data : ALIGN(16) {  /* Align VMA */
+    . = BL1_RW_BASE;
+    ASSERT(. == ALIGN(4096),
+           "BL1_RW_BASE address is not aligned on a page boundary.")
+    .data . : ALIGN(16) {
         __DATA_RAM_START__ = .;
         *(.data*)
         __DATA_RAM_END__ = .;
     } >RAM AT>ROM
 
-    stacks (NOLOAD) : {
+    stacks . (NOLOAD) : {
         __STACKS_START__ = .;
         *(tzfw_normal_stacks)
         __STACKS_END__ = .;

plat/fvp/platform.h

@@ -235,6 +235,14 @@
 #define PLAT_AFF1_SUSPEND	0x2
 #define PLAT_AFF1_ON		0x3
 
+/*******************************************************************************
+ * BL1 specific defines.
+ * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base
+ * addresses.
+ ******************************************************************************/
+#define BL1_RO_BASE			TZROM_BASE
+#define BL1_RW_BASE			TZRAM_BASE
+
 /*******************************************************************************
  * BL2 specific defines.
  ******************************************************************************/