Commit 4fe55a2f authored by Madhukar Pappireddy's avatar Madhukar Pappireddy Committed by TrustedFirmware Code Review
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Merge "fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor...

Merge "fix(plat/marvell/a3720/uart): fix UART clock rate value and divisor calculation" into integration
parents fb88c71d 66a77528
......@@ -45,8 +45,9 @@ func console_a3700_core_init
cbz w2, init_fail
/* Program the baudrate */
/* Divisor = Uart clock / (16 * baudrate) */
/* Divisor = Round(Uartclock / (16 * baudrate)) */
lsl w2, w2, #4
add w1, w1, w2, lsr #1
udiv w2, w1, w2
and w2, w2, #0x3ff
......
......@@ -164,7 +164,7 @@
* PL011 related constants
*/
#define PLAT_MARVELL_BOOT_UART_BASE (MVEBU_REGS_BASE + 0x12000)
#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25804800
#define PLAT_MARVELL_BOOT_UART_CLK_IN_HZ 25000000
#define PLAT_MARVELL_CRASH_UART_BASE PLAT_MARVELL_BOOT_UART_BASE
#define PLAT_MARVELL_CRASH_UART_CLK_IN_HZ PLAT_MARVELL_BOOT_UART_CLK_IN_HZ
......
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