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Commit 530a5cbc authored by Sandrine Bailleux's avatar Sandrine Bailleux Committed by TrustedFirmware Code Review
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Merge changes from topic "tegra-downstream-092319" into integration 

* changes:
  Tegra194: add support to reset GPU
  Tegra194: memctrl: fix logic to check TZDRAM config register access
  Tegra: introduce plat_enable_console()
  Tegra: include: drivers: introduce spe.h
  Tegra194: update nvg header to v6.4
  Tegra194: mce: enable strict checking
  Tegra194: CC6 state from last offline CPU in the cluster
  Tegra194: console driver compilation from platform makefiles
  Tegra194: memctrl: platform handler for TZDRAM setup
  Tegra194: memctrl: override SE client as coherent
  Tegra194: save system suspend entry marker to TZDRAM
  Tegra194: helper functions for CPU rst handler and SMMU ctx offset
  Tegra194: cleanup references to Tegra186
  Tegra194: mce: display NVG header version during boot
  Tegra194: mce: fix cg_cstate encoding format
  Tegra194: drivers: SE and RNG1/PKA1 context save support
  Tegra194: rename secure scratch register macros
  Tegra194: SiP: Fix Rule 8.4 and Rule 10.4 violation
  Tegra194: mce: remove unsupported functionality
  Tegra194: sanity check target cluster during core power on
  Tegra194: fix defects flagged by MISRA scan
  Tegra194: mce: fix defects flagged by MISRA scan
  Tegra194: remove the GPU reset register macro
  Tegra194: MC registers to allow CPU accesses to TZRAM
  Tegra194: increase MAX_MMAP_REGIONS macro value
  Tegra194: update nvg header to v6.1
  Tegra194: update cache operations supported by the ROC
  Tegra194: memctrl: platform handlers to reprogram MSS
  Tegra194: core and cluster count values
  Tegra194: correct the TEGRA_CAR_RESET_BASE macro value
  Tegra194: add MC_SECURITY mask defines
  Tegra194: Update wake mask, wake time for cpu offlining
  Tegra194: program stream ids for XUSB
  Tegra194: Update checks for c-state stats
  Tegra194: smmu: fix mask for board revision id
  Tegra194: smmu: ISO support
  Tegra194: Initialize smmu on system suspend exit
  Tegra194: Update cpu core-id calculation
  Tegra194: read-modify-write ACTLR_ELx registers
  Tegra194: Enable fake system suspend
  Tegra194: convert 'target_cpu' and 'target_cluster' to 32-bits
  Tegra194: platform support for memctrl/smmu drivers
  Tegra194: Support for cpu suspend
parents 76f25eb5 2d1f1010
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plat/nvidia/tegra/common/tegra_bl31_setup.c
View file @ 530a5cbc
......@@ -129,10 +129,8 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
struct tegra_bl31_params *arg_from_bl2 = (struct tegra_bl31_params *) arg0;
plat_params_from_bl2_t *plat_params = (plat_params_from_bl2_t *)arg1;
image_info_t bl32_img_info = { {0} };
uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end, console_base;
uint32_t console_clock;
uint64_t tzdram_start, tzdram_end, bl32_start, bl32_end;
int32_t ret;
static console_16550_t console;
/*
* For RESET_TO_BL31 systems, BL31 is the first bootloader to run so
......@@ -182,31 +180,9 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
}
/*
* Reference clock used by the FPGAs is a lot slower.
* Enable console for the platform
*/
if (tegra_platform_is_fpga()) {
console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
} else {
console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
}
/*
* Get the base address of the UART controller to be used for the
* console
*/
console_base = plat_get_console_from_id(plat_params->uart_id);
if (console_base != 0U) {
/*
* Configure the UART port to be used as the console
*/
(void)console_16550_register(console_base,
console_clock,
TEGRA_CONSOLE_BAUDRATE,
&console);
console_set_scope(&console.console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
}
plat_enable_console(plat_params->uart_id);
/*
* The previous bootloader passes the base address of the shared memory
......
plat/nvidia/tegra/include/drivers/spe.h 0 → 100644
View file @ 530a5cbc
/*
* Copyright (c) 2019, NVIDIA Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPE_H
#define SPE_H
#include <stdint.h>
#include <drivers/console.h>
typedef struct {
console_t console;
uintptr_t base;
} console_spe_t;
/*
* Initialize a new spe console instance and register it with the console
* framework. The |console| pointer must point to storage that will be valid
* for the lifetime of the console, such as a global or static local variable.
* Its contents will be reinitialized from scratch.
*/
int console_spe_register(uintptr_t baseaddr, uint32_t clock, uint32_t baud,
console_spe_t *console);
#endif /* SPE_H */
plat/nvidia/tegra/include/t194/tegra194_private.h 0 → 100644
View file @ 530a5cbc
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __TEGRA194_PRIVATE_H__
#define __TEGRA194_PRIVATE_H__
void tegra194_cpu_reset_handler(void);
uint64_t tegra194_get_cpu_reset_handler_base(void);
uint64_t tegra194_get_cpu_reset_handler_size(void);
uint64_t tegra194_get_smmu_ctx_offset(void);
void tegra194_set_system_suspend_entry(void);
#endif /* __TEGRA194_PRIVATE_H__ */
plat/nvidia/tegra/include/t194/tegra_def.h
View file @ 530a5cbc
......@@ -14,9 +14,9 @@
* and `SYSTEM_SUSPEND` calls as the `state-id` field in the 'power state'
* parameter.
******************************************************************************/
#define PSTATE_ID_CORE_IDLE 6
#define PSTATE_ID_CORE_POWERDN 7
#define PSTATE_ID_SOC_POWERDN 2
#define PSTATE_ID_CORE_IDLE U(6)
#define PSTATE_ID_CORE_POWERDN U(7)
#define PSTATE_ID_SOC_POWERDN U(2)
/*******************************************************************************
* Platform power states (used by PSCI framework)
......@@ -24,215 +24,211 @@
* - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
* - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
******************************************************************************/
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE 8
/*******************************************************************************
* Implementation defined ACTLR_EL3 bit definitions
******************************************************************************/
#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
#define ACTLR_EL3_L2ECTLR_BIT (1 << 5)
#define ACTLR_EL3_L2CTLR_BIT (1 << 4)
#define ACTLR_EL3_CPUECTLR_BIT (1 << 1)
#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
#define ACTLR_EL3_ENABLE_ALL_ACCESS (ACTLR_EL3_L2ACTLR_BIT | \
ACTLR_EL3_L2ECTLR_BIT | \
ACTLR_EL3_L2CTLR_BIT | \
ACTLR_EL3_CPUECTLR_BIT | \
ACTLR_EL3_CPUACTLR_BIT)
#define PLAT_MAX_RET_STATE U(1)
#define PLAT_MAX_OFF_STATE U(8)
/*******************************************************************************
* Secure IRQ definitions
******************************************************************************/
#define TEGRA186_MAX_SEC_IRQS 5
#define TEGRA186_BPMP_WDT_IRQ 46
#define TEGRA186_SPE_WDT_IRQ 47
#define TEGRA186_SCE_WDT_IRQ 48
#define TEGRA186_TOP_WDT_IRQ 49
#define TEGRA186_AON_WDT_IRQ 50
#define TEGRA194_MAX_SEC_IRQS U(2)
#define TEGRA194_TOP_WDT_IRQ U(49)
#define TEGRA194_AON_WDT_IRQ U(50)
#define TEGRA186_SEC_IRQ_TARGET_MASK 0xFF /* 8 Carmel */
#define TEGRA194_SEC_IRQ_TARGET_MASK U(0xFF) /* 8 Carmel */
/*******************************************************************************
* Tegra Miscellanous register constants
******************************************************************************/
#define TEGRA_MISC_BASE 0x00100000
#define HARDWARE_REVISION_OFFSET 0x4
#define MISCREG_PFCFG 0x200C
/*******************************************************************************
* Tegra TSA Controller constants
******************************************************************************/
#define TEGRA_TSA_BASE 0x02000000
#define TSA_CONFIG_STATIC0_CSW_SESWR 0x1010
#define TSA_CONFIG_STATIC0_CSW_SESWR_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_ETRW 0xD034
#define TSA_CONFIG_STATIC0_CSW_ETRW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB 0x3020
#define TSA_CONFIG_STATIC0_CSW_SDMMCWAB_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_AXISW 0x8008
#define TSA_CONFIG_STATIC0_CSW_AXISW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_HDAW 0xD008
#define TSA_CONFIG_STATIC0_CSW_HDAW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_AONDMAW 0xE018
#define TSA_CONFIG_STATIC0_CSW_AONDMAW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_SCEDMAW 0x9008
#define TSA_CONFIG_STATIC0_CSW_SCEDMAW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW 0x9028
#define TSA_CONFIG_STATIC0_CSW_BPMPDMAW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_APEDMAW 0xB008
#define TSA_CONFIG_STATIC0_CSW_APEDMAW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_UFSHCW 0x6008
#define TSA_CONFIG_STATIC0_CSW_UFSHCW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_AFIW 0xF008
#define TSA_CONFIG_STATIC0_CSW_AFIW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_SATAW 0x4008
#define TSA_CONFIG_STATIC0_CSW_SATAW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_EQOSW 0x3038
#define TSA_CONFIG_STATIC0_CSW_EQOSW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW 0x6018
#define TSA_CONFIG_STATIC0_CSW_XUSB_DEVW_RESET 0x1100
#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW 0x6028
#define TSA_CONFIG_STATIC0_CSW_XUSB_HOSTW_RESET 0x1100
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK (0x3 << 11)
#define TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU (0 << 11)
#define TEGRA_MISC_BASE U(0x00100000)
#define HARDWARE_REVISION_OFFSET U(0x4)
#define MISCREG_EMU_REVID U(0x3160)
#define BOARD_MASK_BITS U(0xFF)
#define BOARD_SHIFT_BITS U(24)
#define MISCREG_PFCFG U(0x200C)
/*******************************************************************************
* Tegra Memory Controller constants
******************************************************************************/
#define TEGRA_MC_STREAMID_BASE 0x02C00000
#define TEGRA_MC_BASE 0x02C10000
#define TEGRA_MC_STREAMID_BASE U(0x02C00000)
#define TEGRA_MC_BASE U(0x02C10000)
/* General Security Carveout register macros */
#define MC_GSC_CONFIG_REGS_SIZE 0x40
#define MC_GSC_LOCK_CFG_SETTINGS_BIT (1 << 1)
#define MC_GSC_ENABLE_TZ_LOCK_BIT (1 << 0)
#define MC_GSC_SIZE_RANGE_4KB_SHIFT 27
#define MC_GSC_BASE_LO_SHIFT 12
#define MC_GSC_BASE_LO_MASK 0xFFFFF
#define MC_GSC_BASE_HI_SHIFT 0
#define MC_GSC_BASE_HI_MASK 3
#define MC_GSC_CONFIG_REGS_SIZE U(0x40)
#define MC_GSC_LOCK_CFG_SETTINGS_BIT (U(1) << 1)
#define MC_GSC_ENABLE_TZ_LOCK_BIT (U(1) << 0)
#define MC_GSC_SIZE_RANGE_4KB_SHIFT U(27)
#define MC_GSC_BASE_LO_SHIFT U(12)
#define MC_GSC_BASE_LO_MASK U(0xFFFFF)
#define MC_GSC_BASE_HI_SHIFT U(0)
#define MC_GSC_BASE_HI_MASK U(3)
#define MC_GSC_ENABLE_CPU_SECURE_BIT (U(1) << 31)
/* TZDRAM carveout configuration registers */
#define MC_SECURITY_CFG0_0 0x70
#define MC_SECURITY_CFG1_0 0x74
#define MC_SECURITY_CFG3_0 0x9BC
#define MC_SECURITY_CFG0_0 U(0x70)
#define MC_SECURITY_CFG1_0 U(0x74)
#define MC_SECURITY_CFG3_0 U(0x9BC)
#define MC_SECURITY_BOM_MASK (U(0xFFF) << 20)
#define MC_SECURITY_SIZE_MB_MASK (U(0x1FFF) << 0)
#define MC_SECURITY_BOM_HI_MASK (U(0x3) << 0)
#define MC_SECURITY_CFG_REG_CTRL_0 U(0x154)
#define SECURITY_CFG_WRITE_ACCESS_BIT (U(0x1) << 0)
#define SECURITY_CFG_WRITE_ACCESS_ENABLE U(0x0)
#define SECURITY_CFG_WRITE_ACCESS_DISABLE U(0x1)
/* Video Memory carveout configuration registers */
#define MC_VIDEO_PROTECT_BASE_HI 0x978
#define MC_VIDEO_PROTECT_BASE_LO 0x648
#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
#define MC_VIDEO_PROTECT_BASE_HI U(0x978)
#define MC_VIDEO_PROTECT_BASE_LO U(0x648)
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
/*
* Carveout (MC_SECURITY_CARVEOUT24) registers used to clear the
* non-overlapping Video memory region
*/
#define MC_VIDEO_PROTECT_CLEAR_CFG 0x25A0
#define MC_VIDEO_PROTECT_CLEAR_BASE_LO 0x25A4
#define MC_VIDEO_PROTECT_CLEAR_BASE_HI 0x25A8
#define MC_VIDEO_PROTECT_CLEAR_SIZE 0x25AC
#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 0x25B0
#define MC_VIDEO_PROTECT_CLEAR_CFG U(0x25A0)
#define MC_VIDEO_PROTECT_CLEAR_BASE_LO U(0x25A4)
#define MC_VIDEO_PROTECT_CLEAR_BASE_HI U(0x25A8)
#define MC_VIDEO_PROTECT_CLEAR_SIZE U(0x25AC)
#define MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 U(0x25B0)
/* TZRAM carveout (MC_SECURITY_CARVEOUT11) configuration registers */
#define MC_TZRAM_CARVEOUT_CFG 0x2190
#define MC_TZRAM_BASE_LO 0x2194
#define MC_TZRAM_BASE_HI 0x2198
#define MC_TZRAM_SIZE 0x219C
#define MC_TZRAM_CLIENT_ACCESS_CFG0 0x21A0
#define MC_TZRAM_CARVEOUT_CFG U(0x2190)
#define MC_TZRAM_BASE_LO U(0x2194)
#define MC_TZRAM_BASE_HI U(0x2198)
#define MC_TZRAM_SIZE U(0x219C)
#define MC_TZRAM_CLIENT_ACCESS0_CFG0 U(0x21A0)
#define MC_TZRAM_CLIENT_ACCESS1_CFG0 U(0x21A4)
#define TZRAM_ALLOW_MPCORER (U(1) << 7)
#define TZRAM_ALLOW_MPCOREW (U(1) << 25)
/* Memory Controller Reset Control registers */
#define MC_CLIENT_HOTRESET_CTRL1_VIFAL_FLUSH_ENB (1 << 27)
#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (1 << 28)
#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (1 << 29)
#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (1 << 30)
#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (1 << 31)
#define MC_CLIENT_HOTRESET_CTRL1_DLAA_FLUSH_ENB (U(1) << 28)
#define MC_CLIENT_HOTRESET_CTRL1_DLA1A_FLUSH_ENB (U(1) << 29)
#define MC_CLIENT_HOTRESET_CTRL1_PVA0A_FLUSH_ENB (U(1) << 30)
#define MC_CLIENT_HOTRESET_CTRL1_PVA1A_FLUSH_ENB (U(1) << 31)
/*******************************************************************************
* Tegra UART Controller constants
******************************************************************************/
#define TEGRA_UARTA_BASE 0x03100000
#define TEGRA_UARTB_BASE 0x03110000
#define TEGRA_UARTC_BASE 0x0C280000
#define TEGRA_UARTD_BASE 0x03130000
#define TEGRA_UARTE_BASE 0x03140000
#define TEGRA_UARTF_BASE 0x03150000
#define TEGRA_UARTG_BASE 0x0C290000
#define TEGRA_UARTA_BASE U(0x03100000)
#define TEGRA_UARTB_BASE U(0x03110000)
#define TEGRA_UARTC_BASE U(0x0C280000)
#define TEGRA_UARTD_BASE U(0x03130000)
#define TEGRA_UARTE_BASE U(0x03140000)
#define TEGRA_UARTF_BASE U(0x03150000)
#define TEGRA_UARTG_BASE U(0x0C290000)
/*******************************************************************************
* Tegra Fuse Controller related constants
******************************************************************************/
#define TEGRA_FUSE_BASE 0x03820000
#define OPT_SUBREVISION 0x248
#define SUBREVISION_MASK 0xF
#define TEGRA_FUSE_BASE U(0x03820000)
#define OPT_SUBREVISION U(0x248)
#define SUBREVISION_MASK U(0xF)
/*******************************************************************************
* GICv2 & interrupt handling related constants
******************************************************************************/
#define TEGRA_GICD_BASE 0x03881000
#define TEGRA_GICC_BASE 0x03882000
#define TEGRA_GICD_BASE U(0x03881000)
#define TEGRA_GICC_BASE U(0x03882000)
/*******************************************************************************
* Security Engine related constants
******************************************************************************/
#define TEGRA_SE0_BASE 0x03AC0000
#define SE_MUTEX_WATCHDOG_NS_LIMIT 0x6C
#define TEGRA_PKA1_BASE 0x03AD0000
#define PKA_MUTEX_WATCHDOG_NS_LIMIT 0x8144
#define TEGRA_RNG1_BASE 0x03AE0000
#define RNG_MUTEX_WATCHDOG_NS_LIMIT 0xFE0
#define TEGRA_SE0_BASE U(0x03AC0000)
#define SE0_MUTEX_WATCHDOG_NS_LIMIT U(0x6C)
#define SE0_AES0_ENTROPY_SRC_AGE_CTRL U(0x2FC)
#define TEGRA_PKA1_BASE U(0x03AD0000)
#define SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL U(0x144)
#define PKA1_MUTEX_WATCHDOG_NS_LIMIT SE_PKA1_CTRL_SE_MUTEX_TMOUT_DFTVAL
#define TEGRA_RNG1_BASE U(0x03AE0000)
#define RNG1_MUTEX_WATCHDOG_NS_LIMIT U(0xFE0)
/*******************************************************************************
* Tegra hardware synchronization primitives for the SPE engine
******************************************************************************/
#define TEGRA_AON_HSP_SM_6_7_BASE U(0x0c190000)
#define TEGRA_CONSOLE_SPE_BASE (TEGRA_AON_HSP_SM_6_7_BASE + U(0x8000))
/*******************************************************************************
* Tegra micro-seconds timer constants
******************************************************************************/
#define TEGRA_TMRUS_BASE 0x0C2E0000
#define TEGRA_TMRUS_SIZE 0x10000
#define TEGRA_TMRUS_BASE U(0x0C2E0000)
#define TEGRA_TMRUS_SIZE U(0x10000)
/*******************************************************************************
* Tegra Power Mgmt Controller constants
******************************************************************************/
#define TEGRA_PMC_BASE 0x0C360000
#define TEGRA_PMC_BASE U(0x0C360000)
/*******************************************************************************
* Tegra scratch registers constants
******************************************************************************/
#define TEGRA_SCRATCH_BASE 0x0C390000
#define SECURE_SCRATCH_RSV1_LO 0x06C
#define SECURE_SCRATCH_RSV1_HI 0x070
#define SECURE_SCRATCH_RSV6 0x094
#define SECURE_SCRATCH_RSV11_LO 0x0BC
#define SECURE_SCRATCH_RSV11_HI 0x0C0
#define SECURE_SCRATCH_RSV53_LO 0x20C
#define SECURE_SCRATCH_RSV53_HI 0x210
#define SECURE_SCRATCH_RSV54_HI 0x218
#define SECURE_SCRATCH_RSV55_LO 0x21C
#define SECURE_SCRATCH_RSV55_HI 0x220
#define TEGRA_SCRATCH_BASE U(0x0C390000)
#define SECURE_SCRATCH_RSV44_LO U(0x1C4)
#define SECURE_SCRATCH_RSV44_HI U(0x1C8)
#define SECURE_SCRATCH_RSV97 U(0x36C)
#define SECURE_SCRATCH_RSV99_LO U(0x37C)
#define SECURE_SCRATCH_RSV99_HI U(0x380)
#define SECURE_SCRATCH_RSV109_LO U(0x3CC)
#define SECURE_SCRATCH_RSV109_HI U(0x3D0)
#define SCRATCH_BL31_PARAMS_ADDR SECURE_SCRATCH_RSV44_LO
#define SCRATCH_BL31_PLAT_PARAMS_ADDR SECURE_SCRATCH_RSV44_HI
#define SCRATCH_SECURE_BOOTP_FCFG SECURE_SCRATCH_RSV97
#define SCRATCH_SMMU_TABLE_ADDR_LO SECURE_SCRATCH_RSV99_LO
#define SCRATCH_SMMU_TABLE_ADDR_HI SECURE_SCRATCH_RSV99_HI
#define SCRATCH_RESET_VECTOR_LO SECURE_SCRATCH_RSV109_LO
#define SCRATCH_RESET_VECTOR_HI SECURE_SCRATCH_RSV109_HI
/*******************************************************************************
* Tegra Memory Mapped Control Register Access Bus constants
******************************************************************************/
#define TEGRA_MMCRAB_BASE 0x0E000000
#define TEGRA_MMCRAB_BASE U(0x0E000000)
/*******************************************************************************
* Tegra SMMU Controller constants
******************************************************************************/
#define TEGRA_SMMU0_BASE 0x12000000
#define TEGRA_SMMU1_BASE 0x11000000
#define TEGRA_SMMU2_BASE 0x10000000
#define TEGRA_SMMU0_BASE U(0x12000000)
#define TEGRA_SMMU1_BASE U(0x11000000)
#define TEGRA_SMMU2_BASE U(0x10000000)
/*******************************************************************************
* Tegra TZRAM constants
******************************************************************************/
#define TEGRA_TZRAM_BASE 0x40000000
#define TEGRA_TZRAM_SIZE 0x40000
#define TEGRA_TZRAM_BASE U(0x40000000)
#define TEGRA_TZRAM_SIZE U(0x40000)
/*******************************************************************************
* Tegra Clock and Reset Controller constants
******************************************************************************/
#define TEGRA_CAR_RESET_BASE 0x200000000
#define TEGRA_GPU_RESET_REG_OFFSET 0x18UL
#define GPU_RESET_BIT (1UL << 0)
#define TEGRA_CAR_RESET_BASE U(0x20000000)
#define TEGRA_GPU_RESET_REG_OFFSET U(0x18)
#define TEGRA_GPU_RESET_GPU_SET_OFFSET U(0x1C)
#define GPU_RESET_BIT (U(1) << 0)
#define GPU_SET_BIT (U(1) << 0)
/*******************************************************************************
* XUSB PADCTL
******************************************************************************/
#define TEGRA_XUSB_PADCTL_BASE U(0x3520000)
#define TEGRA_XUSB_PADCTL_SIZE U(0x10000)
#define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 U(0x136c)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 U(0x1370)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 U(0x1374)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 U(0x1378)
#define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 U(0x137c)
#define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 U(0x139c)
/*******************************************************************************
* XUSB STREAMIDs
******************************************************************************/
#define TEGRA_SID_XUSB_HOST U(0x1b)
#define TEGRA_SID_XUSB_DEV U(0x1c)
#define TEGRA_SID_XUSB_VF0 U(0x5d)
#define TEGRA_SID_XUSB_VF1 U(0x5e)
#define TEGRA_SID_XUSB_VF2 U(0x5f)
#define TEGRA_SID_XUSB_VF3 U(0x60)
#endif /* __TEGRA_DEF_H__ */
plat/nvidia/tegra/include/tegra_private.h
View file @ 530a5cbc
......@@ -76,7 +76,7 @@ int32_t tegra_soc_validate_power_state(uint32_t power_state,
/* Declarations for plat_setup.c */
const mmap_region_t *plat_get_mmio_map(void);
uint32_t plat_get_console_from_id(int32_t id);
void plat_enable_console(int32_t id);
void plat_gic_setup(void);
struct tegra_bl31_params *plat_get_bl31_params(void);
plat_params_from_bl2_t *plat_get_bl31_plat_params(void);
......
plat/nvidia/tegra/soc/t132/plat_setup.c
View file @ 530a5cbc
......@@ -6,9 +6,11 @@
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <drivers/console.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
#include <plat/common/platform.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
/* sets of MMIO ranges setup */
......@@ -85,14 +87,30 @@ static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = {
};
/*******************************************************************************
* Retrieve the UART controller base to be used as the console
* Enable console corresponding to the console ID
******************************************************************************/
uint32_t plat_get_console_from_id(int id)
void plat_enable_console(int32_t id)
{
if (id > TEGRA132_MAX_UART_PORTS)
return 0;
static console_16550_t uart_console;
uint32_t console_clock;
return tegra132_uart_addresses[id];
if ((id > 0) && (id < TEGRA132_MAX_UART_PORTS)) {
/*
* Reference clock used by the FPGAs is a lot slower.
*/
if (tegra_platform_is_fpga()) {
console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
} else {
console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
}
(void)console_16550_register(tegra132_uart_addresses[id],
console_clock,
TEGRA_CONSOLE_BAUDRATE,
&uart_console);
console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
}
}
/*******************************************************************************
......
plat/nvidia/tegra/soc/t186/plat_setup.c
View file @ 530a5cbc
......@@ -141,19 +141,30 @@ static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
};
/*******************************************************************************
* Retrieve the UART controller base to be used as the console
* Enable console corresponding to the console ID
******************************************************************************/
uint32_t plat_get_console_from_id(int32_t id)
void plat_enable_console(int32_t id)
{
uint32_t ret;
static console_16550_t uart_console;
uint32_t console_clock;
if ((id > 0) && (id < TEGRA186_MAX_UART_PORTS)) {
/*
* Reference clock used by the FPGAs is a lot slower.
*/
if (tegra_platform_is_fpga()) {
console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
} else {
console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
}
if (id > TEGRA186_MAX_UART_PORTS) {
ret = 0;
} else {
ret = tegra186_uart_addresses[id];
(void)console_16550_register(tegra186_uart_addresses[id],
console_clock,
TEGRA_CONSOLE_BAUDRATE,
&uart_console);
console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
}
return ret;
}
/*******************************************************************************
......
plat/nvidia/tegra/soc/t194/drivers/include/mce_private.h
View file @ 530a5cbc
......@@ -7,44 +7,40 @@
#ifndef __MCE_PRIVATE_H__
#define __MCE_PRIVATE_H__
#include <mmio.h>
#include <tegra_def.h>
/*******************************************************************************
* Macros to prepare CSTATE info request
******************************************************************************/
/* Description of the parameters for UPDATE_CSTATE_INFO request */
#define CLUSTER_CSTATE_MASK 0x7UL
#define CLUSTER_CSTATE_SHIFT 0X0UL
#define CLUSTER_CSTATE_UPDATE_BIT (1UL << 7)
#define CCPLEX_CSTATE_MASK 0x3UL
#define CCPLEX_CSTATE_SHIFT 8UL
#define CCPLEX_CSTATE_UPDATE_BIT (1UL << 15)
#define SYSTEM_CSTATE_MASK 0xFUL
#define SYSTEM_CSTATE_SHIFT 16UL
#define SYSTEM_CSTATE_UPDATE_BIT (1UL << 23)
#define CSTATE_WAKE_MASK_UPDATE_BIT (1UL << 31)
#define CSTATE_WAKE_MASK_SHIFT 32UL
#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFUL
#define CLUSTER_CSTATE_MASK 0x7U
#define CLUSTER_CSTATE_SHIFT 0X0U
#define CLUSTER_CSTATE_UPDATE_BIT (1U << 7)
#define CCPLEX_CSTATE_MASK 0x7U
#define CCPLEX_CSTATE_SHIFT 8U
#define CCPLEX_CSTATE_UPDATE_BIT (1U << 15)
#define SYSTEM_CSTATE_MASK 0xFU
#define SYSTEM_CSTATE_SHIFT 16U
#define SYSTEM_CSTATE_UPDATE_BIT (1U << 23)
#define CSTATE_WAKE_MASK_UPDATE_BIT (1U << 31)
#define CSTATE_WAKE_MASK_SHIFT 32U
#define CSTATE_WAKE_MASK_CLEAR 0xFFFFFFFFU
/*******************************************************************************
* Auto-CC3 control macros
* Core ID mask (bits 3:0 in the online request)
******************************************************************************/
#define MCE_AUTO_CC3_FREQ_MASK 0xFFUL
#define MCE_AUTO_CC3_FREQ_SHIFT 0UL
#define MCE_AUTO_CC3_ENABLE_BIT (1UL << 31)
#define MCE_CORE_ID_MASK 0xFU
/*******************************************************************************
* Core ID mask (bits 3:0 in the online request)
* C-state statistics macros
******************************************************************************/
#define MCE_CORE_ID_MASK 0xFUL
#define MCE_STAT_ID_SHIFT 16U
/*******************************************************************************
* Cache control macros
* Security config macros
******************************************************************************/
#define CACHE_CLEAN_SET (1UL << 0)
#define CACHE_CLEAN_INVAL_SET (1UL << 1)
#define CACHE_CLEAN_INVAL_TR_SET (1UL << 2)
#define STRICT_CHECKING_ENABLED_SET (1UL << 0)
#define STRICT_CHECKING_LOCKED_SET (1UL << 1)
/* declarations for NVG handler functions */
uint64_t nvg_get_version(void);
......@@ -55,20 +51,25 @@ int32_t nvg_disable_power_saver_modes(void);
void nvg_set_wake_time(uint32_t wake_time);
void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
uint32_t system, uint32_t wake_mask, uint8_t update_wake_mask);
int32_t nvg_update_crossover_time(uint32_t type, uint32_t time);
int32_t nvg_set_cstate_stat_query_value(uint64_t data);
uint64_t nvg_get_cstate_stat_query_value(void);
int32_t nvg_is_sc7_allowed(void);
int32_t nvg_online_core(uint32_t core);
int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable);
int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx);
int32_t nvg_roc_flush_cache(void);
int32_t nvg_roc_clean_cache(void);
int32_t nvg_roc_flush_cache(void);
int32_t nvg_roc_clean_cache_trbits(void);
int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time);
void nvg_set_request_data(uint64_t req, uint64_t data);
void nvg_set_request(uint64_t req);
uint64_t nvg_get_result(void);
uint64_t nvg_cache_clean(void);
uint64_t nvg_cache_clean_inval(void);
uint64_t nvg_cache_inval_all(void);
int32_t nvg_roc_clean_cache_trbits(void);
void nvg_enable_strict_checking_mode(void);
/* MCE helper functions */
void mce_enable_strict_checking(void);
#endif /* __MCE_PRIVATE_H__ */
plat/nvidia/tegra/soc/t194/drivers/include/se.h 0 → 100644
View file @ 530a5cbc
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SE_H__
#define __SE_H__
int32_t tegra_se_suspend(void);
void tegra_se_resume(void);
#endif /* __SE_H__ */
plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h
View file @ 530a5cbc
......@@ -19,257 +19,315 @@
* occur when there is only new functionality.
*/
enum {
TEGRA_NVG_VERSION_MAJOR = 6,
TEGRA_NVG_VERSION_MINOR = 0,
TEGRA_NVG_VERSION_MAJOR = 6,
TEGRA_NVG_VERSION_MINOR = 4
};
typedef enum {
TEGRA_NVG_CHANNEL_VERSION = 0,
TEGRA_NVG_CHANNEL_POWER_PERF = 1,
TEGRA_NVG_CHANNEL_POWER_MODES = 2,
TEGRA_NVG_CHANNEL_WAKE_TIME = 3,
TEGRA_NVG_CHANNEL_CSTATE_INFO = 4,
TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5,
TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6,
// Value 7 reserved
TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8,
// Value 9 reserved
TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10,
TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11,
// Values 12-42 reserved
TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43,
TEGRA_NVG_CHANNEL_ONLINE_CORE = 44,
TEGRA_NVG_CHANNEL_CC3_CTRL = 45,
TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50,
TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL = 51,
// 52 FREQ FEEDBACK
TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53,
TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54,
TEGRA_NVG_CHANNEL_LAST_INDEX,
TEGRA_NVG_CHANNEL_VERSION = 0,
TEGRA_NVG_CHANNEL_POWER_PERF = 1,
TEGRA_NVG_CHANNEL_POWER_MODES = 2,
TEGRA_NVG_CHANNEL_WAKE_TIME = 3,
TEGRA_NVG_CHANNEL_CSTATE_INFO = 4,
TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND = 5,
TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND = 6,
TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND = 8,
TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST = 10,
TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE = 11,
TEGRA_NVG_CHANNEL_SHUTDOWN = 42,
TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED = 43,
TEGRA_NVG_CHANNEL_ONLINE_CORE = 44,
TEGRA_NVG_CHANNEL_CC3_CTRL = 45,
TEGRA_NVG_CHANNEL_CCPLEX_CACHE_CONTROL = 49,
TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC = 50,
TEGRA_NVG_CHANNEL_HSM_ERROR_CTRL = 53,
TEGRA_NVG_CHANNEL_SECURITY_CONFIG = 54,
TEGRA_NVG_CHANNEL_DEBUG_CONFIG = 55,
TEGRA_NVG_CHANNEL_DDA_SNOC_MCF = 56,
TEGRA_NVG_CHANNEL_DDA_MCF_ORD1 = 57,
TEGRA_NVG_CHANNEL_DDA_MCF_ORD2 = 58,
TEGRA_NVG_CHANNEL_DDA_MCF_ORD3 = 59,
TEGRA_NVG_CHANNEL_DDA_MCF_ISO = 60,
TEGRA_NVG_CHANNEL_DDA_MCF_SISO = 61,
TEGRA_NVG_CHANNEL_DDA_MCF_NISO = 62,
TEGRA_NVG_CHANNEL_DDA_MCF_NISO_REMOTE = 63,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_ISO = 64,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_SISO = 65,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO = 66,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_NISO_REMOTE = 67,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3FILL = 68,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3WR = 69,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_L3RD_DMA = 70,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_RSP_MCFRD_DMA = 71,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_GLOBAL = 72,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_LL = 73,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_L3D = 74,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_RD = 75,
TEGRA_NVG_CHANNEL_DDA_L3CTRL_FCM_WR = 76,
TEGRA_NVG_CHANNEL_DDA_SNOC_GLOBAL_CTRL = 77,
TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REQ_CTRL = 78,
TEGRA_NVG_CHANNEL_DDA_SNOC_CLIENT_REPLENTISH_CTRL = 79,
TEGRA_NVG_CHANNEL_LAST_INDEX
} tegra_nvg_channel_id_t;
typedef enum {
// Value 0 reserved
NVG_STAT_QUERY_SC7_ENTRIES = 1,
// Values 2-5 reserved
NVG_STAT_QUERY_CC6_ENTRIES = 6,
NVG_STAT_QUERY_CG7_ENTRIES = 7,
// Values 8-9 reserved
NVG_STAT_QUERY_C6_ENTRIES = 10,
// Values 11-13 reserved
NVG_STAT_QUERY_C7_ENTRIES = 14,
// Values 15-31 reserved
NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32,
NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41,
NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46,
NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51,
NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56,
NVG_STAT_QUERY_SC7_ENTRIES = 1,
NVG_STAT_QUERY_CC6_ENTRIES = 6,
NVG_STAT_QUERY_CG7_ENTRIES = 7,
NVG_STAT_QUERY_C6_ENTRIES = 10,
NVG_STAT_QUERY_C7_ENTRIES = 14,
NVG_STAT_QUERY_SC7_RESIDENCY_SUM = 32,
NVG_STAT_QUERY_CC6_RESIDENCY_SUM = 41,
NVG_STAT_QUERY_CG7_RESIDENCY_SUM = 46,
NVG_STAT_QUERY_C6_RESIDENCY_SUM = 51,
NVG_STAT_QUERY_C7_RESIDENCY_SUM = 56,
NVG_STAT_QUERY_SC7_ENTRY_TIME_SUM = 60,
NVG_STAT_QUERY_CC6_ENTRY_TIME_SUM = 61,
NVG_STAT_QUERY_CG7_ENTRY_TIME_SUM = 62,
NVG_STAT_QUERY_C6_ENTRY_TIME_SUM = 63,
NVG_STAT_QUERY_C7_ENTRY_TIME_SUM = 64,
NVG_STAT_QUERY_SC7_EXIT_TIME_SUM = 70,
NVG_STAT_QUERY_CC6_EXIT_TIME_SUM = 71,
NVG_STAT_QUERY_CG7_EXIT_TIME_SUM = 72,
NVG_STAT_QUERY_C6_EXIT_TIME_SUM = 73,
NVG_STAT_QUERY_C7_EXIT_TIME_SUM = 74,
NVG_STAT_QUERY_SC7_ENTRY_LAST = 80,
NVG_STAT_QUERY_CC6_ENTRY_LAST = 81,
NVG_STAT_QUERY_CG7_ENTRY_LAST = 82,
NVG_STAT_QUERY_C6_ENTRY_LAST = 83,
NVG_STAT_QUERY_C7_ENTRY_LAST = 84,
NVG_STAT_QUERY_SC7_EXIT_LAST = 90,
NVG_STAT_QUERY_CC6_EXIT_LAST = 91,
NVG_STAT_QUERY_CG7_EXIT_LAST = 92,
NVG_STAT_QUERY_C6_EXIT_LAST = 93,
NVG_STAT_QUERY_C7_EXIT_LAST = 94
} tegra_nvg_stat_query_t;
typedef enum {
TEGRA_NVG_CORE_C0 = 0,
TEGRA_NVG_CORE_C1 = 1,
TEGRA_NVG_CORE_C6 = 6,
TEGRA_NVG_CORE_C7 = 7,
TEGRA_NVG_CORE_WARMRSTREQ = 8,
TEGRA_NVG_CORE_C0 = 0,
TEGRA_NVG_CORE_C1 = 1,
TEGRA_NVG_CORE_C6 = 6,
TEGRA_NVG_CORE_C7 = 7,
TEGRA_NVG_CORE_WARMRSTREQ = 8
} tegra_nvg_core_sleep_state_t;
typedef enum {
TEGRA_NVG_CLUSTER_CC0 = 0,
TEGRA_NVG_CLUSTER_CC6 = 6,
TEGRA_NVG_CLUSTER_CC0 = 0,
TEGRA_NVG_CLUSTER_CC6 = 6
} tegra_nvg_cluster_sleep_state_t;
typedef enum {
TEGRA_NVG_CCPLEX_CG0 = 0,
TEGRA_NVG_CCPLEX_CG7 = 1,
TEGRA_NVG_CG_CG0 = 0,
TEGRA_NVG_CG_CG7 = 7
} tegra_nvg_cluster_group_sleep_state_t;
typedef enum {
TEGRA_NVG_SYSTEM_SC0 = 0,
TEGRA_NVG_SYSTEM_SC7 = 7,
TEGRA_NVG_SYSTEM_SC8 = 8,
TEGRA_NVG_SYSTEM_SC0 = 0,
TEGRA_NVG_SYSTEM_SC7 = 7,
TEGRA_NVG_SYSTEM_SC8 = 8
} tegra_nvg_system_sleep_state_t;
// ---------------------------------------------------------------------------
// NVG Data subformats
// ---------------------------------------------------------------------------
typedef union
{
uint64_t flat;
struct nvg_version_channel_t {
uint64_t minor_version : 32;
uint64_t major_version : 32;
} bits;
typedef union {
uint64_t flat;
struct nvg_version_channel_t {
uint32_t minor_version : 32;
uint32_t major_version : 32;
} bits;
} nvg_version_data_t;
typedef union nvg_channel_1_data_u
{
uint64_t flat;
struct nvg_channel_1_data_s
{
uint64_t perf_per_watt_mode : 1;
uint64_t reserved_63_1 : 63;
} bits;
typedef union {
uint64_t flat;
struct nvg_power_perf_channel_t {
uint32_t perf_per_watt : 1;
uint32_t reserved_31_1 : 31;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_power_perf_channel_t;
typedef union {
uint64_t flat;
struct nvg_power_modes_channel_t {
uint32_t low_battery : 1;
uint32_t reserved_1_1 : 1;
uint32_t battery_save : 1;
uint32_t reserved_31_3 : 29;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_power_modes_channel_t;
typedef union nvg_channel_1_data_u {
uint64_t flat;
struct nvg_channel_1_data_s {
uint32_t perf_per_watt_mode : 1;
uint32_t reserved_31_1 : 31;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_channel_1_data_t;
typedef union nvg_channel_2_data_u
{
uint64_t flat;
struct nvg_channel_2_data_s
{
uint64_t reserved_1_0 : 2;
uint64_t battery_saver_mode : 1;
uint64_t reserved_63_3 : 61;
} bits;
typedef union {
uint64_t flat;
struct nvg_ccplex_cache_control_channel_t {
uint32_t gpu_ways : 5;
uint32_t reserved_7_5 : 3;
uint32_t gpu_only_ways : 5;
uint32_t reserved_31_13 : 19;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_ccplex_cache_control_channel_t;
typedef union nvg_channel_2_data_u {
uint64_t flat;
struct nvg_channel_2_data_s {
uint32_t reserved_1_0 : 2;
uint32_t battery_saver_mode : 1;
uint32_t reserved_31_3 : 29;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_channel_2_data_t;
typedef union
{
uint64_t flat;
struct nvg_wake_time_channel_t {
uint64_t wake_time : 32;
uint64_t reserved_63_32 : 32;
} bits;
typedef union {
uint64_t flat;
struct nvg_wake_time_channel_t {
uint32_t wake_time : 32;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_wake_time_channel_t;
typedef union
{
uint64_t flat;
struct nvg_cstate_info_channel_t {
uint64_t cluster_state : 3;
uint64_t reserved_6_3 : 4;
uint64_t update_cluster : 1;
uint64_t cg_cstate : 3;
uint64_t reserved_14_11 : 4;
uint64_t update_cg : 1;
uint64_t system_cstate : 4;
uint64_t reserved_22_20 : 3;
uint64_t update_system : 1;
uint64_t reserved_30_24 : 7;
uint64_t update_wake_mask : 1;
uint64_t wake_mask : 32;
} bits;
typedef union {
uint64_t flat;
struct nvg_cstate_info_channel_t {
uint32_t cluster_state : 3;
uint32_t reserved_6_3 : 4;
uint32_t update_cluster : 1;
uint32_t cg_cstate : 3;
uint32_t reserved_14_11 : 4;
uint32_t update_cg : 1;
uint32_t system_cstate : 4;
uint32_t reserved_22_20 : 3;
uint32_t update_system : 1;
uint32_t reserved_30_24 : 7;
uint32_t update_wake_mask : 1;
uint32_t wake_mask : 32;
} bits;
} nvg_cstate_info_channel_t;
typedef union
{
uint64_t flat;
struct nvg_lower_bound_channel_t {
uint64_t crossover_value : 32;
uint64_t reserved_63_32 : 32;
} bits;
typedef union {
uint64_t flat;
struct nvg_lower_bound_channel_t {
uint32_t crossover_value : 32;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_lower_bound_channel_t;
typedef union
{
uint64_t flat;
struct nvg_cstate_stat_query_channel_t {
uint64_t unit_id : 4;
uint64_t reserved_15_4 : 12;
uint64_t stat_id : 16;
uint64_t reserved_63_32 : 32;
} bits;
typedef union {
uint64_t flat;
struct nvg_cstate_stat_query_channel_t {
uint32_t unit_id : 4;
uint32_t reserved_15_4 : 12;
uint32_t stat_id : 16;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_cstate_stat_query_channel_t;
typedef union
{
uint64_t flat;
struct nvg_is_sc7_allowed_channel_t {
uint64_t is_sc7_allowed : 1;
uint64_t reserved_63_32 : 63;
} bits;
typedef union {
uint64_t flat;
struct nvg_is_sc7_allowed_channel_t {
uint32_t is_sc7_allowed : 1;
uint32_t reserved_31_1 : 31;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_is_sc7_allowed_channel_t;
typedef union
{
uint64_t flat;
struct nvg_core_online_channel_t {
uint64_t core_id : 4;
uint64_t reserved_63_4 : 60;
} bits;
typedef union {
uint64_t flat;
struct nvg_core_online_channel_t {
uint32_t core_id : 4;
uint32_t reserved_31_4 : 28;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_core_online_channel_t;
typedef union
{
uint64_t flat;
struct nvg_cc3_control_channel_t {
uint64_t freq_req : 8;
uint64_t reserved_30_8 : 23;
uint64_t enable : 1;
uint64_t reserved_63_32 : 32;
} bits;
typedef union {
uint64_t flat;
struct nvg_cc3_control_channel_t {
uint32_t freq_req : 8;
uint32_t reserved_30_8 : 23;
uint32_t enable : 1;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_cc3_control_channel_t;
typedef union
{
uint64_t flat;
struct nvg_update_gsc_channel_t {
uint64_t gsc_enum : 16;
uint64_t reserved_63_16 : 48;
} bits;
} nvg_update_gsc_channel_t;
typedef union
{
uint64_t flat;
struct nvg_cache_inval_channel_t {
uint64_t cache_clean : 1;
uint64_t cache_clean_inval : 1;
uint64_t cache_clean_inval_tr : 1;
uint64_t reserved_63_3 : 61;
} bits;
} nvg_cache_inval_channel_t;
/* GSC type define */
typedef enum {
TEGRA_NVG_GSC_ALL=0,
TEGRA_NVG_GSC_NVDEC=1,
TEGRA_NVG_GSC_WPR1=2,
TEGRA_NVG_GSC_WPR2=3,
TEGRA_NVG_GSC_TSECA=4,
TEGRA_NVG_GSC_TSECB=5,
TEGRA_NVG_GSC_BPMP=6,
TEGRA_NVG_GSC_APE=7,
TEGRA_NVG_GSC_SPE=8,
TEGRA_NVG_GSC_SCE=9,
TEGRA_NVG_GSC_APR=10,
TEGRA_NVG_GSC_TZRAM=11,
TEGRA_NVG_GSC_SE=12,
TEGRA_NVG_GSC_DMCE=13,
TEGRA_NVG_GSC_BPMP_TO_DMCE=14,
TEGRA_NVG_GSC_BPMP_TO_SPE=16,
TEGRA_NVG_GSC_CPU_TZ_TO_BPMP=18,
TEGRA_NVG_GSC_CPU_NS_TO_BPMP=20,
TEGRA_NVG_GSC_IPC_SE_SPE_SCE_BPMP=22,
TEGRA_NVG_GSC_SC7_RESUME_FW=23,
TEGRA_NVG_GSC_VPR_RESIZE=24,
TEGRA_NVG_GSC_RCE=25,
TEGRA_NVG_GSC_CV=26,
TEGRA_NVG_GSC_BO_MTS_PACKAGE=28,
TEGRA_NVG_GSC_BO_MCE_PREBOOT=29,
TEGRA_NVG_GSC_TZ_DRAM_IDX=34,
TEGRA_NVG_GSC_VPR_IDX=35,
} tegra_nvg_gsc_index_t;
typedef enum {
TEGRA_NVG_CROSSOVER_C6 = 0,
TEGRA_NVG_CROSSOVER_CC6 = 1,
TEGRA_NVG_CROSSOVER_CG7 = 2,
} tegra_nvg_crossover_index_t;
#endif // T194_NVG_H
TEGRA_NVG_CHANNEL_UPDATE_GSC_ALL = 0,
TEGRA_NVG_CHANNEL_UPDATE_GSC_NVDEC = 1,
TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR1 = 2,
TEGRA_NVG_CHANNEL_UPDATE_GSC_WPR2 = 3,
TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECA = 4,
TEGRA_NVG_CHANNEL_UPDATE_GSC_TSECB = 5,
TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP = 6,
TEGRA_NVG_CHANNEL_UPDATE_GSC_APE = 7,
TEGRA_NVG_CHANNEL_UPDATE_GSC_SPE = 8,
TEGRA_NVG_CHANNEL_UPDATE_GSC_SCE = 9,
TEGRA_NVG_CHANNEL_UPDATE_GSC_APR = 10,
TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM = 11,
TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_TSEC = 12,
TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_RCE = 13,
TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_MCE = 14,
TEGRA_NVG_CHANNEL_UPDATE_GSC_SE_SC7 = 15,
TEGRA_NVG_CHANNEL_UPDATE_GSC_BPMP_TO_SPE = 16,
TEGRA_NVG_CHANNEL_UPDATE_GSC_RCE = 17,
TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_TZ_TO_BPMP = 18,
TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR1 = 19,
TEGRA_NVG_CHANNEL_UPDATE_GSC_CPU_NS_TO_BPMP = 20,
TEGRA_NVG_CHANNEL_UPDATE_GSC_OEM_SC7 = 21,
TEGRA_NVG_CHANNEL_UPDATE_GSC_IPC_SE_SPE_SCE_BPMP = 22,
TEGRA_NVG_CHANNEL_UPDATE_GSC_SC7_RESUME_FW = 23,
TEGRA_NVG_CHANNEL_UPDATE_GSC_CAMERA_TASKLIST = 24,
TEGRA_NVG_CHANNEL_UPDATE_GSC_XUSB = 25,
TEGRA_NVG_CHANNEL_UPDATE_GSC_CV = 26,
TEGRA_NVG_CHANNEL_UPDATE_GSC_VM_ENCR2 = 27,
TEGRA_NVG_CHANNEL_UPDATE_GSC_HYPERVISOR_SW = 28,
TEGRA_NVG_CHANNEL_UPDATE_GSC_SMMU_PAGETABLES = 29,
TEGRA_NVG_CHANNEL_UPDATE_GSC_30 = 30,
TEGRA_NVG_CHANNEL_UPDATE_GSC_31 = 31,
TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM = 32,
TEGRA_NVG_CHANNEL_UPDATE_GSC_NVLINK = 33,
TEGRA_NVG_CHANNEL_UPDATE_GSC_SBS = 34,
TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR = 35,
TEGRA_NVG_CHANNEL_UPDATE_GSC_LAST_INDEX
} tegra_nvg_channel_update_gsc_gsc_enum_t;
typedef union {
uint64_t flat;
struct nvg_update_ccplex_gsc_channel_t {
uint32_t gsc_enum : 16;
uint32_t reserved_31_16 : 16;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_update_ccplex_gsc_channel_t;
typedef union {
uint64_t flat;
struct nvg_security_config_channel_t {
uint32_t strict_checking_enabled : 1;
uint32_t strict_checking_locked : 1;
uint32_t reserved_31_2 : 30;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_security_config_t;
typedef union {
uint64_t flat;
struct nvg_shutdown_channel_t {
uint32_t reboot : 1;
uint32_t reserved_31_1 : 31;
uint32_t reserved_63_32 : 32;
} bits;
} nvg_shutdown_t;
#endif
plat/nvidia/tegra/soc/t194/drivers/mce/aarch64/nvg_helpers.S
View file @ 530a5cbc
......@@ -10,6 +10,9 @@
.globl nvg_set_request_data
.globl nvg_set_request
.globl nvg_get_result
.globl nvg_cache_clean
.globl nvg_cache_clean_inval
.globl nvg_cache_inval_all
/* void nvg_set_request_data(uint64_t req, uint64_t data) */
func nvg_set_request_data
......@@ -29,3 +32,21 @@ func nvg_get_result
mrs x0, s3_0_c15_c1_3
ret
endfunc nvg_get_result
/* uint64_t nvg_cache_clean(void) */
func nvg_cache_clean
mrs x0, s3_0_c15_c3_5
ret
endfunc nvg_cache_clean
/* uint64_t nvg_cache_clean_inval(void) */
func nvg_cache_clean_inval
mrs x0, s3_0_c15_c3_6
ret
endfunc nvg_cache_clean_inval
/* uint64_t nvg_cache_inval_all(void) */
func nvg_cache_inval_all
mrs x0, s3_0_c15_c3_7
ret
endfunc nvg_cache_inval_all
\ No newline at end of file
plat/nvidia/tegra/soc/t194/drivers/mce/mce.c
View file @ 530a5cbc
......@@ -14,13 +14,26 @@
#include <denver.h>
#include <mce.h>
#include <mce_private.h>
#include <mmio.h>
#include <platform_def.h>
#include <stdbool.h>
#include <string.h>
#include <errno.h>
#include <t194_nvg.h>
#include <tegra_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
/* Handler to check if MCE firmware is supported */
static bool mce_firmware_not_supported(void)
{
bool status;
/* these platforms do not load MCE firmware */
status = tegra_platform_is_linsim() || tegra_platform_is_qt() ||
tegra_platform_is_virt_dev_kit();
return status;
}
/*******************************************************************************
* Common handler for all MCE commands
......@@ -28,16 +41,10 @@
int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
uint64_t arg2)
{
uint64_t ret64 = 0, arg3, arg4, arg5;
int32_t ret = 0;
cpu_context_t *ctx = cm_get_context(NON_SECURE);
gp_regs_t *gp_regs = get_gpregs_ctx(ctx);
assert(ctx);
assert(gp_regs);
switch (cmd) {
case MCE_CMD_ENTER_CSTATE:
case (uint64_t)MCE_CMD_ENTER_CSTATE:
ret = nvg_enter_cstate((uint32_t)arg0, (uint32_t)arg1);
if (ret < 0) {
ERROR("%s: enter_cstate failed(%d)\n", __func__, ret);
......@@ -45,68 +52,15 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
break;
case MCE_CMD_UPDATE_CSTATE_INFO:
/*
* get the parameters required for the update cstate info
* command
*/
arg3 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4));
arg4 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5));
arg5 = read_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6));
/* arg0 cluster
* arg1 ccplex
* arg2 system
* arg3 sys_state_force => T19x not support
* arg4 wake_mask
* arg5 update_wake_mask
*/
nvg_update_cstate_info((uint32_t)arg0, (uint32_t)arg1,
(uint32_t)arg2, (uint32_t)arg4, (uint8_t)arg5);
write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X4), (arg3));
write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X5), (arg4));
write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X6), (arg5));
break;
case MCE_CMD_UPDATE_CROSSOVER_TIME:
ret = nvg_update_crossover_time((uint32_t)arg0, (uint32_t)arg1);
if (ret < 0) {
ERROR("%s: update_crossover_time failed(%d)\n",
__func__, ret);
}
break;
case MCE_CMD_READ_CSTATE_STATS:
ret64 = nvg_get_cstate_stat_query_value();
/* update context to return cstate stats value */
write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64));
write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64));
break;
case MCE_CMD_WRITE_CSTATE_STATS:
ret = nvg_set_cstate_stat_query_value(arg0);
break;
case MCE_CMD_IS_SC7_ALLOWED:
case (uint64_t)MCE_CMD_IS_SC7_ALLOWED:
ret = nvg_is_sc7_allowed();
if (ret < 0) {
ERROR("%s: is_sc7_allowed failed(%d)\n", __func__, ret);
break;
}
/* update context to return SC7 status value */
write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), ((uint64_t)ret));
write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X3), ((uint64_t)ret));
break;
case MCE_CMD_ONLINE_CORE:
case (uint64_t)MCE_CMD_ONLINE_CORE:
ret = nvg_online_core((uint32_t)arg0);
if (ret < 0) {
ERROR("%s: online_core failed(%d)\n", __func__, ret);
......@@ -114,55 +68,9 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
break;
case MCE_CMD_CC3_CTRL:
ret = nvg_cc3_ctrl((uint32_t)arg0, (uint8_t)arg2);
if (ret < 0) {
ERROR("%s: cc3_ctrl failed(%d)\n", __func__, ret);
}
break;
case MCE_CMD_READ_VERSIONS:
/* get the MCE firmware version */
ret64 = nvg_get_version();
/*
* version = minor(63:32) | major(31:0). Update context
* to return major and minor version number.
*/
write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X1), (ret64 & (uint64_t)0xFFFF));
write_ctx_reg(gp_regs, ((uint64_t)CTX_GPREG_X2), (ret64 >> 32));
break;
case MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
ret = nvg_roc_clean_cache_trbits();
if (ret < 0) {
ERROR("%s: flush cache_trbits failed(%d)\n", __func__,
ret);
}
break;
case MCE_CMD_ROC_FLUSH_CACHE:
ret = nvg_roc_flush_cache();
if (ret < 0) {
ERROR("%s: flush cache failed(%d)\n", __func__, ret);
}
break;
case MCE_CMD_ROC_CLEAN_CACHE:
ret = nvg_roc_clean_cache();
if (ret < 0) {
ERROR("%s: clean cache failed(%d)\n", __func__, ret);
}
break;
default:
ERROR("unknown MCE command (%llu)\n", cmd);
ret = EINVAL;
ret = -EINVAL;
break;
}
......@@ -174,7 +82,18 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
******************************************************************************/
int32_t mce_update_gsc_videomem(void)
{
return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_VPR_IDX);
int32_t ret;
/*
* MCE firmware is not running on simulation platforms.
*/
if (mce_firmware_not_supported()) {
ret = -EINVAL;
} else {
ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR);
}
return ret;
}
/*******************************************************************************
......@@ -182,7 +101,18 @@ int32_t mce_update_gsc_videomem(void)
******************************************************************************/
int32_t mce_update_gsc_tzdram(void)
{
return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZ_DRAM_IDX);
int32_t ret;
/*
* MCE firmware is not running on simulation platforms.
*/
if (mce_firmware_not_supported()) {
ret = -EINVAL;
} else {
ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZ_DRAM);
}
return ret;
}
/*******************************************************************************
......@@ -190,7 +120,18 @@ int32_t mce_update_gsc_tzdram(void)
******************************************************************************/
int32_t mce_update_gsc_tzram(void)
{
return nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_GSC_TZRAM);
int32_t ret;
/*
* MCE firmware is not running on simulation platforms.
*/
if (mce_firmware_not_supported()) {
ret = -EINVAL;
} else {
ret = nvg_update_ccplex_gsc((uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_TZRAM);
}
return ret;
}
/*******************************************************************************
......@@ -215,9 +156,7 @@ void mce_verify_firmware_version(void)
/*
* MCE firmware is not running on simulation platforms.
*/
if ((tegra_platform_is_linsim() == 1U) ||
(tegra_platform_is_virt_dev_kit() == 1U) ||
(tegra_platform_is_qt() == 1U)) {
if (mce_firmware_not_supported()) {
return;
}
......@@ -229,8 +168,8 @@ void mce_verify_firmware_version(void)
minor = (uint32_t)version;
major = (uint32_t)(version >> 32);
INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor,
0, 0);
INFO("MCE Version - HW=%u:%u, SW=%u:%u\n", major, minor,
TEGRA_NVG_VERSION_MAJOR, TEGRA_NVG_VERSION_MINOR);
/*
* Verify that the MCE firmware version and the interface header
......@@ -246,3 +185,53 @@ void mce_verify_firmware_version(void)
panic();
}
}
/*******************************************************************************
* Handler to enable the strict checking mode
******************************************************************************/
void mce_enable_strict_checking(void)
{
uint64_t sctlr = read_sctlr_el3();
int32_t ret = 0;
if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
/*
* Step1: TZ-DRAM and TZRAM should be setup before the MMU is
* enabled.
*
* The common code makes sure that TZDRAM/TZRAM are already
* enabled before calling into this handler. If this is not the
* case, the following sequence must be executed before moving
* on to step 2.
*
* tlbialle1is();
* tlbialle3is();
* dsbsy();
* isb();
*
*/
if ((sctlr & (uint64_t)SCTLR_M_BIT) == (uint64_t)SCTLR_M_BIT) {
tlbialle1is();
tlbialle3is();
dsbsy();
isb();
}
/*
* Step2: SCF flush - Clean and invalidate caches and clear the
* TR-bits
*/
ret = nvg_roc_clean_cache_trbits();
if (ret < 0) {
ERROR("%s: flush cache_trbits failed(%d)\n", __func__,
ret);
return;
}
/*
* Step3: Issue the SECURITY_CONFIG request to MCE to enable
* strict checking mode.
*/
nvg_enable_strict_checking_mode();
}
}
plat/nvidia/tegra/soc/t194/drivers/mce/nvg.c
View file @ 530a5cbc
......@@ -13,11 +13,10 @@
#include <mce_private.h>
#include <platform_def.h>
#include <t194_nvg.h>
#include <tegra_private.h>
extern void nvg_set_request_data(uint64_t req, uint64_t data);
extern void nvg_set_request(uint64_t req);
extern uint64_t nvg_get_result(void);
#define ID_AFR0_EL1_CACHE_OPS_SHIFT 12
#define ID_AFR0_EL1_CACHE_OPS_MASK 0xFU
/*
* Reports the major and minor version of this interface.
*
......@@ -26,7 +25,7 @@ extern uint64_t nvg_get_result(void);
*/
uint64_t nvg_get_version(void)
{
nvg_set_request(TEGRA_NVG_CHANNEL_VERSION);
nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_VERSION);
return (uint64_t)nvg_get_result();
}
......@@ -38,7 +37,7 @@ uint64_t nvg_get_version(void)
*/
int32_t nvg_enable_power_perf_mode(void)
{
nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 1U);
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 1U);
return 0;
}
......@@ -50,7 +49,7 @@ int32_t nvg_enable_power_perf_mode(void)
*/
int32_t nvg_disable_power_perf_mode(void)
{
nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_PERF, 0U);
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_PERF, 0U);
return 0;
}
......@@ -62,7 +61,7 @@ int32_t nvg_disable_power_perf_mode(void)
*/
int32_t nvg_enable_power_saver_modes(void)
{
nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 1U);
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 1U);
return 0;
}
......@@ -74,7 +73,7 @@ int32_t nvg_enable_power_saver_modes(void)
*/
int32_t nvg_disable_power_saver_modes(void)
{
nvg_set_request_data(TEGRA_NVG_CHANNEL_POWER_MODES, 0U);
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_POWER_MODES, 0U);
return 0;
}
......@@ -88,7 +87,7 @@ int32_t nvg_disable_power_saver_modes(void)
void nvg_set_wake_time(uint32_t wake_time)
{
/* time (TSC ticks) until the core is expected to get a wake event */
nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time);
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, (uint64_t)wake_time);
}
/*
......@@ -97,7 +96,7 @@ void nvg_set_wake_time(uint32_t wake_time)
*
* NVGDATA[0:2]: SW(RW), CLUSTER_CSTATE
* NVGDATA[7]: SW(W), update cluster flag
* NVGDATA[8:9]: SW(RW), CG_CSTATE
* NVGDATA[8:10]: SW(RW), CG_CSTATE
* NVGDATA[15]: SW(W), update ccplex flag
* NVGDATA[16:19]: SW(RW), SYSTEM_CSTATE
* NVGDATA[23]: SW(W), update system flag
......@@ -136,77 +135,7 @@ void nvg_update_cstate_info(uint32_t cluster, uint32_t ccplex,
val |= ((uint64_t)wake_mask & CSTATE_WAKE_MASK_CLEAR) << CSTATE_WAKE_MASK_SHIFT;
/* set the updated cstate info */
nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
}
/*
* Indices gives MTS the crossover point in TSC ticks for when it becomes
* no longer viable to enter the named state
*
* Type 0 : NVGDATA[0:31]: C6 Lower bound
* Type 1 : NVGDATA[0:31]: CC6 Lower bound
* Type 2 : NVGDATA[0:31]: CG7 Lower bound
*/
int32_t nvg_update_crossover_time(uint32_t type, uint32_t time)
{
int32_t ret = 0;
switch (type) {
case TEGRA_NVG_CROSSOVER_C6:
nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_C6_LOWER_BOUND,
(uint64_t)time);
break;
case TEGRA_NVG_CROSSOVER_CC6:
nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CC6_LOWER_BOUND,
(uint64_t)time);
break;
case TEGRA_NVG_CROSSOVER_CG7:
nvg_set_request_data(TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND,
(uint64_t)time);
break;
default:
ERROR("%s: unknown crossover type (%d)\n", __func__, type);
ret = EINVAL;
break;
}
return ret;
}
/*
* These NVG calls allow ARM SW to access CSTATE statistical information
*
* NVGDATA[0:3]: SW(RW) Core/cluster/cg id
* NVGDATA[16:31]: SW(RW) Stat id
*/
int32_t nvg_set_cstate_stat_query_value(uint64_t data)
{
int32_t ret = 0;
/* sanity check stat id */
if (data > (uint64_t)NVG_STAT_QUERY_C7_RESIDENCY_SUM) {
ERROR("%s: unknown stat id (%d)\n", __func__, (uint32_t)data);
ret = EINVAL;
} else {
nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST, data);
}
return ret;
}
/*
* The read-only value associated with the CSTATE_STAT_QUERY_REQUEST
*
* NVGDATA[0:63]: SW(R) Stat count
*/
uint64_t nvg_get_cstate_stat_query_value(void)
{
nvg_set_request(TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE);
return (uint64_t)nvg_get_result();
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
}
/*
......@@ -217,7 +146,7 @@ uint64_t nvg_get_cstate_stat_query_value(void)
int32_t nvg_is_sc7_allowed(void)
{
/* issue command to check if SC7 is allowed */
nvg_set_request(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED);
nvg_set_request((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED);
/* 1 = SC7 allowed, 0 = SC7 not allowed */
return (int32_t)nvg_get_result();
......@@ -239,42 +168,13 @@ int32_t nvg_online_core(uint32_t core)
ret = EINVAL;
} else {
/* get a core online */
nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE,
(uint64_t)core & MCE_CORE_ID_MASK);
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE,
(uint64_t)core & MCE_CORE_ID_MASK);
}
return ret;
}
/*
* Enables and controls the voltage/frequency hint for CC3. CC3 is disabled
* by default.
*
* NVGDATA[7:0] SW(RW) frequency request
* NVGDATA[31:31] SW(RW) enable bit
*/
int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable)
{
uint64_t val = 0;
/*
* If the enable bit is cleared, Auto-CC3 will be disabled by setting
* the SW visible frequency request registers for all non
* floorswept cores valid independent of StandbyWFI and disabling
* the IDLE frequency request register. If set, Auto-CC3
* will be enabled by setting the ARM SW visible frequency
* request registers for all non floorswept cores to be enabled by
* StandbyWFI or the equivalent signal, and always keeping the IDLE
* frequency request register enabled.
*/
if (enable != 0U) {
val = ((uint64_t)freq & MCE_AUTO_CC3_FREQ_MASK) | MCE_AUTO_CC3_ENABLE_BIT;
}
nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, val);
return 0;
}
/*
* MC GSC (General Security Carveout) register values are expected to be
* changed by TrustZone ARM code after boot.
......@@ -283,14 +183,14 @@ int32_t nvg_cc3_ctrl(uint32_t freq, uint8_t enable)
*/
int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
{
int32_t ret = 0;
int32_t ret;
/* sanity check GSC ID */
if (gsc_idx > (uint32_t)TEGRA_NVG_GSC_VPR_IDX) {
ERROR("%s: unknown gsc_idx (%d)\n", __func__, gsc_idx);
if (gsc_idx > (uint32_t)TEGRA_NVG_CHANNEL_UPDATE_GSC_VPR) {
ERROR("%s: unknown gsc_idx (%u)\n", __func__, gsc_idx);
ret = EINVAL;
} else {
nvg_set_request_data(TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC,
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_UPDATE_CCPLEX_GSC,
(uint64_t)gsc_idx);
}
......@@ -299,41 +199,62 @@ int32_t nvg_update_ccplex_gsc(uint32_t gsc_idx)
/*
* Cache clean operation for all CCPLEX caches.
*
* NVGDATA[0] cache_clean
*/
int32_t nvg_roc_clean_cache(void)
{
nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
(uint64_t)CACHE_CLEAN_SET);
int32_t ret = 0;
return 0;
/* check if cache flush through mts is supported */
if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
if (nvg_cache_clean() == 0U) {
ERROR("%s: failed\n", __func__);
ret = EINVAL;
}
} else {
ret = EINVAL;
}
return ret;
}
/*
* Cache clean and invalidate operation for all CCPLEX caches.
*
* NVGDATA[1] cache_clean_inval
*/
int32_t nvg_roc_flush_cache(void)
{
nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
(uint64_t)CACHE_CLEAN_INVAL_SET);
int32_t ret = 0;
return 0;
/* check if cache flush through mts is supported */
if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
if (nvg_cache_clean_inval() == 0U) {
ERROR("%s: failed\n", __func__);
ret = EINVAL;
}
} else {
ret = EINVAL;
}
return ret;
}
/*
* Cache clean and invalidate, clear TR-bit operation for all CCPLEX caches.
*
* NVGDATA[2] cache_clean_inval_tr
*/
int32_t nvg_roc_clean_cache_trbits(void)
{
nvg_set_request_data(TEGRA_NVG_CHANNEL_CCPLEX_CACHE_INVAL,
(uint64_t)CACHE_CLEAN_INVAL_TR_SET);
int32_t ret = 0;
return 0;
/* check if cache flush through mts is supported */
if (((read_id_afr0_el1() >> ID_AFR0_EL1_CACHE_OPS_SHIFT) &
ID_AFR0_EL1_CACHE_OPS_MASK) == 1U) {
if (nvg_cache_inval_all() == 0U) {
ERROR("%s: failed\n", __func__);
ret = EINVAL;
}
} else {
ret = EINVAL;
}
return ret;
}
/*
......@@ -342,6 +263,7 @@ int32_t nvg_roc_clean_cache_trbits(void)
int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
{
int32_t ret = 0;
uint64_t val = 0ULL;
/* check for allowed power state */
if ((state != (uint32_t)TEGRA_NVG_CORE_C0) &&
......@@ -356,8 +278,22 @@ int32_t nvg_enter_cstate(uint32_t state, uint32_t wake_time)
nvg_set_wake_time(wake_time);
/* set the core cstate */
write_actlr_el1(state);
val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
write_actlr_el1(val | (uint64_t)state);
}
return ret;
}
/*
* Enable strict checking mode
*
* NVGDATA[3] strict_check ON + lock
*/
void nvg_enable_strict_checking_mode(void)
{
uint64_t params = (uint64_t)(STRICT_CHECKING_ENABLED_SET |
STRICT_CHECKING_LOCKED_SET);
nvg_set_request_data(TEGRA_NVG_CHANNEL_SECURITY_CONFIG, params);
}
plat/nvidia/tegra/soc/t194/drivers/se/se.c 0 → 100644
View file @ 530a5cbc
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <stdbool.h>
#include <arch_helpers.h>
#include <common/debug.h>
#include <drivers/delay_timer.h>
#include <lib/mmio.h>
#include <lib/psci/psci.h>
#include <tegra_platform.h>
#include "se_private.h"
/*******************************************************************************
* Constants and Macros
******************************************************************************/
#define ERR_STATUS_SW_CLEAR U(0xFFFFFFFF)
#define INT_STATUS_SW_CLEAR U(0xFFFFFFFF)
#define MAX_TIMEOUT_MS U(100) /* Timeout in 100ms */
#define NUM_SE_REGS_TO_SAVE U(4)
/*******************************************************************************
* Data structure and global variables
******************************************************************************/
static uint32_t se_regs[NUM_SE_REGS_TO_SAVE];
/*
* Check that SE operation has completed after kickoff.
*
* This function is invoked after an SE operation has been started,
* and it checks the following conditions:
*
* 1. SE_STATUS = IDLE
* 2. AHB bus data transfer is complete.
* 3. SE_ERR_STATUS is clean.
*/
static bool tegra_se_is_operation_complete(void)
{
uint32_t val = 0, timeout = 0, sha_status, aes_status;
int32_t ret = 0;
bool se_is_busy, txn_has_errors, txn_successful;
/*
* Poll the status register to check if the operation
* completed.
*/
do {
val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS);
se_is_busy = !!(val & CTX_SAVE_AUTO_SE_BUSY);
/* sleep until SE finishes */
if (se_is_busy) {
mdelay(1);
timeout++;
}
} while (se_is_busy && (timeout < MAX_TIMEOUT_MS));
/* any transaction errors? */
txn_has_errors = (tegra_se_read_32(SHA_ERR_STATUS) != 0U) ||
(tegra_se_read_32(AES0_ERR_STATUS) != 0U);
/* transaction successful? */
sha_status = tegra_se_read_32(SHA_INT_STATUS) & SHA_SE_OP_DONE;
aes_status = tegra_se_read_32(AES0_INT_STATUS) & AES0_SE_OP_DONE;
txn_successful = (sha_status == SHA_SE_OP_DONE) &&
(aes_status == AES0_SE_OP_DONE);
if ((timeout == MAX_TIMEOUT_MS) || txn_has_errors || !txn_successful) {
ERROR("%s: Atomic context save operation failed!\n",
__func__);
ret = -ECANCELED;
}
return (ret == 0);
}
/*
* Wait for SE engine to be idle and clear any pending interrupts, before
* starting the next SE operation.
*/
static bool tegra_se_is_ready(void)
{
int32_t ret = 0;
uint32_t val = 0, timeout = 0;
bool se_is_ready;
/* Wait for previous operation to finish */
do {
val = tegra_se_read_32(CTX_SAVE_AUTO_STATUS);
se_is_ready = (val == CTX_SAVE_AUTO_SE_READY);
/* sleep until SE is ready */
if (!se_is_ready) {
mdelay(1);
timeout++;
}
} while (!se_is_ready && (timeout < MAX_TIMEOUT_MS));
if (timeout == MAX_TIMEOUT_MS) {
ERROR("%s: SE is not ready!\n", __func__);
ret = -ETIMEDOUT;
}
/* Clear any pending interrupts from previous operation */
tegra_se_write_32(AES0_INT_STATUS, INT_STATUS_SW_CLEAR);
tegra_se_write_32(AES1_INT_STATUS, INT_STATUS_SW_CLEAR);
tegra_se_write_32(RSA_INT_STATUS, INT_STATUS_SW_CLEAR);
tegra_se_write_32(SHA_INT_STATUS, INT_STATUS_SW_CLEAR);
/* Clear error status for each engine seen from current port */
tegra_se_write_32(AES0_ERR_STATUS, ERR_STATUS_SW_CLEAR);
tegra_se_write_32(AES1_ERR_STATUS, ERR_STATUS_SW_CLEAR);
tegra_se_write_32(RSA_ERR_STATUS, ERR_STATUS_SW_CLEAR);
tegra_se_write_32(SHA_ERR_STATUS, ERR_STATUS_SW_CLEAR);
return (ret == 0);
}
/*
* During System Suspend, this handler triggers the hardware context
* save operation.
*/
static int32_t tegra_se_save_context(void)
{
int32_t ret = -ECANCELED;
/*
* 1. Ensure all SE Driver including RNG1/PKA1 are shut down.
* TSEC/R5s are powergated/idle. All tasks on SE1~SE4, RNG1,
* PKA1 are wrapped up. SE0 is ready for use.
* 2. Clear interrupt/error in SE0 status register.
* 3. Scrub SE0 register to avoid false failure for illegal
* configuration. Probably not needed, dependent on HW
* implementation.
* 4. Check SE is ready for HW CTX_SAVE by polling
* SE_CTX_SAVE_AUTO_STATUS.SE_READY.
*
* Steps 1-4 are executed by tegra_se_is_ready().
*
* 5. Issue context save command.
* 6. Check SE is busy with CTX_SAVE, the command in step5 was not
* dropped for ongoing traffic in any of SE port/engine.
* 7. Poll SE register or wait for SE APB interrupt for task completion
* a. Polling: Read SE_CTX_SAVE_AUTO_STATUS.BUSY till it reports IDLE
* b. Interrupt: After receiving interrupt from SE APB, read
* SE_CTX_SAVE_AUTO_STATUS.BUSY till it reports IDLE.
* 8. Check AES0 and SHA ERR_STATUS to ensure no error case.
* 9. Check AES0 and SHA INT_STATUS to ensure operation has successfully
* completed.
*
* Steps 6-9 are executed by tegra_se_is_operation_complete().
*/
if (tegra_se_is_ready()) {
/* Issue context save command */
tegra_se_write_32(AES0_OPERATION, SE_OP_CTX_SAVE);
/* Wait for operation to finish */
if (tegra_se_is_operation_complete()) {
ret = 0;
}
}
return ret;
}
/*
* Handler to power down the SE hardware blocks - SE, RNG1 and PKA1. This
* needs to be called only during System Suspend.
*/
int32_t tegra_se_suspend(void)
{
int32_t ret = 0;
/* save SE registers */
se_regs[0] = mmio_read_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT);
se_regs[1] = mmio_read_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL);
se_regs[2] = mmio_read_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT);
se_regs[3] = mmio_read_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT);
/* Save SE context. The BootROM restores it during System Resume */
ret = tegra_se_save_context();
if (ret != 0) {
ERROR("%s: context save failed (%d)\n", __func__, ret);
}
return ret;
}
/*
* Handler to power up the SE hardware block(s) during System Resume.
*/
void tegra_se_resume(void)
{
/*
* When TZ takes over after System Resume, TZ should first reconfigure
* SE_MUTEX_WATCHDOG_NS_LIMIT, PKA1_MUTEX_WATCHDOG_NS_LIMIT,
* RNG1_MUTEX_WATCHDOG_NS_LIMIT and SE_ENTROPY_SRC_AGE_CTRL before
* other operations.
*/
mmio_write_32(TEGRA_SE0_BASE + SE0_MUTEX_WATCHDOG_NS_LIMIT, se_regs[0]);
mmio_write_32(TEGRA_SE0_BASE + SE0_AES0_ENTROPY_SRC_AGE_CTRL, se_regs[1]);
mmio_write_32(TEGRA_RNG1_BASE + RNG1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[2]);
mmio_write_32(TEGRA_PKA1_BASE + PKA1_MUTEX_WATCHDOG_NS_LIMIT, se_regs[3]);
}
plat/nvidia/tegra/soc/t194/drivers/se/se_private.h 0 → 100644
View file @ 530a5cbc
/*
* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef __SE_PRIVATE_H__
#define __SE_PRIVATE_H__
#include <lib/utils_def.h>
/* SE0_INT_ENABLE_0 */
#define SE0_INT_ENABLE U(0x88)
#define SE0_DISABLE_ALL_INT U(0x0)
/* SE0_INT_STATUS_0 */
#define SE0_INT_STATUS U(0x8C)
#define SE0_CLEAR_ALL_INT_STATUS U(0x3F)
/* SE0_SHA_INT_STATUS_0 */
#define SHA_INT_STATUS U(0x184)
#define SHA_SE_OP_DONE (U(1) << 4)
/* SE0_SHA_ERR_STATUS_0 */
#define SHA_ERR_STATUS U(0x18C)
/* SE0_AES0_INT_STATUS_0 */
#define AES0_INT_STATUS U(0x2F0)
#define AES0_SE_OP_DONE (U(1) << 4)
/* SE0_AES0_ERR_STATUS_0 */
#define AES0_ERR_STATUS U(0x2F8)
/* SE0_AES1_INT_STATUS_0 */
#define AES1_INT_STATUS U(0x4F0)
/* SE0_AES1_ERR_STATUS_0 */
#define AES1_ERR_STATUS U(0x4F8)
/* SE0_RSA_INT_STATUS_0 */
#define RSA_INT_STATUS U(0x758)
/* SE0_RSA_ERR_STATUS_0 */
#define RSA_ERR_STATUS U(0x760)
/* SE0_AES0_OPERATION_0 */
#define AES0_OPERATION U(0x238)
#define OP_MASK_BITS U(0x7)
#define SE_OP_CTX_SAVE U(0x3)
/* SE0_AES0_CTX_SAVE_CONFIG_0 */
#define CTX_SAVE_CONFIG U(0x2D4)
/* SE0_AES0_CTX_SAVE_AUTO_STATUS_0 */
#define CTX_SAVE_AUTO_STATUS U(0x300)
#define CTX_SAVE_AUTO_SE_READY U(0xFF)
#define CTX_SAVE_AUTO_SE_BUSY (U(0x1) << 31)
/* SE0_AES0_CTX_SAVE_AUTO_CTRL_0 */
#define CTX_SAVE_AUTO_CTRL U(0x304)
#define SE_CTX_SAVE_AUTO_EN (U(0x1) << 0)
#define SE_CTX_SAVE_AUTO_LOCK_EN (U(0x1) << 1)
/* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_0 */
#define CTX_SAVE_AUTO_START_ADDR U(0x308)
/* SE0_AES0_CTX_SAVE_AUTO_START_ADDR_HI_0 */
#define CTX_SAVE_AUTO_START_ADDR_HI U(0x30C)
/*******************************************************************************
* Inline functions definition
******************************************************************************/
static inline uint32_t tegra_se_read_32(uint32_t offset)
{
return mmio_read_32(TEGRA_SE0_BASE + offset);
}
static inline void tegra_se_write_32(uint32_t offset, uint32_t val)
{
mmio_write_32(TEGRA_SE0_BASE + offset, val);
}
#endif /* __SE_PRIVATE_H__ */
plat/nvidia/tegra/soc/t194/plat_psci_handlers.c
View file @ 530a5cbc
......@@ -5,58 +5,65 @@
*/
#include <arch.h>
#include <arch_helpers.h>
#include <assert.h>
#include <stdbool.h>
#include <string.h>
#include <arch_helpers.h>
#include <common/bl_common.h>
#include <context.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <common/debug.h>
#include <context.h>
#include <denver.h>
#include <lib/el3_runtime/context_mgmt.h>
#include <lib/psci/psci.h>
#include <mce.h>
#include <mce_private.h>
#include <plat/common/platform.h>
#include <lib/psci/psci.h>
#include <se.h>
#include <smmu.h>
#include <string.h>
#include <tegra_private.h>
#include <t194_nvg.h>
#include <tegra194_private.h>
#include <tegra_platform.h>
#include <tegra_private.h>
extern void prepare_core_pwr_dwn(void);
extern uint8_t tegra_fake_system_suspend;
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
extern void tegra186_cpu_reset_handler(void);
extern uint32_t __tegra186_cpu_reset_handler_data,
__tegra186_cpu_reset_handler_end;
extern void tegra194_cpu_reset_handler(void);
extern uint32_t __tegra194_cpu_reset_handler_data,
__tegra194_cpu_reset_handler_end;
/* TZDRAM offset for saving SMMU context */
#define TEGRA186_SMMU_CTX_OFFSET 16
#endif
#define TEGRA194_SMMU_CTX_OFFSET 16U
/* state id mask */
#define TEGRA186_STATE_ID_MASK 0xF
#define TEGRA194_STATE_ID_MASK 0xFU
/* constants to get power state's wake time */
#define TEGRA186_WAKE_TIME_MASK 0x0FFFFFF0
#define TEGRA186_WAKE_TIME_SHIFT 4
#define TEGRA194_WAKE_TIME_MASK 0x0FFFFFF0U
#define TEGRA194_WAKE_TIME_SHIFT 4U
/* default core wake mask for CPU_SUSPEND */
#define TEGRA186_CORE_WAKE_MASK 0x180c
/* context size to save during system suspend */
#define TEGRA186_SE_CONTEXT_SIZE 3
#define TEGRA194_CORE_WAKE_MASK 0x180cU
static uint32_t se_regs[TEGRA186_SE_CONTEXT_SIZE];
static struct t18x_psci_percpu_data {
unsigned int wake_time;
} __aligned(CACHE_WRITEBACK_GRANULE) percpu_data[PLATFORM_CORE_COUNT];
static struct t19x_psci_percpu_data {
uint32_t wake_time;
} __aligned(CACHE_WRITEBACK_GRANULE) t19x_percpu_data[PLATFORM_CORE_COUNT];
int32_t tegra_soc_validate_power_state(unsigned int power_state,
/*
* tegra_fake_system_suspend acts as a boolean var controlling whether
* we are going to take fake system suspend code or normal system suspend code
* path. This variable is set inside the sip call handlers, when the kernel
* requests an SIP call to set the suspend debug flags.
*/
bool tegra_fake_system_suspend;
int32_t tegra_soc_validate_power_state(uint32_t power_state,
psci_power_state_t *req_state)
{
int state_id = psci_get_pstate_id(power_state) & TEGRA186_STATE_ID_MASK;
int cpu = plat_my_core_pos();
uint8_t state_id = (uint8_t)psci_get_pstate_id(power_state) &
TEGRA194_STATE_ID_MASK;
uint32_t cpu = plat_my_core_pos();
int32_t ret = PSCI_E_SUCCESS;
/* save the core wake time (in TSC ticks)*/
percpu_data[cpu].wake_time = (power_state & TEGRA186_WAKE_TIME_MASK)
<< TEGRA186_WAKE_TIME_SHIFT;
t19x_percpu_data[cpu].wake_time = (power_state & TEGRA194_WAKE_TIME_MASK)
<< TEGRA194_WAKE_TIME_SHIFT;
/*
* Clean percpu_data[cpu] to DRAM. This needs to be done to ensure that
......@@ -65,8 +72,8 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
* from DRAM in that function, because the L2 cache is not flushed
* unless the cluster is entering CC6/CC7.
*/
clean_dcache_range((uint64_t)&percpu_data[cpu],
sizeof(percpu_data[cpu]));
clean_dcache_range((uint64_t)&t19x_percpu_data[cpu],
sizeof(t19x_percpu_data[cpu]));
/* Sanity check the requested state id */
switch (state_id) {
......@@ -81,148 +88,195 @@ int32_t tegra_soc_validate_power_state(unsigned int power_state,
default:
ERROR("%s: unsupported state id (%d)\n", __func__, state_id);
return PSCI_E_INVALID_PARAMS;
ret = PSCI_E_INVALID_PARAMS;
break;
}
return PSCI_E_SUCCESS;
return ret;
}
int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
{
const plat_local_state_t *pwr_domain_state;
unsigned int stateid_afflvl0, stateid_afflvl2;
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
uint8_t stateid_afflvl0, stateid_afflvl2;
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t smmu_ctx_base;
#endif
uint32_t val;
mce_cstate_info_t cstate_info = { 0 };
mce_cstate_info_t sc7_cstate_info = {
.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6,
.system = (uint32_t)TEGRA_NVG_SYSTEM_SC7,
.system_state_force = 1U,
.update_wake_mask = 1U,
};
uint32_t cpu = plat_my_core_pos();
int32_t ret = 0;
/* get the state ID */
pwr_domain_state = target_state->pwr_domain_state;
stateid_afflvl0 = pwr_domain_state[MPIDR_AFFLVL0] &
TEGRA186_STATE_ID_MASK;
TEGRA194_STATE_ID_MASK;
stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
TEGRA186_STATE_ID_MASK;
TEGRA194_STATE_ID_MASK;
if ((stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ||
(stateid_afflvl0 == PSTATE_ID_CORE_POWERDN)) {
/* Enter CPU idle/powerdown */
val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
(uint32_t)TEGRA_NVG_CORE_C6 : (uint32_t)TEGRA_NVG_CORE_C7;
ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val,
percpu_data[cpu].wake_time, 0);
assert(ret == 0);
} else if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
/* save SE registers */
se_regs[0] = mmio_read_32(TEGRA_SE0_BASE +
SE_MUTEX_WATCHDOG_NS_LIMIT);
se_regs[1] = mmio_read_32(TEGRA_RNG1_BASE +
RNG_MUTEX_WATCHDOG_NS_LIMIT);
se_regs[2] = mmio_read_32(TEGRA_PKA1_BASE +
PKA_MUTEX_WATCHDOG_NS_LIMIT);
/* save 'Secure Boot' Processor Feature Config Register */
val = mmio_read_32(TEGRA_MISC_BASE + MISCREG_PFCFG);
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV6, val);
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_SECURE_BOOTP_FCFG, val);
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
/* save SMMU context */
smmu_ctx_base = params_from_bl2->tzdram_base +
((uintptr_t)&__tegra186_cpu_reset_handler_data -
(uintptr_t)tegra186_cpu_reset_handler) +
TEGRA186_SMMU_CTX_OFFSET;
tegra194_get_smmu_ctx_offset();
tegra_smmu_save_context((uintptr_t)smmu_ctx_base);
#else
tegra_smmu_save_context(0);
#endif
if (tegra_fake_system_suspend == 0U) {
/*
* Suspend SE, RNG1 and PKA1 only on silcon and fpga,
* since VDK does not support atomic se ctx save
*/
if (tegra_platform_is_silicon() || tegra_platform_is_fpga()) {
ret = tegra_se_suspend();
assert(ret == 0);
}
if (!tegra_fake_system_suspend) {
/* Prepare for system suspend */
cstate_info.cluster = TEGRA_NVG_CLUSTER_CC6;
cstate_info.system = TEGRA_NVG_SYSTEM_SC7;
cstate_info.system_state_force = 1;
cstate_info.update_wake_mask = 1;
mce_update_cstate_info(&cstate_info);
mce_update_cstate_info(&sc7_cstate_info);
do {
val = mce_command_handler(
MCE_CMD_IS_SC7_ALLOWED,
TEGRA_NVG_CORE_C7,
val = (uint32_t)mce_command_handler(
(uint32_t)MCE_CMD_IS_SC7_ALLOWED,
(uint32_t)TEGRA_NVG_CORE_C7,
MCE_CORE_SLEEP_TIME_INFINITE,
0);
} while (val == 0);
/* Instruct the MCE to enter system suspend state */
(void)mce_command_handler(MCE_CMD_ENTER_CSTATE,
TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0);
0U);
} while (val == 0U);
/* Instruct the MCE to enter system suspend state */
ret = mce_command_handler(
(uint64_t)MCE_CMD_ENTER_CSTATE,
(uint64_t)TEGRA_NVG_CORE_C7,
MCE_CORE_SLEEP_TIME_INFINITE,
0U);
assert(ret == 0);
/* set system suspend state for house-keeping */
tegra194_set_system_suspend_entry();
}
} else {
; /* do nothing */
}
return PSCI_E_SUCCESS;
}
/*******************************************************************************
* Platform handler to calculate the proper target power level at the
* specified affinity level
* Helper function to check if this is the last ON CPU in the cluster
******************************************************************************/
plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
const plat_local_state_t *states,
unsigned int ncpu)
static bool tegra_last_on_cpu_in_cluster(const plat_local_state_t *states,
uint32_t ncpu)
{
plat_local_state_t target = *states;
int cluster_powerdn = 1;
int core_pos = read_mpidr() & MPIDR_CPU_MASK;
plat_local_state_t target;
bool last_on_cpu = true;
uint32_t num_cpus = ncpu, pos = 0;
do {
target = states[pos];
if (target != PLAT_MAX_OFF_STATE) {
last_on_cpu = false;
}
--num_cpus;
pos++;
} while (num_cpus != 0U);
/* get the current core's power state */
target = *(states + core_pos);
return last_on_cpu;
}
/*******************************************************************************
* Helper function to get target power state for the cluster
******************************************************************************/
static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *states,
uint32_t ncpu)
{
uint32_t core_pos = (uint32_t)read_mpidr() & (uint32_t)MPIDR_CPU_MASK;
plat_local_state_t target = states[core_pos];
mce_cstate_info_t cstate_info = { 0 };
/* CPU suspend */
if (lvl == MPIDR_AFFLVL1 && target == PSTATE_ID_CORE_POWERDN) {
if (target == PSTATE_ID_CORE_POWERDN) {
/* Program default wake mask */
/* Check if CCx state is allowed. */
cstate_info.wake_mask = TEGRA194_CORE_WAKE_MASK;
cstate_info.update_wake_mask = 1;
mce_update_cstate_info(&cstate_info);
}
/* CPU off */
if (lvl == MPIDR_AFFLVL1 && target == PLAT_MAX_OFF_STATE) {
/* find out the number of ON cpus in the cluster */
do {
target = *states++;
if (target != PLAT_MAX_OFF_STATE)
cluster_powerdn = 0;
} while (--ncpu);
if (target == PLAT_MAX_OFF_STATE) {
/* Enable cluster powerdn from last CPU in the cluster */
if (cluster_powerdn) {
if (tegra_last_on_cpu_in_cluster(states, ncpu)) {
/* Enable CC7 state and turn off wake mask */
/* Enable CC6 state and turn off wake mask */
cstate_info.cluster = (uint32_t)TEGRA_NVG_CLUSTER_CC6;
cstate_info.update_wake_mask = 1U;
mce_update_cstate_info(&cstate_info);
} else {
/* Turn off wake_mask */
cstate_info.update_wake_mask = 1U;
mce_update_cstate_info(&cstate_info);
target = PSCI_LOCAL_STATE_RUN;
}
}
return target;
}
/*******************************************************************************
* Platform handler to calculate the proper target power level at the
* specified affinity level
******************************************************************************/
plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
const plat_local_state_t *states,
uint32_t ncpu)
{
plat_local_state_t target = PSCI_LOCAL_STATE_RUN;
uint32_t cpu = plat_my_core_pos();
/* System Suspend */
if ((lvl == MPIDR_AFFLVL2) || (target == PSTATE_ID_SOC_POWERDN))
return PSTATE_ID_SOC_POWERDN;
if ((lvl == (uint32_t)MPIDR_AFFLVL2) && (states[cpu] == PSTATE_ID_SOC_POWERDN)) {
target = PSTATE_ID_SOC_POWERDN;
}
/* default state */
return PSCI_LOCAL_STATE_RUN;
/* CPU off, CPU suspend */
if (lvl == (uint32_t)MPIDR_AFFLVL1) {
target = tegra_get_afflvl1_pwr_state(states, ncpu);
}
/* target cluster/system state */
return target;
}
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
int32_t tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
{
const plat_local_state_t *pwr_domain_state =
target_state->pwr_domain_state;
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
unsigned int stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
TEGRA186_STATE_ID_MASK;
uint8_t stateid_afflvl2 = pwr_domain_state[PLAT_MAX_PWR_LVL] &
TEGRA194_STATE_ID_MASK;
uint64_t val;
u_register_t ns_sctlr_el1;
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
/*
......@@ -231,38 +285,64 @@ int tegra_soc_pwr_domain_power_down_wfi(const psci_power_state_t *target_state)
* BL3-1 over to TZDRAM.
*/
val = params_from_bl2->tzdram_base +
((uintptr_t)&__tegra186_cpu_reset_handler_end -
(uintptr_t)tegra186_cpu_reset_handler);
tegra194_get_cpu_reset_handler_size();
memcpy((void *)(uintptr_t)val, (void *)(uintptr_t)BL31_BASE,
(uintptr_t)&__BL31_END__ - (uintptr_t)BL31_BASE);
/*
* In fake suspend mode, ensure that the loopback procedure
* towards system suspend exit is started, instead of calling
* WFI. This is done by disabling both MMU's of EL1 & El3
* and calling tegra_secure_entrypoint().
*/
if (tegra_fake_system_suspend) {
/*
* Disable EL1's MMU.
*/
ns_sctlr_el1 = read_sctlr_el1();
ns_sctlr_el1 &= (~((u_register_t)SCTLR_M_BIT));
write_sctlr_el1(ns_sctlr_el1);
/*
* Disable MMU to power up the CPU in a "clean"
* state
*/
disable_mmu_el3();
tegra_secure_entrypoint();
panic();
}
}
return PSCI_E_SUCCESS;
}
#endif
int tegra_soc_pwr_domain_on(u_register_t mpidr)
int32_t tegra_soc_pwr_domain_on(u_register_t mpidr)
{
int target_cpu = mpidr & MPIDR_CPU_MASK;
int target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
uint64_t target_cpu = mpidr & MPIDR_CPU_MASK;
uint64_t target_cluster = (mpidr & MPIDR_CLUSTER_MASK) >>
MPIDR_AFFINITY_BITS;
int32_t ret = 0;
if (target_cluster > MPIDR_AFFLVL1) {
if (target_cluster > ((uint32_t)PLATFORM_CLUSTER_COUNT - 1U)) {
ERROR("%s: unsupported CPU (0x%lx)\n", __func__ , mpidr);
return PSCI_E_NOT_PRESENT;
}
/* construct the target CPU # */
target_cpu |= (target_cluster << 2);
target_cpu += (target_cluster << 1U);
mce_command_handler(MCE_CMD_ONLINE_CORE, target_cpu, 0, 0);
ret = mce_command_handler((uint64_t)MCE_CMD_ONLINE_CORE, target_cpu, 0U, 0U);
if (ret < 0) {
return PSCI_E_DENIED;
}
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
{
int stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
uint8_t stateid_afflvl2 = target_state->pwr_domain_state[PLAT_MAX_PWR_LVL];
/*
* Reset power state info for CPUs when onlining, we set
......@@ -278,14 +358,17 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
*/
if (stateid_afflvl2 == PSTATE_ID_SOC_POWERDN) {
mmio_write_32(TEGRA_SE0_BASE + SE_MUTEX_WATCHDOG_NS_LIMIT,
se_regs[0]);
mmio_write_32(TEGRA_RNG1_BASE + RNG_MUTEX_WATCHDOG_NS_LIMIT,
se_regs[1]);
mmio_write_32(TEGRA_PKA1_BASE + PKA_MUTEX_WATCHDOG_NS_LIMIT,
se_regs[2]);
/*
* Enable strict checking after programming the GSC for
* enabling TZSRAM and TZDRAM
*/
mce_enable_strict_checking();
/* Init SMMU */
tegra_smmu_init();
/* Resume SE, RNG1 and PKA1 */
tegra_se_resume();
/*
* Reset power state info for the last core doing SC7
......@@ -298,15 +381,22 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
return PSCI_E_SUCCESS;
}
int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
{
int impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
uint64_t impl = (read_midr() >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK;
int32_t ret = 0;
(void)target_state;
/* Disable Denver's DCO operations */
if (impl == DENVER_IMPL)
if (impl == DENVER_IMPL) {
denver_disable_dco();
}
/* Turn off CPU */
ret = mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
(uint64_t)TEGRA_NVG_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
assert(ret == 0);
return PSCI_E_SUCCESS;
}
......@@ -325,7 +415,7 @@ __dead2 void tegra_soc_prepare_system_off(void)
}
}
int tegra_soc_prepare_system_reset(void)
int32_t tegra_soc_prepare_system_reset(void)
{
return PSCI_E_SUCCESS;
}
plat/nvidia/tegra/soc/t194/plat_secondary.c
View file @ 530a5cbc
......@@ -9,21 +9,14 @@
#include <lib/mmio.h>
#include <mce.h>
#include <string.h>
#include <tegra194_private.h>
#include <tegra_def.h>
#include <tegra_private.h>
#define MISCREG_CPU_RESET_VECTOR 0x2000
#define MISCREG_AA64_RST_LOW 0x2004
#define MISCREG_AA64_RST_HIGH 0x2008
#define MISCREG_AA64_RST_LOW 0x2004U
#define MISCREG_AA64_RST_HIGH 0x2008U
#define CPU_RESET_MODE_AA64 1
extern void tegra_secure_entrypoint(void);
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
extern void tegra186_cpu_reset_handler(void);
extern uint64_t __tegra186_smmu_ctx_start;
#endif
#define CPU_RESET_MODE_AA64 1U
/*******************************************************************************
* Setup secondary CPU vectors
......@@ -31,32 +24,33 @@ extern uint64_t __tegra186_smmu_ctx_start;
void plat_secondary_setup(void)
{
uint32_t addr_low, addr_high;
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
uint64_t cpu_reset_handler_base = params_from_bl2->tzdram_base;
#else
uint64_t cpu_reset_handler_base = (uintptr_t)tegra_secure_entrypoint;
#endif
uint64_t cpu_reset_handler_base, cpu_reset_handler_size;
INFO("Setting up secondary CPU boot\n");
#if ENABLE_SYSTEM_SUSPEND_CTX_SAVE_TZDRAM
memcpy((void *)((uintptr_t)cpu_reset_handler_base),
(void *)(uintptr_t)tegra186_cpu_reset_handler,
(uintptr_t)&__tegra186_smmu_ctx_start -
(uintptr_t)tegra186_cpu_reset_handler);
#endif
addr_low = (uint32_t)cpu_reset_handler_base | CPU_RESET_MODE_AA64;
addr_high = (uint32_t)((cpu_reset_handler_base >> 32) & 0x7ff);
/*
* The BL31 code resides in the TZSRAM which loses state
* when we enter System Suspend. Copy the wakeup trampoline
* code to TZDRAM to help us exit from System Suspend.
*/
cpu_reset_handler_base = tegra194_get_cpu_reset_handler_base();
cpu_reset_handler_size = tegra194_get_cpu_reset_handler_size();
memcpy((void *)((uintptr_t)params_from_bl2->tzdram_base),
(void *)((uintptr_t)cpu_reset_handler_base),
cpu_reset_handler_size);
/* TZDRAM base will be used as the "resume" address */
addr_low = (uint32_t)params_from_bl2->tzdram_base | CPU_RESET_MODE_AA64;
addr_high = (uint32_t)((params_from_bl2->tzdram_base >> 32U) & 0x7ffU);
/* write lower 32 bits first, then the upper 11 bits */
mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_LOW, addr_low);
mmio_write_32(TEGRA_MISC_BASE + MISCREG_AA64_RST_HIGH, addr_high);
/* save reset vector to be used during SYSTEM_SUSPEND exit */
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_LO,
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_LO,
addr_low);
mmio_write_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV1_HI,
mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_RESET_VECTOR_HI,
addr_high);
}
plat/nvidia/tegra/soc/t194/plat_setup.c
View file @ 530a5cbc
......@@ -19,19 +19,25 @@
#include <drivers/arm/gicv2.h>
#include <bl31/interrupt_mgmt.h>
#include <mce.h>
#include <mce_private.h>
#include <plat/common/platform.h>
#include <spe.h>
#include <tegra_def.h>
#include <tegra_mc_def.h>
#include <tegra_platform.h>
#include <tegra_private.h>
#include <lib/xlat_tables/xlat_tables_v2.h>
/* ID for spe-console */
#define TEGRA_CONSOLE_SPE_ID 0xFE
/*******************************************************************************
* The Tegra power domain tree has a single system level power domain i.e. a
* single root node. The first entry in the power domain descriptor specifies
* the number of power domains at the highest power level.
*******************************************************************************
*/
const unsigned char tegra_power_domain_tree_desc[] = {
static const uint8_t tegra_power_domain_tree_desc[] = {
/* No of root nodes */
1,
/* No of clusters */
......@@ -39,13 +45,17 @@ const unsigned char tegra_power_domain_tree_desc[] = {
/* No of CPU cores - cluster0 */
PLATFORM_MAX_CPUS_PER_CLUSTER,
/* No of CPU cores - cluster1 */
PLATFORM_MAX_CPUS_PER_CLUSTER,
/* No of CPU cores - cluster2 */
PLATFORM_MAX_CPUS_PER_CLUSTER,
/* No of CPU cores - cluster3 */
PLATFORM_MAX_CPUS_PER_CLUSTER
};
/*******************************************************************************
* This function returns the Tegra default topology tree information.
******************************************************************************/
const unsigned char *plat_get_power_domain_tree_desc(void)
const uint8_t *plat_get_power_domain_tree_desc(void)
{
return tegra_power_domain_tree_desc;
}
......@@ -54,44 +64,52 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
* Table of regions to map using the MMU.
*/
static const mmap_region_t tegra_mmap[] = {
MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000, /* 128KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000, /* 128KB - UART A, B*/
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000, /* 128KB - UART C, G */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000, /* 192KB - UART D, E, F */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000, /* 128KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000, /* 256KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000, /* 384KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000, /* 64KB */
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(TEGRA_MISC_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_TSA_BASE, 0x20000U, /* 128KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_MC_STREAMID_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_MC_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
#if !ENABLE_CONSOLE_SPE
MAP_REGION_FLAT(TEGRA_UARTA_BASE, 0x20000U, /* 128KB - UART A, B*/
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_UARTC_BASE, 0x20000U, /* 128KB - UART C, G */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_UARTD_BASE, 0x30000U, /* 192KB - UART D, E, F */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
#endif
MAP_REGION_FLAT(TEGRA_FUSE_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_GICD_BASE, 0x20000U, /* 128KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_SE0_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_PKA1_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_RNG1_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
#if ENABLE_CONSOLE_SPE
MAP_REGION_FLAT(TEGRA_AON_HSP_SM_6_7_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
#endif
MAP_REGION_FLAT(TEGRA_CAR_RESET_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_PMC_BASE, 0x40000U, /* 256KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_SCRATCH_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_MMCRAB_BASE, 0x60000U, /* 384KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_SMMU0_BASE, 0x1000000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_SMMU1_BASE, 0x1000000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_SMMU2_BASE, 0x1000000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
MAP_REGION_FLAT(TEGRA_XUSB_PADCTL_BASE, 0x10000U, /* 64KB */
(uint8_t)MT_DEVICE | (uint8_t)MT_RW | (uint8_t)MT_SECURE),
{0}
};
......@@ -107,20 +125,21 @@ const mmap_region_t *plat_get_mmio_map(void)
/*******************************************************************************
* Handler to get the System Counter Frequency
******************************************************************************/
unsigned int plat_get_syscnt_freq2(void)
uint32_t plat_get_syscnt_freq2(void)
{
return 31250000;
}
#if !ENABLE_CONSOLE_SPE
/*******************************************************************************
* Maximum supported UART controllers
******************************************************************************/
#define TEGRA186_MAX_UART_PORTS 7
#define TEGRA194_MAX_UART_PORTS 7
/*******************************************************************************
* This variable holds the UART port base addresses
******************************************************************************/
static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
static uint32_t tegra194_uart_addresses[TEGRA194_MAX_UART_PORTS + 1] = {
0, /* undefined - treated as an error case */
TEGRA_UARTA_BASE,
TEGRA_UARTB_BASE,
......@@ -128,18 +147,49 @@ static uint32_t tegra186_uart_addresses[TEGRA186_MAX_UART_PORTS + 1] = {
TEGRA_UARTD_BASE,
TEGRA_UARTE_BASE,
TEGRA_UARTF_BASE,
TEGRA_UARTG_BASE,
TEGRA_UARTG_BASE
};
#endif
/*******************************************************************************
* Retrieve the UART controller base to be used as the console
* Enable console corresponding to the console ID
******************************************************************************/
uint32_t plat_get_console_from_id(int id)
void plat_enable_console(int32_t id)
{
if (id > TEGRA186_MAX_UART_PORTS)
return 0;
uint32_t console_clock = 0U;
#if ENABLE_CONSOLE_SPE
static console_spe_t spe_console;
if (id == TEGRA_CONSOLE_SPE_ID) {
(void)console_spe_register(TEGRA_CONSOLE_SPE_BASE,
console_clock,
TEGRA_CONSOLE_BAUDRATE,
&spe_console);
console_set_scope(&spe_console.console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
}
#else
static console_16550_t uart_console;
if ((id > 0) && (id < TEGRA194_MAX_UART_PORTS)) {
/*
* Reference clock used by the FPGAs is a lot slower.
*/
if (tegra_platform_is_fpga()) {
console_clock = TEGRA_BOOT_UART_CLK_13_MHZ;
} else {
console_clock = TEGRA_BOOT_UART_CLK_408_MHZ;
}
return tegra186_uart_addresses[id];
(void)console_16550_register(tegra194_uart_addresses[id],
console_clock,
TEGRA_CONSOLE_BAUDRATE,
&uart_console);
console_set_scope(&uart_console.console, CONSOLE_FLAG_BOOT |
CONSOLE_FLAG_RUNTIME | CONSOLE_FLAG_CRASH);
}
#endif
}
/*******************************************************************************
......@@ -151,40 +201,61 @@ void plat_early_platform_setup(void)
/* sanity check MCE firmware compatibility */
mce_verify_firmware_version();
/* Program XUSB STREAMIDs
* Xavier XUSB has support for XUSB virtualization. It will have one
* physical function (PF) and four Virtual function (VF)
*
* There were below two SIDs for XUSB until T186.
* 1) #define TEGRA_SID_XUSB_HOST 0x1bU
* 2) #define TEGRA_SID_XUSB_DEV 0x1cU
*
* We have below four new SIDs added for VF(s)
* 3) #define TEGRA_SID_XUSB_VF0 0x5dU
* 4) #define TEGRA_SID_XUSB_VF1 0x5eU
* 5) #define TEGRA_SID_XUSB_VF2 0x5fU
* 6) #define TEGRA_SID_XUSB_VF3 0x60U
*
* When virtualization is enabled then we have to disable SID override
* and program above SIDs in below newly added SID registers in XUSB
* PADCTL MMIO space. These registers are TZ protected and so need to
* be done in ATF.
* a) #define XUSB_PADCTL_HOST_AXI_STREAMID_PF_0 (0x136cU)
* b) #define XUSB_PADCTL_DEV_AXI_STREAMID_PF_0 (0x139cU)
* c) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_0 (0x1370U)
* d) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_1 (0x1374U)
* e) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_2 (0x1378U)
* f) #define XUSB_PADCTL_HOST_AXI_STREAMID_VF_3 (0x137cU)
*
* This change disables SID override and programs XUSB SIDs in
* above registers to support both virtualization and non-virtualization
*
* Known Limitations:
* If xusb interface disables SMMU in XUSB DT in non-virtualization
* setup then there will be SMMU fault. We need to use WAR at
* https:\\git-master.nvidia.com/r/1529227/ to the issue.
*
* More details can be found in the bug 1971161
*/
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_HOST);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_0, TEGRA_SID_XUSB_VF0);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_1, TEGRA_SID_XUSB_VF1);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_2, TEGRA_SID_XUSB_VF2);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_HOST_AXI_STREAMID_VF_3, TEGRA_SID_XUSB_VF3);
mmio_write_32(TEGRA_XUSB_PADCTL_BASE +
XUSB_PADCTL_DEV_AXI_STREAMID_PF_0, TEGRA_SID_XUSB_DEV);
}
/* Secure IRQs for Tegra186 */
static const irq_sec_cfg_t tegra186_sec_irqs[] = {
[0] = {
TEGRA186_BPMP_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
[1] = {
TEGRA186_BPMP_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
[2] = {
TEGRA186_SPE_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
[3] = {
TEGRA186_SCE_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
[4] = {
TEGRA186_TOP_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
[5] = {
TEGRA186_AON_WDT_IRQ,
TEGRA186_SEC_IRQ_TARGET_MASK,
INTR_TYPE_EL3,
},
/* Secure IRQs for Tegra194 */
static const interrupt_prop_t tegra194_interrupt_props[] = {
INTR_PROP_DESC(TEGRA194_TOP_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE),
INTR_PROP_DESC(TEGRA194_AON_WDT_IRQ, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_EDGE)
};
/*******************************************************************************
......@@ -192,15 +263,13 @@ static const irq_sec_cfg_t tegra186_sec_irqs[] = {
******************************************************************************/
void plat_gic_setup(void)
{
tegra_gic_setup(tegra186_sec_irqs,
sizeof(tegra186_sec_irqs) / sizeof(tegra186_sec_irqs[0]));
tegra_gic_setup(tegra194_interrupt_props, ARRAY_SIZE(tegra194_interrupt_props));
tegra_gic_init();
/*
* Initialize the FIQ handler only if the platform supports any
* FIQ interrupt sources.
* Initialize the FIQ handler
*/
if (sizeof(tegra186_sec_irqs) > 0)
tegra_fiq_handler_setup();
tegra_fiq_handler_setup();
}
/*******************************************************************************
......@@ -210,7 +279,7 @@ struct tegra_bl31_params *plat_get_bl31_params(void)
{
uint32_t val;
val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_LO);
val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PARAMS_ADDR);
return (struct tegra_bl31_params *)(uintptr_t)val;
}
......@@ -222,7 +291,16 @@ plat_params_from_bl2_t *plat_get_bl31_plat_params(void)
{
uint32_t val;
val = mmio_read_32(TEGRA_SCRATCH_BASE + SECURE_SCRATCH_RSV53_HI);
val = mmio_read_32(TEGRA_SCRATCH_BASE + SCRATCH_BL31_PLAT_PARAMS_ADDR);
return (plat_params_from_bl2_t *)(uintptr_t)val;
}
void plat_late_platform_setup(void)
{
/*
* Enable strict checking after programming the GSC for
* enabling TZSRAM and TZDRAM
*/
mce_enable_strict_checking();
}
plat/nvidia/tegra/soc/t194/plat_sip_calls.c
View file @ 530a5cbc
......@@ -15,38 +15,20 @@
#include <memctrl.h>
#include <common/runtime_svc.h>
#include <tegra_private.h>
#include <tegra_platform.h>
#include <stdbool.h>
extern uint32_t tegra186_system_powerdn_state;
extern bool tegra_fake_system_suspend;
/*******************************************************************************
* Tegra186 SiP SMCs
* Tegra194 SiP SMCs
******************************************************************************/
#define TEGRA_SIP_SYSTEM_SHUTDOWN_STATE 0xC2FFFE01
#define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02
#define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00
#define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01
#define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02
#define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03
#define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04
#define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05
#define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06
#define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07
#define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08
#define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09
#define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A
#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B
#define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C
#define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D
#define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E
#define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F
#define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10
#define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11
#define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12
#define TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND 0xC2FFFE03U
/*******************************************************************************
* This function is responsible for handling all T186 SiP calls
* This function is responsible for handling all T194 SiP calls
******************************************************************************/
int plat_sip_handler(uint32_t smc_fid,
int32_t plat_sip_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
uint64_t x3,
......@@ -55,64 +37,27 @@ int plat_sip_handler(uint32_t smc_fid,
void *handle,
uint64_t flags)
{
int mce_ret;
int32_t ret = -ENOTSUP;
/*
* Convert SMC FID to SMC64 until the linux driver uses
* SMC64 encoding.
*/
smc_fid |= (SMC_64 << FUNCID_CC_SHIFT);
switch (smc_fid) {
/*
* Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 -
* 0x82FFFFFF SiP SMC space
*/
case TEGRA_SIP_MCE_CMD_ENTER_CSTATE:
case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO:
case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME:
case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS:
case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS:
case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED:
case TEGRA_SIP_MCE_CMD_CC3_CTRL:
case TEGRA_SIP_MCE_CMD_ECHO_DATA:
case TEGRA_SIP_MCE_CMD_READ_VERSIONS:
case TEGRA_SIP_MCE_CMD_ENUM_FEATURES:
case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA:
case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA:
case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE:
case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE:
case TEGRA_SIP_MCE_CMD_ENABLE_LATIC:
case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ:
case TEGRA_SIP_MCE_CMD_MISC_CCPLEX:
/* clean up the high bits */
smc_fid &= MCE_CMD_MASK;
/* execute the command and store the result */
mce_ret = mce_command_handler(smc_fid, x1, x2, x3);
write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, mce_ret);
return 0;
case TEGRA_SIP_SYSTEM_SHUTDOWN_STATE:
/* clean up the high bits */
x1 = (uint32_t)x1;
(void)x1;
(void)x4;
(void)cookie;
(void)flags;
if (smc_fid == TEGRA_SIP_ENABLE_FAKE_SYSTEM_SUSPEND) {
/*
* SC8 is a special Tegra186 system state where the CPUs and
* DRAM are powered down but the other subsystem is still
* alive.
* System suspend mode is set if the platform ATF is
* running on VDK and there is a debug SIP call. This mode
* ensures that the debug path is exercised, instead of
* regular code path to suit the pre-silicon platform needs.
* This includes replacing the call to WFI, with calls to
* system suspend exit procedures.
*/
return 0;
default:
break;
if (tegra_platform_is_virt_dev_kit()) {
tegra_fake_system_suspend = true;
ret = 0;
}
}
return -ENOTSUP;
return ret;
}
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