Commit 538b0020 authored by Paul Beesley's avatar Paul Beesley Committed by Manish Pandey
Browse files

spm: Remove SPM Alpha 1 prototype and support files


The Secure Partition Manager (SPM) prototype implementation is
being removed. This is preparatory work for putting in place a
dispatcher component that, in turn, enables partition managers
at S-EL2 / S-EL1.

This patch removes:

- The core service files (std_svc/spm)
- The Resource Descriptor headers (include/services)
- SPRT protocol support and service definitions
- SPCI protocol support and service definitions

Change-Id: Iaade6f6422eaf9a71187b1e2a4dffd7fb8766426
Signed-off-by: default avatarPaul Beesley <paul.beesley@arm.com>
Signed-off-by: default avatarArtsem Artsemenka <artsem.artsemenka@arm.com>
parent 3f3c341a
Showing with 7 additions and 907 deletions
+7 -907
......@@ -571,14 +571,6 @@ ifeq ($(CTX_INCLUDE_MTE_REGS),1)
endif
endif
# The SPCI-based SPM implementation and the MM-based SPM implementation cannot
# be enabled at the same time.
ifeq ($(ENABLE_SPM),1)
ifeq ($(SPM_MM),1)
$(error Use only one of the ENABLE_SPM and SPM_MM flags)
endif
endif
################################################################################
# Process platform overrideable behaviour
################################################################################
......@@ -719,7 +711,6 @@ $(eval $(call assert_boolean,ENABLE_PMF))
$(eval $(call assert_boolean,ENABLE_PSCI_STAT))
$(eval $(call assert_boolean,ENABLE_RUNTIME_INSTRUMENTATION))
$(eval $(call assert_boolean,ENABLE_SPE_FOR_LOWER_ELS))
$(eval $(call assert_boolean,ENABLE_SPM))
$(eval $(call assert_boolean,ENABLE_SVE_FOR_NS))
$(eval $(call assert_boolean,ERROR_DEPRECATED))
$(eval $(call assert_boolean,FAULT_INJECTION_SUPPORT))
......@@ -784,7 +775,6 @@ $(eval $(call add_define,ENABLE_PMF))
$(eval $(call add_define,ENABLE_PSCI_STAT))
$(eval $(call add_define,ENABLE_RUNTIME_INSTRUMENTATION))
$(eval $(call add_define,ENABLE_SPE_FOR_LOWER_ELS))
$(eval $(call add_define,ENABLE_SPM))
$(eval $(call add_define,ENABLE_SVE_FOR_NS))
$(eval $(call add_define,ERROR_DEPRECATED))
$(eval $(call add_define,FAULT_INJECTION_SUPPORT))
......
......@@ -142,7 +142,7 @@ SECTIONS
ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
"cpu_ops not defined for this platform.")
#if ENABLE_SPM || SPM_MM
#if SPM_MM
#ifndef SPM_SHIM_EXCEPTIONS_VMA
#define SPM_SHIM_EXCEPTIONS_VMA RAM
#endif
......
......@@ -5,16 +5,11 @@
#
################################################################################
# Include Makefile for either of the supported SPM implementations
# Include Makefile for the SPM-MM implementation
################################################################################
ifeq (${ENABLE_SPM},1)
$(info Including SPM (SPCI) makefile)
include services/std_svc/spm/spm.mk
endif
ifeq (${SPM_MM},1)
ifeq (${EL3_EXCEPTION_HANDLING},0)
$(error EL3_EXCEPTION_HANDLING must be 1 for SPM support)
$(error EL3_EXCEPTION_HANDLING must be 1 for SPM-MM support)
else
$(info Including SPM Management Mode (MM) makefile)
include services/std_svc/spm_mm/spm.mk
......
......@@ -235,11 +235,6 @@ Common build options
The default is 1 but is automatically disabled when the target architecture
is AArch32.
- ``ENABLE_SPM`` : Boolean option to enable the SPCI-based Secure Partition
Manager (SPM) implementation.
Refer to the :ref:`Secure Partition Manager` guide for more details about
this feature. Default is 0.
- ``ENABLE_SVE_FOR_NS``: Boolean option to enable Scalable Vector Extension
(SVE) for the Non-secure world only. SVE is an optional architectural feature
for AArch64. Note that when SVE is enabled for the Non-secure world, access
......
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPRT_COMMON_H
#define SPRT_COMMON_H
#define SPRT_MAX_MSG_ARGS 6
/*
* Message types supported.
*/
#define SPRT_MSG_TYPE_SERVICE_HANDLE_OPEN 1
#define SPRT_MSG_TYPE_SERVICE_HANDLE_CLOSE 2
/* TODO: Add other types of SPRT messages. */
#define SPRT_MSG_TYPE_SERVICE_TUN_REQUEST 10
/*
* Struct that defines the layout of the fields corresponding to a request in
* shared memory.
*/
struct __attribute__((__packed__)) sprt_queue_entry_message {
uint32_t type; /* Type of message (result of an SPCI call). */
uint16_t client_id; /* SPCI client ID */
uint16_t service_handle;/* SPCI service handle */
uint32_t session_id; /* Optional SPCI session ID */
uint32_t token; /* SPCI request token */
uint64_t args[SPRT_MAX_MSG_ARGS];
};
#define SPRT_QUEUE_ENTRY_MSG_SIZE (sizeof(struct sprt_queue_entry_message))
#define SPRT_QUEUE_NUM_BLOCKING 0
#define SPRT_QUEUE_NUM_NON_BLOCKING 1
#endif /* SPRT_COMMON_H */
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPRT_HOST_H
#define SPRT_HOST_H
#include <stddef.h>
#include "sprt_common.h"
/*
* Initialize the specified buffer to be used by SPM.
*/
void sprt_initialize_queues(void *buffer_base, size_t buffer_size);
/*
* Push a message to the queue number `queue_num` in a buffer that has been
* initialized by `sprt_initialize_queues`.
*/
int sprt_push_message(void *buffer_base,
const struct sprt_queue_entry_message *message,
int queue_num);
#endif /* SPRT_HOST_H */
......@@ -457,7 +457,7 @@
* Trusted DRAM (if available) or the DRAM region secured by the TrustZone
* controller.
*/
# if ENABLE_SPM
# if SPM_MM
# define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
# define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000))
# define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000))
......@@ -500,9 +500,9 @@
* SPD and no SPM, as they are the only ones that can be used as BL32.
*/
#if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME
# if defined(SPD_none) && !ENABLE_SPM && !SPM_MM
# if defined(SPD_none) && !SPM_MM
# undef BL32_BASE
# endif /* defined(SPD_none) && !ENABLE_SPM && !SPM_MM*/
# endif /* defined(SPD_none) && !SPM_MM*/
#endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */
/*******************************************************************************
......
......@@ -9,31 +9,6 @@
#include <lib/utils_def.h>
#include <lib/xlat_tables/xlat_tables_defs.h>
/*
* Reserve 4 MiB for binaries of Secure Partitions and Resource Description
* blobs.
*/
#define PLAT_SP_PACKAGE_BASE BL32_BASE
#define PLAT_SP_PACKAGE_SIZE ULL(0x400000)
#define PLAT_MAP_SP_PACKAGE_MEM_RO MAP_REGION_FLAT( \
PLAT_SP_PACKAGE_BASE, \
PLAT_SP_PACKAGE_SIZE, \
MT_MEMORY | MT_RO | MT_SECURE)
#define PLAT_MAP_SP_PACKAGE_MEM_RW MAP_REGION_FLAT( \
PLAT_SP_PACKAGE_BASE, \
PLAT_SP_PACKAGE_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
/*
* The rest of the memory reserved for BL32 is free for SPM to use it as memory
* pool to allocate memory regions requested in the resource description.
*/
#define PLAT_SPM_HEAP_BASE (PLAT_SP_PACKAGE_BASE + PLAT_SP_PACKAGE_SIZE)
#define PLAT_SPM_HEAP_SIZE (BL32_LIMIT - BL32_BASE - PLAT_SP_PACKAGE_SIZE)
#if SPM_MM
/*
* If BL31 is placed in DRAM, place the Secure Partition in DRAM right after the
* region used by BL31. If BL31 it is placed in SRAM, put the Secure Partition
......@@ -121,23 +96,8 @@
/* Total number of memory regions with distinct properties */
#define ARM_SP_IMAGE_NUM_MEM_REGIONS 6
#endif /* SPM_MM */
/* Cookies passed to the Secure Partition at boot. Not used by ARM platforms. */
#define PLAT_SPM_COOKIE_0 ULL(0)
#define PLAT_SPM_COOKIE_1 ULL(0)
/*
* Max number of elements supported by SPM in this platform. The defines below
* are used to allocate memory at compile time for different arrays in SPM.
*/
#define PLAT_SPM_MAX_PARTITIONS U(2)
#define PLAT_SPM_MEM_REGIONS_MAX U(80)
#define PLAT_SPM_NOTIFICATIONS_MAX U(30)
#define PLAT_SPM_SERVICES_MAX U(30)
#define PLAT_SPCI_HANDLES_MAX_NUM U(20)
#define PLAT_SPM_RESPONSES_MAX U(30)
#endif /* ARM_SPM_DEF_H */
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPM_RES_DESC_H
#define SPM_RES_DESC_H
#include <stdint.h>
#include <services/sp_res_desc_def.h>
/*******************************************************************************
* Attribute Section
******************************************************************************/
struct sp_rd_sect_attribute {
/*
* Version of the resource description.
*/
uint16_t version;
/*
* Type of the Secure Partition:
* - bit[0]: SP Type
* - b'0: UP SP
* - b'1: MP SP
* If UP SP:
* - bit[1]: Type of UP SP
* - b'0: Migratable UP SP
* - b'1: Pinned UP SP
*/
uint16_t sp_type;
/*
* If this is a Pinned UP SP, PE on which the Pinned UP SP will run.
*/
uint32_t pe_mpidr;
/*
* Run-Time Exception Level:
* - 0: SEL0 SP
* - 1: SEL1 SP
*/
uint8_t runtime_el;
/*
* Type of Execution:
* - 0: Init-time only
* - 1: Run-time Execution
*/
uint8_t exec_type;
/*
* Expected behavior upon failure:
* - 0: Restartable
* - 1: One-Shot
*/
uint8_t panic_policy;
/*
* Translation Granule to use in the SP translation regime:
* - 0: 4KB
* - 1: 16KB
* - 2: 64KB
*/
uint8_t xlat_granule;
/*
* Size of the SP binary in bytes.
*/
uint32_t binary_size;
/*
* - If SP is NOT PIE:
* - VA Address where the SP expects to be loaded.
* - If SP is PIE:
* - Ignored.
*/
uint64_t load_address;
/*
* Initial execution address. This is a VA as the SP sees it.
*/
uint64_t entrypoint;
};
/*******************************************************************************
* Memory Region Section
******************************************************************************/
struct sp_rd_sect_mem_region {
/*
* Name of a Memory region, including null terminator. Reserved names:
* - "Client Shared Memory Region":
* Memory region where memory shared by clients shall be mapped.
* - "Queue Memory Region":
* Memory region shared with SPM for SP queue management.
*/
char name[RD_MEM_REGION_NAME_LEN];
/*
* Memory Attributes:
* - bits[3:0]: Type of memory
* - 0: Device
* - 1: Code
* - 2: Data
* - 3: BSS
* - 4: Read-only Data
* - 5: SPM-to-SP Shared Memory Region
* - 6: Client Shared Memory Region
* - 7: Miscellaneous
* - If memory is { SPM-to-SP shared Memory, Client Shared Memory,
* Miscellaneous }
* - bits[4]: Position Independent
* - b'0: Position Dependent
* - b'1: Position Independent
*/
uint32_t attr;
/*
* Base address of the memory region.
*/
uint64_t base;
/*
* Size of the memory region.
*/
uint64_t size;
/*
* Pointer to next memory region (or NULL if this is the last one).
*/
struct sp_rd_sect_mem_region *next;
};
/*******************************************************************************
* Notification Section
******************************************************************************/
struct sp_rd_sect_notification {
/*
* Notification attributes:
* - bit[31]: Notification Type
* - b'0: Platform Notification
* - b'1: Interrupt
* If Notification Type == Platform Notification
* - bits[15:0]: Implementation-defined Notification ID
* If Notification Type == Interrupt
* - bits[15:0]: IRQ number
* - bits[23:16]: Interrupt Priority
* - bit[24]: Trigger Type
* - b'0: Edge Triggered
* - b'1: Level Triggered
* - bit[25]: Trigger Level
* - b'0: Falling or Low
* - b'1: Rising or High
*/
uint32_t attr;
/*
* Processing Element.
* If Notification Type == Interrupt && IRQ number is { SGI, LPI }
* - PE ID to which IRQ will be forwarded
*/
uint32_t pe;
/*
* Pointer to next notification (or NULL if this is the last one).
*/
struct sp_rd_sect_notification *next;
};
/*******************************************************************************
* Service Description Section
******************************************************************************/
struct sp_rd_sect_service {
/*
* Service identifier.
*/
uint32_t uuid[4];
/*
* Accessibility Options:
* - bit[0]: Accessibility by secure-world clients
* - b'0: Not Accessible
* - b'1: Accessible
* - bit[1]: Accessible by EL3
* - b'0: Not Accessible
* - b'1: Accessible
* - bit[2]: Accessible by normal-world clients
* - b'0: Not Accessible
* - b'1: Accessible
*/
uint8_t accessibility;
/*
* Request type supported:
* - bit[0]: Blocking request
* - b'0: Not Enable
* - b'1: Enable
* - bit[1]: Non-blocking request
* - b'0: Not Enable
* - b'1: Enable
*/
uint8_t request_type;
/*
* Maximum number of client connections that the service can support.
*/
uint16_t connection_quota;
/*
* If the service requires secure world memory to be shared with its
* clients:
* - Maximum amount of secure world memory in bytes to reserve from the
* secure world memory pool for the service.
*/
uint32_t secure_mem_size;
/*
* Interrupt number used to notify the SP for the service.
* - Should also be enabled in the Notification Section.
*/
uint32_t interrupt_num;
/*
* Pointer to next service (or NULL if this is the last one).
*/
struct sp_rd_sect_service *next;
};
/*******************************************************************************
* Complete resource description struct
******************************************************************************/
struct sp_res_desc {
/* Attribute Section */
struct sp_rd_sect_attribute attribute;
/* System Resource Section */
struct sp_rd_sect_mem_region *mem_region;
struct sp_rd_sect_notification *notification;
/* Service Section */
struct sp_rd_sect_service *service;
};
#endif /* SPM_RES_DESC_H */
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPM_RES_DESC_DEFS_H
#define SPM_RES_DESC_DEFS_H
#include <lib/utils_def.h>
/*******************************************************************************
* Attribute Section
******************************************************************************/
#define RD_ATTR_TYPE_UP_MIGRATABLE U(0)
#define RD_ATTR_TYPE_UP_PINNED U(2)
#define RD_ATTR_TYPE_MP U(1)
#define RD_ATTR_RUNTIME_SEL0 U(0)
#define RD_ATTR_RUNTIME_SEL1 U(1)
#define RD_ATTR_INIT_ONLY U(0)
#define RD_ATTR_RUNTIME U(1)
#define RD_ATTR_PANIC_RESTART U(0)
#define RD_ATTR_PANIC_ONESHOT U(1)
#define RD_ATTR_XLAT_GRANULE_4KB U(0)
#define RD_ATTR_XLAT_GRANULE_16KB U(1)
#define RD_ATTR_XLAT_GRANULE_64KB U(2)
/*******************************************************************************
* Memory Region Section
******************************************************************************/
#define RD_MEM_REGION_NAME_LEN U(32)
#define RD_MEM_DEVICE U(0)
#define RD_MEM_NORMAL_CODE U(1)
#define RD_MEM_NORMAL_DATA U(2)
#define RD_MEM_NORMAL_BSS U(3)
#define RD_MEM_NORMAL_RODATA U(4)
#define RD_MEM_NORMAL_SPM_SP_SHARED_MEM U(5)
#define RD_MEM_NORMAL_CLIENT_SHARED_MEM U(6)
#define RD_MEM_NORMAL_MISCELLANEOUS U(7)
#define RD_MEM_MASK U(15)
#define RD_MEM_IS_PIE (U(1) << 4)
/*******************************************************************************
* Notification Section
******************************************************************************/
#define RD_NOTIF_TYPE_PLATFORM (U(0) << 31)
#define RD_NOTIF_TYPE_INTERRUPT (U(1) << 31)
#define RD_NOTIF_PLAT_ID_MASK U(0xFFFF)
#define RD_NOTIF_PLAT_ID_SHIFT U(0)
#define RD_NOTIF_PLATFORM(id) \
(RD_NOTIF_TYPE_PLATFORM \
| (((id) & RD_NOTIF_PLAT_ID_MASK) << RD_NOTIF_PLAT_ID_SHIFT))
#define RD_NOTIF_IRQ_NUM_MASK U(0xFFFF)
#define RD_NOTIF_IRQ_NUM_SHIFT U(0)
#define RD_NOTIF_IRQ_PRIO_MASK U(0xFF)
#define RD_NOTIF_IRQ_PRIO_SHIFT U(16)
#define RD_NOTIF_IRQ_EDGE_FALLING U(0)
#define RD_NOTIF_IRQ_EDGE_RISING U(2)
#define RD_NOTIF_IRQ_LEVEL_LOW U(1)
#define RD_NOTIF_IRQ_LEVEL_HIGH U(3)
#define RD_NOTIF_IRQ_TRIGGER_SHIFT U(24)
#define RD_NOTIF_IRQ(num, prio, trig) \
(RD_NOTIF_TYPE_IRQ \
| (((num) & RD_NOTIF_IRQ_NUM_MASK) << RD_NOTIF_IRQ_NUM_SHIFT) \
| (((prio) & RD_NOTIF_IRQ_PRIO_MASK) << RD_NOTIF_IRQ_PRIO_SHIFT) \
| (((trig) << RD_NOTIF_IRQ_TRIGGER_SHIFT)))
/*******************************************************************************
* Service Description Section
******************************************************************************/
#define RD_SERV_ACCESS_SECURE (U(1) << 0)
#define RD_SERV_ACCESS_EL3 (U(1) << 1)
#define RD_SERV_ACCESS_NORMAL (U(1) << 2)
#define RD_SERV_SUPPORT_BLOCKING (U(1) << 0)
#define RD_SERV_SUPPORT_NON_BLOCKING (U(1) << 0)
#endif /* SPM_RES_DESC_DEFS_H */
/*
* Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPCI_SVC_H
#define SPCI_SVC_H
#include <lib/smccc.h>
#include <lib/utils_def.h>
/* SPCI_VERSION helpers */
#define SPCI_VERSION_MAJOR U(0)
#define SPCI_VERSION_MAJOR_SHIFT 16
#define SPCI_VERSION_MAJOR_MASK U(0x7FFF)
#define SPCI_VERSION_MINOR U(1)
#define SPCI_VERSION_MINOR_SHIFT 0
#define SPCI_VERSION_MINOR_MASK U(0xFFFF)
#define SPCI_VERSION_FORM(major, minor) ((((major) & SPCI_VERSION_MAJOR_MASK) \
<< SPCI_VERSION_MAJOR_SHIFT) | \
((minor) & SPCI_VERSION_MINOR_MASK))
#define SPCI_VERSION_COMPILED SPCI_VERSION_FORM(SPCI_VERSION_MAJOR, \
SPCI_VERSION_MINOR)
/* Definitions to build the complete SMC ID */
#define SPCI_FID_MISC_FLAG (U(0) << 27)
#define SPCI_FID_MISC_SHIFT U(20)
#define SPCI_FID_MISC_MASK U(0x7F)
#define SPCI_FID_TUN_FLAG (U(1) << 27)
#define SPCI_FID_TUN_SHIFT U(24)
#define SPCI_FID_TUN_MASK U(0x7)
#define OEN_SPCI_START U(0x30)
#define OEN_SPCI_END U(0x3F)
#define SPCI_SMC(spci_fid) ((OEN_SPCI_START << FUNCID_OEN_SHIFT) | \
(U(1) << 31) | (spci_fid))
#define SPCI_MISC_32(misc_fid) ((SMC_32 << FUNCID_CC_SHIFT) | \
SPCI_FID_MISC_FLAG | \
SPCI_SMC((misc_fid) << SPCI_FID_MISC_SHIFT))
#define SPCI_MISC_64(misc_fid) ((SMC_64 << FUNCID_CC_SHIFT) | \
SPCI_FID_MISC_FLAG | \
SPCI_SMC((misc_fid) << SPCI_FID_MISC_SHIFT))
#define SPCI_TUN_32(tun_fid) ((SMC_32 << FUNCID_CC_SHIFT) | \
SPCI_FID_TUN_FLAG | \
SPCI_SMC((tun_fid) << SPCI_FID_TUN_SHIFT))
#define SPCI_TUN_64(tun_fid) ((SMC_64 << FUNCID_CC_SHIFT) | \
SPCI_FID_TUN_FLAG | \
SPCI_SMC((tun_fid) << SPCI_FID_TUN_SHIFT))
/* SPCI miscellaneous functions */
#define SPCI_FID_VERSION U(0x0)
#define SPCI_FID_SERVICE_HANDLE_OPEN U(0x2)
#define SPCI_FID_SERVICE_HANDLE_CLOSE U(0x3)
#define SPCI_FID_SERVICE_MEM_REGISTER U(0x4)
#define SPCI_FID_SERVICE_MEM_UNREGISTER U(0x5)
#define SPCI_FID_SERVICE_MEM_PUBLISH U(0x6)
#define SPCI_FID_SERVICE_REQUEST_BLOCKING U(0x7)
#define SPCI_FID_SERVICE_REQUEST_START U(0x8)
#define SPCI_FID_SERVICE_GET_RESPONSE U(0x9)
#define SPCI_FID_SERVICE_RESET_CLIENT_STATE U(0xA)
/* SPCI tunneling functions */
#define SPCI_FID_SERVICE_TUN_REQUEST_START U(0x0)
#define SPCI_FID_SERVICE_REQUEST_RESUME U(0x1)
#define SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING U(0x2)
/* Complete SMC IDs and associated values */
#define SPCI_VERSION SPCI_MISC_32(SPCI_FID_VERSION)
#define SPCI_SERVICE_HANDLE_OPEN SPCI_MISC_32(SPCI_FID_SERVICE_HANDLE_OPEN)
#define SPCI_SERVICE_HANDLE_OPEN_NOTIFY_BIT U(1)
#define SPCI_SERVICE_HANDLE_CLOSE SPCI_MISC_32(SPCI_FID_SERVICE_HANDLE_CLOSE)
#define SPCI_SERVICE_MEM_REGISTER_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_MEM_REGISTER)
#define SPCI_SERVICE_MEM_REGISTER_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_MEM_REGISTER)
#define SPCI_SERVICE_MEM_UNREGISTER_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_MEM_UNREGISTER)
#define SPCI_SERVICE_MEM_UNREGISTER_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_MEM_UNREGISTER)
#define SPCI_SERVICE_MEM_PUBLISH_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_MEM_PUBLISH)
#define SPCI_SERVICE_MEM_PUBLISH_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_MEM_PUBLISH)
#define SPCI_SERVICE_REQUEST_BLOCKING_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_REQUEST_BLOCKING)
#define SPCI_SERVICE_REQUEST_BLOCKING_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_REQUEST_BLOCKING)
#define SPCI_SERVICE_REQUEST_START_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_REQUEST_START)
#define SPCI_SERVICE_REQUEST_START_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_REQUEST_START)
#define SPCI_SERVICE_GET_RESPONSE_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_GET_RESPONSE)
#define SPCI_SERVICE_GET_RESPONSE_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_GET_RESPONSE)
#define SPCI_SERVICE_RESET_CLIENT_STATE_AARCH32 SPCI_MISC_32(SPCI_FID_SERVICE_RESET_CLIENT_STATE)
#define SPCI_SERVICE_RESET_CLIENT_STATE_AARCH64 SPCI_MISC_64(SPCI_FID_SERVICE_RESET_CLIENT_STATE)
#define SPCI_SERVICE_TUN_REQUEST_START_AARCH32 SPCI_TUN_32(SPCI_FID_SERVICE_TUN_REQUEST_START)
#define SPCI_SERVICE_TUN_REQUEST_START_AARCH64 SPCI_TUN_64(SPCI_FID_SERVICE_TUN_REQUEST_START)
#define SPCI_SERVICE_REQUEST_RESUME_AARCH32 SPCI_TUN_32(SPCI_FID_SERVICE_REQUEST_RESUME)
#define SPCI_SERVICE_REQUEST_RESUME_AARCH64 SPCI_TUN_64(SPCI_FID_SERVICE_REQUEST_RESUME)
#define SPCI_SERVICE_TUN_REQUEST_BLOCKING_AARCH32 SPCI_TUN_32(SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING)
#define SPCI_SERVICE_TUN_REQUEST_BLOCKING_AARCH64 SPCI_TUN_64(SPCI_FID_SERVICE_TUN_REQUEST_BLOCKING)
/* SPCI error codes. */
#define SPCI_SUCCESS 0
#define SPCI_NOT_SUPPORTED -1
#define SPCI_INVALID_PARAMETER -2
#define SPCI_NO_MEMORY -3
#define SPCI_BUSY -4
#define SPCI_QUEUED -5
#define SPCI_DENIED -6
#define SPCI_NOT_PRESENT -7
#endif /* SPCI_SVC_H */
......@@ -7,8 +7,6 @@
#ifndef SPM_SVC_H
#define SPM_SVC_H
#if SPM_MM
#include <lib/utils_def.h>
#define SPM_VERSION_MAJOR U(0)
......@@ -61,16 +59,12 @@
#define SPM_DENIED -3
#define SPM_NO_MEMORY -5
#endif /* SPM_MM */
#ifndef __ASSEMBLER__
#include <stdint.h>
int32_t spm_setup(void);
#if SPM_MM
uint64_t spm_smc_handler(uint32_t smc_fid,
uint64_t x1,
uint64_t x2,
......@@ -83,8 +77,6 @@ uint64_t spm_smc_handler(uint32_t smc_fid,
/* Helper to enter a Secure Partition */
uint64_t spm_sp_call(uint32_t smc_fid, uint64_t x1, uint64_t x2, uint64_t x3);
#endif /* SPM_MM */
#endif /* __ASSEMBLER__ */
#endif /* SPM_SVC_H */
/*
* Copyright (c) 2018-2019, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPRT_SVC_H
#define SPRT_SVC_H
#include <lib/smccc.h>
#include <lib/utils_def.h>
/* SPRT_VERSION helpers */
#define SPRT_VERSION_MAJOR U(0)
#define SPRT_VERSION_MAJOR_SHIFT 16
#define SPRT_VERSION_MAJOR_MASK U(0x7FFF)
#define SPRT_VERSION_MINOR U(1)
#define SPRT_VERSION_MINOR_SHIFT 0
#define SPRT_VERSION_MINOR_MASK U(0xFFFF)
#define SPRT_VERSION_FORM(major, minor) ((((major) & SPRT_VERSION_MAJOR_MASK) \
<< SPRT_VERSION_MAJOR_SHIFT) | \
((minor) & SPRT_VERSION_MINOR_MASK))
#define SPRT_VERSION_COMPILED SPRT_VERSION_FORM(SPRT_VERSION_MAJOR, \
SPRT_VERSION_MINOR)
/* SPRT function IDs */
#define SPRT_FID_VERSION U(0x0)
#define SPRT_FID_PUT_RESPONSE U(0x1)
#define SPRT_FID_YIELD U(0x5)
#define SPRT_FID_PANIC U(0x7)
#define SPRT_FID_MEMORY_PERM_ATTR_GET U(0xB)
#define SPRT_FID_MEMORY_PERM_ATTR_SET U(0xC)
#define SPRT_FID_MASK U(0xFF)
/* Definitions to build the complete SMC ID */
#define OEN_SPRT_START U(0x20)
#define OEN_SPRT_END U(0x2F)
#define SPRT_SMC_64(sprt_fid) ((OEN_SPRT_START << FUNCID_OEN_SHIFT) | \
(U(1) << 31) | ((sprt_fid) & SPRT_FID_MASK) | \
(SMC_64 << FUNCID_CC_SHIFT))
#define SPRT_SMC_32(sprt_fid) ((OEN_SPRT_START << FUNCID_OEN_SHIFT) | \
(U(1) << 31) | ((sprt_fid) & SPRT_FID_MASK) | \
(SMC_32 << FUNCID_CC_SHIFT))
/* Complete SMC IDs */
#define SPRT_VERSION SPRT_SMC_32(SPRT_FID_VERSION)
#define SPRT_PUT_RESPONSE_AARCH64 SPRT_SMC_64(SPRT_FID_PUT_RESPONSE)
#define SPRT_YIELD_AARCH64 SPRT_SMC_64(SPRT_FID_YIELD)
#define SPRT_PANIC_AARCH64 SPRT_SMC_64(SPRT_FID_PANIC)
#define SPRT_MEMORY_PERM_ATTR_GET_AARCH64 SPRT_SMC_64(SPRT_FID_MEMORY_PERM_ATTR_GET)
#define SPRT_MEMORY_PERM_ATTR_SET_AARCH64 SPRT_SMC_64(SPRT_FID_MEMORY_PERM_ATTR_SET)
/* Defines used by SPRT_MEMORY_PERM_ATTR_{GET,SET}_AARCH64 */
#define SPRT_MEMORY_PERM_ATTR_RO U(0)
#define SPRT_MEMORY_PERM_ATTR_RW U(1)
#define SPRT_MEMORY_PERM_ATTR_RO_EXEC U(2)
/* U(3) is reserved */
#define SPRT_MEMORY_PERM_ATTR_MASK U(3)
#define SPRT_MEMORY_PERM_ATTR_SHIFT 3
/* SPRT error codes. */
#define SPRT_SUCCESS 0
#define SPRT_NOT_SUPPORTED -1
#define SPRT_INVALID_PARAMETER -2
#endif /* SPRT_SVC_H */
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <errno.h>
#include <stddef.h>
#include <stdint.h>
#include "sprt_common.h"
#include "sprt_queue.h"
void sprt_initialize_queues(void *buffer_base, size_t buffer_size)
{
/* Initialize queue for blocking messages */
void *blocking_base = buffer_base;
uint32_t blocking_num = 4U;
size_t blocking_size = SPRT_QUEUE_HEADER_SIZE +
SPRT_QUEUE_ENTRY_MSG_SIZE * blocking_num;
sprt_queue_init(blocking_base, blocking_num, SPRT_QUEUE_ENTRY_MSG_SIZE);
/* Initialize queue for non-blocking messages */
void *non_blocking_base = (void *)((uintptr_t)blocking_base + blocking_size);
size_t non_blocking_size = buffer_size - blocking_size;
uint32_t non_blocking_num = (non_blocking_size - SPRT_QUEUE_HEADER_SIZE) /
SPRT_QUEUE_ENTRY_MSG_SIZE;
sprt_queue_init(non_blocking_base, non_blocking_num, SPRT_QUEUE_ENTRY_MSG_SIZE);
}
int sprt_push_message(void *buffer_base,
const struct sprt_queue_entry_message *message,
int queue_num)
{
struct sprt_queue *q = buffer_base;
while (queue_num-- > 0) {
uintptr_t next_addr = (uintptr_t)q + sizeof(struct sprt_queue) +
q->entry_num * q->entry_size;
q = (struct sprt_queue *) next_addr;
}
return sprt_queue_push(q, message);
}
#
# Copyright (c) 2018, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
SPRT_LIB_SOURCES := $(addprefix lib/sprt/, \
sprt_host.c \
sprt_queue.c)
SPRT_LIB_INCLUDES := -Iinclude/lib/sprt/
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <assert.h>
#include <errno.h>
#include <stdint.h>
#include <string.h>
#include "sprt_queue.h"
void sprt_queue_init(void *queue_base, uint32_t entry_num, uint32_t entry_size)
{
assert(queue_base != NULL);
assert(entry_size > 0U);
assert(entry_num > 0U);
struct sprt_queue *queue = (struct sprt_queue *)queue_base;
queue->entry_num = entry_num;
queue->entry_size = entry_size;
queue->idx_write = 0U;
queue->idx_read = 0U;
memset(queue->data, 0, entry_num * entry_size);
}
int sprt_queue_is_empty(void *queue_base)
{
assert(queue_base != NULL);
struct sprt_queue *queue = (struct sprt_queue *)queue_base;
return (queue->idx_write == queue->idx_read);
}
int sprt_queue_is_full(void *queue_base)
{
assert(queue_base != NULL);
struct sprt_queue *queue = (struct sprt_queue *)queue_base;
uint32_t idx_next_write = (queue->idx_write + 1) % queue->entry_num;
return (idx_next_write == queue->idx_read);
}
int sprt_queue_push(void *queue_base, const void *entry)
{
assert(entry != NULL);
assert(queue_base != NULL);
if (sprt_queue_is_full(queue_base) != 0) {
return -ENOMEM;
}
struct sprt_queue *queue = (struct sprt_queue *)queue_base;
uint8_t *dst_entry = &queue->data[queue->entry_size * queue->idx_write];
memcpy(dst_entry, entry, queue->entry_size);
/*
* Make sure that the message data is visible before increasing the
* counter of available messages.
*/
__asm__ volatile("dmb st" ::: "memory");
queue->idx_write = (queue->idx_write + 1) % queue->entry_num;
__asm__ volatile("dmb st" ::: "memory");
return 0;
}
int sprt_queue_pop(void *queue_base, void *entry)
{
assert(entry != NULL);
assert(queue_base != NULL);
if (sprt_queue_is_empty(queue_base) != 0) {
return -ENOENT;
}
struct sprt_queue *queue = (struct sprt_queue *)queue_base;
uint8_t *src_entry = &queue->data[queue->entry_size * queue->idx_read];
memcpy(entry, src_entry, queue->entry_size);
/*
* Make sure that the message data is visible before increasing the
* counter of read messages.
*/
__asm__ volatile("dmb st" ::: "memory");
queue->idx_read = (queue->idx_read + 1) % queue->entry_num;
__asm__ volatile("dmb st" ::: "memory");
return 0;
}
/*
* Copyright (c) 2018, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef SPRT_QUEUE_H
#define SPRT_QUEUE_H
#include <stdint.h>
/* Struct that defines a queue. Not to be used directly. */
struct __attribute__((__packed__)) sprt_queue {
uint32_t entry_num; /* Number of entries */
uint32_t entry_size; /* Size of an entry */
uint32_t idx_write; /* Index of first empty entry */
uint32_t idx_read; /* Index of first entry to read */
uint8_t data[0]; /* Start of data */
};
#define SPRT_QUEUE_HEADER_SIZE (sizeof(struct sprt_queue))
/*
* Initializes a memory region to be used as a queue of the given number of
* entries with the specified size.
*/
void sprt_queue_init(void *queue_base, uint32_t entry_num, uint32_t entry_size);
/* Returns 1 if the queue is empty, 0 otherwise */
int sprt_queue_is_empty(void *queue_base);
/* Returns 1 if the queue is full, 0 otherwise */
int sprt_queue_is_full(void *queue_base);
/*
* Pushes a new entry intro the queue. Returns 0 on success, -ENOMEM if the
* queue is full.
*/
int sprt_queue_push(void *queue_base, const void *entry);
/*
* Pops an entry from the queue. Returns 0 on success, -ENOENT if the queue is
* empty.
*/
int sprt_queue_pop(void *queue_base, void *entry);
#endif /* SPRT_QUEUE_H */
......@@ -178,9 +178,6 @@ RECLAIM_INIT_CODE := 0
# SPD choice
SPD := none
# Enable the SPCI-based Secure Partition Manager implementation
ENABLE_SPM := 0
# Enable the Management Mode (MM)-based Secure Partition Manager implementation
SPM_MM := 0
......
......@@ -99,9 +99,6 @@ const mmap_region_t plat_arm_mmap[] = {
#if SPM_MM
ARM_SP_IMAGE_MMAP,
#endif
#if ENABLE_SPM
PLAT_MAP_SP_PACKAGE_MEM_RW,
#endif
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif
......@@ -129,9 +126,6 @@ const mmap_region_t plat_arm_mmap[] = {
ARM_V2M_MAP_MEM_PROTECT,
#if SPM_MM
ARM_SPM_BUF_EL3_MMAP,
#endif
#if ENABLE_SPM
PLAT_MAP_SP_PACKAGE_MEM_RO,
#endif
{0}
};
......
......@@ -61,7 +61,7 @@
* plat_arm_mmap array defined for each BL stage.
*/
#if defined(IMAGE_BL31)
# if ENABLE_SPM || SPM_MM
# if SPM_MM
# define PLAT_ARM_MMAP_ENTRIES 9
# define MAX_XLAT_TABLES 9
# define PLAT_SP_IMAGE_MMAP_REGIONS 30
......@@ -116,11 +116,7 @@
* calculated using the current BL31 PROGBITS debug size plus the sizes of
* BL2 and BL1-RW
*/
#if ENABLE_SPM
#define PLAT_ARM_MAX_BL31_SIZE UL(0x60000)
#else
#define PLAT_ARM_MAX_BL31_SIZE UL(0x3B000)
#endif
#ifndef __aarch64__
/*
......
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