rcar_gen3: plat: Fix cache line size

The CPU has cache line size of 64 Bytes, fix the cache line size.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>

plat/renesas/rcar/include/platform_def.h

@@ -79,7 +79,7 @@
  *          Cortex-A53
  * L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
  */
-#define PLATFORM_CACHE_LINE_SIZE	128
+#define PLATFORM_CACHE_LINE_SIZE	64
 #define PLATFORM_CLUSTER_COUNT		U(2)
 #define PLATFORM_CLUSTER0_CORE_COUNT	U(4)
 #define PLATFORM_CLUSTER1_CORE_COUNT	U(4)