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Commit 53ff5c79 authored by Marek Vasut's avatar Marek Vasut
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rcar_gen3: plat: Fix cache line size 



The CPU has cache line size of 64 Bytes, fix the cache line size.
Signed-off-by: default avatarMarek Vasut <marek.vasut+renesas@gmail.com>
parent 8a2f1eee
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plat/renesas/rcar/include/platform_def.h
View file @ 53ff5c79
...@@ -79,7 +79,7 @@ ...@@ -79,7 +79,7 @@
* Cortex-A53 * Cortex-A53
* L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way) * L1:I/32KB(16KBx2way) D/32KB(8KBx4way) L2:512KB(32KBx16way)
*/ */
#define PLATFORM_CACHE_LINE_SIZE 128 #define PLATFORM_CACHE_LINE_SIZE 64
#define PLATFORM_CLUSTER_COUNT U(2) #define PLATFORM_CLUSTER_COUNT U(2)
#define PLATFORM_CLUSTER0_CORE_COUNT U(4) #define PLATFORM_CLUSTER0_CORE_COUNT U(4)
#define PLATFORM_CLUSTER1_CORE_COUNT U(4) #define PLATFORM_CLUSTER1_CORE_COUNT U(4)
......
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