Tegra194: support for NVG interface v6.6

This patch updates the NVG interface header file to v6.6.

Change-Id: I2f5df274bf820ba1c5df47d8dcbf7f5f056ff45f
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>

plat/nvidia/tegra/soc/t194/drivers/include/t194_nvg.h

@@ -20,7 +20,7 @@
  */
 enum {
 	TEGRA_NVG_VERSION_MAJOR = 6,
-	TEGRA_NVG_VERSION_MINOR = 4
+	TEGRA_NVG_VERSION_MINOR = 6
 };
 
 typedef enum {
@@ -34,6 +34,10 @@ typedef enum {
 	TEGRA_NVG_CHANNEL_CROSSOVER_CG7_LOWER_BOUND		= 8,
 	TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_REQUEST		= 10,
 	TEGRA_NVG_CHANNEL_CSTATE_STAT_QUERY_VALUE		= 11,
+	TEGRA_NVG_CHANNEL_NUM_CORES				= 20,
+	TEGRA_NVG_CHANNEL_UNIQUE_LOGICAL_ID			= 21,
+	TEGRA_NVG_CHANNEL_LOGICAL_TO_PHYSICAL_MAPPING		= 22,
+	TEGRA_NVG_CHANNEL_LOGICAL_TO_MPIDR			= 23,
 	TEGRA_NVG_CHANNEL_SHUTDOWN				= 42,
 	TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED			= 43,
 	TEGRA_NVG_CHANNEL_ONLINE_CORE				= 44,
@@ -112,8 +116,14 @@ typedef enum {
 	TEGRA_NVG_CORE_WARMRSTREQ = 8
 } tegra_nvg_core_sleep_state_t;
 
+typedef enum {
+	TEGRA_NVG_SHUTDOWN = 0U,
+	TEGRA_NVG_REBOOT = 1U
+} tegra_nvg_shutdown_reboot_state_t;
+
 typedef enum {
 	TEGRA_NVG_CLUSTER_CC0 = 0,
+	TEGRA_NVG_CLUSTER_AUTO_CC1 = 1,
 	TEGRA_NVG_CLUSTER_CC6 = 6
 } tegra_nvg_cluster_sleep_state_t;
 
@@ -128,11 +138,6 @@ typedef enum {
 	TEGRA_NVG_SYSTEM_SC8 = 8
 } tegra_nvg_system_sleep_state_t;
 
-typedef enum {
-    TEGRA_NVG_SHUTDOWN = 0U,
-    TEGRA_NVG_REBOOT = 1U,
-} tegra_nvg_shutdown_reboot_state_t;
-
 // ---------------------------------------------------------------------------
 // NVG Data subformats
 // ---------------------------------------------------------------------------
@@ -217,7 +222,20 @@ typedef union {
 		uint32_t update_system			: 1;
 		uint32_t reserved_30_24			: 7;
 		uint32_t update_wake_mask		: 1;
-		uint32_t wake_mask	: 32;
+		union {
+			uint32_t flat				: 32;
+			struct {
+				uint32_t vfiq			: 1;
+				uint32_t virq			: 1;
+				uint32_t fiq			: 1;
+				uint32_t irq			: 1;
+				uint32_t serror			: 1;
+				uint32_t reserved_10_5	: 6;
+				uint32_t fiqout			: 1;
+				uint32_t irqout			: 1;
+				uint32_t reserved_31_13	: 19;
+			} carmel;
+		} wake_mask;
 	} bits;
 } nvg_cstate_info_channel_t;
 
@@ -239,6 +257,52 @@ typedef union {
 	} bits;
 } nvg_cstate_stat_query_channel_t;
 
+typedef union {
+	uint64_t flat;
+	struct nvg_num_cores_channel_t {
+		uint32_t num_cores		: 4;
+		uint32_t reserved_31_4	: 28;
+		uint32_t reserved_63_32 : 32;
+	} bits;
+} nvg_num_cores_channel_t;
+
+typedef union {
+	uint64_t flat;
+	struct nvg_unique_logical_id_channel_t {
+		uint32_t unique_core_id	: 3;
+		uint32_t reserved_31_3	: 29;
+		uint32_t reserved_63_32 : 32;
+	} bits;
+} nvg_unique_logical_id_channel_t;
+
+typedef union {
+	uint64_t flat;
+	struct nvg_logical_to_physical_mappings_channel_t {
+		uint32_t lcore0_pcore_id	: 4;
+		uint32_t lcore1_pcore_id	: 4;
+		uint32_t lcore2_pcore_id	: 4;
+		uint32_t lcore3_pcore_id	: 4;
+		uint32_t lcore4_pcore_id	: 4;
+		uint32_t lcore5_pcore_id	: 4;
+		uint32_t lcore6_pcore_id	: 4;
+		uint32_t lcore7_pcore_id	: 4;
+		uint32_t reserved_63_32		: 32;
+	} bits;
+} nvg_logical_to_physical_mappings_channel_t;
+
+typedef union {
+	uint64_t flat;
+	struct nvg_logical_to_mpidr_channel_write_t {
+		uint32_t lcore_id		: 3;
+		uint32_t reserved_31_3	: 29;
+		uint32_t reserved_63_32	: 32;
+	} write;
+	struct nvg_logical_to_mpidr_channel_read_t {
+		uint32_t mpidr			: 32;
+		uint32_t reserved_63_32	: 32;
+	} read;
+} nvg_logical_to_mpidr_channel_t;
+
 typedef union {
 	uint64_t flat;
 	struct nvg_is_sc7_allowed_channel_t {
@@ -260,8 +324,8 @@ typedef union {
 typedef union {
 	uint64_t flat;
 	struct nvg_cc3_control_channel_t {
-		uint32_t freq_req	: 8;
-		uint32_t reserved_30_8	: 23;
+		uint32_t freq_req	: 9;
+		uint32_t reserved_30_9	: 22;
 		uint32_t enable		: 1;
 		uint32_t reserved_63_32	: 32;
 	} bits;
@@ -335,4 +399,26 @@ typedef union {
 	} bits;
 } nvg_shutdown_t;
 
+typedef union {
+	uint64_t flat;
+	struct nvg_debug_config_channel_t {
+		uint32_t enter_debug_state_on_mca : 1;
+		uint32_t reserved_31_1            : 31;
+		uint32_t reserved_63_32           : 32;
+	} bits;
+} nvg_debug_config_t;
+
+typedef union {
+	uint64_t flat;
+	struct nvg_hsm_error_ctrl_channel_t {
+		uint32_t uncorr			: 1;
+		uint32_t corr			: 1;
+		uint32_t reserved_31_2	: 30;
+		uint32_t reserved_63_32	: 32;
+	} bits;
+} nvg_hsm_error_ctrl_channel_t;
+
+extern nvg_debug_config_t nvg_debug_config;
+
 #endif
+