Tegra194: smmu: add PCIE0R1 mc reg to system suspend save list

PCIE0R1 security and override registers need to be preserved across
system suspend. Adding them to system suspend save register list.
Due to addition of above registers, increasing context save memory
by 2 bytes.

Change-Id: I1b3a56aee31f3c11e3edc2fb0a6da146eec1a30d
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>

plat/nvidia/tegra/soc/t194/plat_smmu.c

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -139,6 +139,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = {
 	mc_make_sid_security_cfg(NVENCSRD1),
 	mc_make_sid_security_cfg(NVENC1SRD1),
 	mc_make_sid_security_cfg(ISPRA1),
+	mc_make_sid_security_cfg(PCIE0R1),
 	mc_make_sid_security_cfg(MIU0R),
 	mc_make_sid_security_cfg(MIU0W),
 	mc_make_sid_security_cfg(MIU1R),
@@ -262,6 +263,7 @@ static __attribute__((aligned(16))) smmu_regs_t tegra194_smmu_context[] = {
 	mc_make_sid_override_cfg(NVENCSRD1),
 	mc_make_sid_override_cfg(NVENC1SRD1),
 	mc_make_sid_override_cfg(ISPRA1),
+	mc_make_sid_override_cfg(PCIE0R1),
 	mc_make_sid_override_cfg(MIU0R),
 	mc_make_sid_override_cfg(MIU0W),
 	mc_make_sid_override_cfg(MIU1R),

plat/nvidia/tegra/soc/t194/plat_trampoline.S

 /*
- * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2019-2020, NVIDIA CORPORATION. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -12,7 +12,7 @@
 
 #define TEGRA194_STATE_SYSTEM_SUSPEND	0x5C7
 #define TEGRA194_STATE_SYSTEM_RESUME	0x600D
-#define TEGRA194_SMMU_CTX_SIZE		0x80B
+#define TEGRA194_SMMU_CTX_SIZE		0x80D
 
 	.align 4
 	.globl	tegra194_cpu_reset_handler