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Commit 55a85659 authored by danh-arm's avatar danh-arm
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Merge pull request #552 from antonio-nino-diaz-arm/an/cache-dts 

Add cache topology info to FVP DTBs
parents 63a6d09a b1063d95
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fdts/fvp-base-gicv2-psci.dts
View file @ 55a85659
/* /*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -125,6 +125,7 @@ ...@@ -125,6 +125,7 @@
reg = <0x0 0x0>; reg = <0x0 0x0>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU1:cpu@1 { CPU1:cpu@1 {
...@@ -133,6 +134,7 @@ ...@@ -133,6 +134,7 @@
reg = <0x0 0x1>; reg = <0x0 0x1>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU2:cpu@2 { CPU2:cpu@2 {
...@@ -141,6 +143,7 @@ ...@@ -141,6 +143,7 @@
reg = <0x0 0x2>; reg = <0x0 0x2>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU3:cpu@3 { CPU3:cpu@3 {
...@@ -149,6 +152,7 @@ ...@@ -149,6 +152,7 @@
reg = <0x0 0x3>; reg = <0x0 0x3>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU4:cpu@100 { CPU4:cpu@100 {
...@@ -157,6 +161,7 @@ ...@@ -157,6 +161,7 @@
reg = <0x0 0x100>; reg = <0x0 0x100>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU5:cpu@101 { CPU5:cpu@101 {
...@@ -165,6 +170,7 @@ ...@@ -165,6 +170,7 @@
reg = <0x0 0x101>; reg = <0x0 0x101>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU6:cpu@102 { CPU6:cpu@102 {
...@@ -173,6 +179,7 @@ ...@@ -173,6 +179,7 @@
reg = <0x0 0x102>; reg = <0x0 0x102>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU7:cpu@103 { CPU7:cpu@103 {
...@@ -181,6 +188,11 @@ ...@@ -181,6 +188,11 @@
reg = <0x0 0x103>; reg = <0x0 0x103>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
}; };
}; };
......
fdts/fvp-base-gicv2legacy-psci.dts
View file @ 55a85659
/* /*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -125,6 +125,7 @@ ...@@ -125,6 +125,7 @@
reg = <0x0 0x0>; reg = <0x0 0x0>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU1:cpu@1 { CPU1:cpu@1 {
...@@ -133,6 +134,7 @@ ...@@ -133,6 +134,7 @@
reg = <0x0 0x1>; reg = <0x0 0x1>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU2:cpu@2 { CPU2:cpu@2 {
...@@ -141,6 +143,7 @@ ...@@ -141,6 +143,7 @@
reg = <0x0 0x2>; reg = <0x0 0x2>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU3:cpu@3 { CPU3:cpu@3 {
...@@ -149,6 +152,7 @@ ...@@ -149,6 +152,7 @@
reg = <0x0 0x3>; reg = <0x0 0x3>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU4:cpu@100 { CPU4:cpu@100 {
...@@ -157,6 +161,7 @@ ...@@ -157,6 +161,7 @@
reg = <0x0 0x100>; reg = <0x0 0x100>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU5:cpu@101 { CPU5:cpu@101 {
...@@ -165,6 +170,7 @@ ...@@ -165,6 +170,7 @@
reg = <0x0 0x101>; reg = <0x0 0x101>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU6:cpu@102 { CPU6:cpu@102 {
...@@ -173,6 +179,7 @@ ...@@ -173,6 +179,7 @@
reg = <0x0 0x102>; reg = <0x0 0x102>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU7:cpu@103 { CPU7:cpu@103 {
...@@ -181,6 +188,11 @@ ...@@ -181,6 +188,11 @@
reg = <0x0 0x103>; reg = <0x0 0x103>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
}; };
}; };
......
fdts/fvp-base-gicv3-psci.dts
View file @ 55a85659
/* /*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -123,6 +123,7 @@ ...@@ -123,6 +123,7 @@
reg = <0x0 0x0>; reg = <0x0 0x0>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU1:cpu@1 { CPU1:cpu@1 {
...@@ -131,6 +132,7 @@ ...@@ -131,6 +132,7 @@
reg = <0x0 0x1>; reg = <0x0 0x1>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU2:cpu@2 { CPU2:cpu@2 {
...@@ -139,6 +141,7 @@ ...@@ -139,6 +141,7 @@
reg = <0x0 0x2>; reg = <0x0 0x2>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU3:cpu@3 { CPU3:cpu@3 {
...@@ -147,6 +150,7 @@ ...@@ -147,6 +150,7 @@
reg = <0x0 0x3>; reg = <0x0 0x3>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU4:cpu@100 { CPU4:cpu@100 {
...@@ -155,6 +159,7 @@ ...@@ -155,6 +159,7 @@
reg = <0x0 0x100>; reg = <0x0 0x100>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU5:cpu@101 { CPU5:cpu@101 {
...@@ -163,6 +168,7 @@ ...@@ -163,6 +168,7 @@
reg = <0x0 0x101>; reg = <0x0 0x101>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU6:cpu@102 { CPU6:cpu@102 {
...@@ -171,6 +177,7 @@ ...@@ -171,6 +177,7 @@
reg = <0x0 0x102>; reg = <0x0 0x102>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU7:cpu@103 { CPU7:cpu@103 {
...@@ -179,6 +186,11 @@ ...@@ -179,6 +186,11 @@
reg = <0x0 0x103>; reg = <0x0 0x103>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
}; };
}; };
......
fdts/fvp-foundation-gicv2-psci.dts
View file @ 55a85659
/* /*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -110,6 +110,7 @@ ...@@ -110,6 +110,7 @@
reg = <0x0 0x0>; reg = <0x0 0x0>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU1:cpu@1 { CPU1:cpu@1 {
...@@ -118,6 +119,7 @@ ...@@ -118,6 +119,7 @@
reg = <0x0 0x1>; reg = <0x0 0x1>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU2:cpu@2 { CPU2:cpu@2 {
...@@ -126,6 +128,7 @@ ...@@ -126,6 +128,7 @@
reg = <0x0 0x2>; reg = <0x0 0x2>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU3:cpu@3 { CPU3:cpu@3 {
...@@ -134,6 +137,11 @@ ...@@ -134,6 +137,11 @@
reg = <0x0 0x3>; reg = <0x0 0x3>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
}; };
}; };
......
fdts/fvp-foundation-gicv2legacy-psci.dts
View file @ 55a85659
/* /*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -110,6 +110,7 @@ ...@@ -110,6 +110,7 @@
reg = <0x0 0x0>; reg = <0x0 0x0>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU1:cpu@1 { CPU1:cpu@1 {
...@@ -118,6 +119,7 @@ ...@@ -118,6 +119,7 @@
reg = <0x0 0x1>; reg = <0x0 0x1>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU2:cpu@2 { CPU2:cpu@2 {
...@@ -126,6 +128,7 @@ ...@@ -126,6 +128,7 @@
reg = <0x0 0x2>; reg = <0x0 0x2>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU3:cpu@3 { CPU3:cpu@3 {
...@@ -134,6 +137,11 @@ ...@@ -134,6 +137,11 @@
reg = <0x0 0x3>; reg = <0x0 0x3>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
}; };
}; };
......
fdts/fvp-foundation-gicv3-psci.dts
View file @ 55a85659
/* /*
* Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2013-2016, ARM Limited and Contributors. All rights reserved.
* *
* Redistribution and use in source and binary forms, with or without * Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met: * modification, are permitted provided that the following conditions are met:
...@@ -108,6 +108,7 @@ ...@@ -108,6 +108,7 @@
reg = <0x0 0x0>; reg = <0x0 0x0>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU1:cpu@1 { CPU1:cpu@1 {
...@@ -116,6 +117,7 @@ ...@@ -116,6 +117,7 @@
reg = <0x0 0x1>; reg = <0x0 0x1>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU2:cpu@2 { CPU2:cpu@2 {
...@@ -124,6 +126,7 @@ ...@@ -124,6 +126,7 @@
reg = <0x0 0x2>; reg = <0x0 0x2>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
}; };
CPU3:cpu@3 { CPU3:cpu@3 {
...@@ -132,6 +135,11 @@ ...@@ -132,6 +135,11 @@
reg = <0x0 0x3>; reg = <0x0 0x3>;
enable-method = "psci"; enable-method = "psci";
cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>; cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
next-level-cache = <&L2_0>;
};
L2_0: l2-cache0 {
compatible = "cache";
}; };
}; };
......
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