ddr: a80x0: add DDR 32-bit mode support

This commit introduces 32-bit DDR topology map initialization.
For that purpose a new DDR32 build flag is added, with
according documentation update.

Change-Id: I169ff358c2923afd984e27bc126dc551dcaefc01
Signed-off-by: Alex Leibovich <alexl@marvell.com>

docs/plat/marvell/armada/build.rst

@@ -194,6 +194,10 @@ Special Build Flags
     can interrupt UART recovery process). This MACRO definition is set in
     ``plat/marvell/armada/a8k/common/include/platform_def.h`` file.
 
+- DDR32
+    In order to work in 32bit DDR, instead of the default 64bit ECC DDR,
+    this flag should be set to 1.
+
 For more information about build options, please refer to the
 :ref:`Build Options` document.
 

plat/marvell/armada/a8k/a80x0/board/dram_port.c

@@ -52,8 +52,13 @@ static struct mv_ddr_topology_map board_topology_map = {
 	   MV_DDR_FREQ_SAR,		/* frequency */
 	   0, 0,			/* cas_l, cas_wl */
 	   MV_DDR_TEMP_LOW} },		/* temperature */
+#if DDR32
+	MV_DDR_32BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
+	MV_DDR_CFG_DEFAULT,		/* ddr configuration data source */
+#else
 	MV_DDR_64BIT_ECC_PUP8_BUS_MASK, /* subphys mask */
 	MV_DDR_CFG_SPD,			/* ddr configuration data source */
+#endif
 	{ {0} },			/* raw spd data */
 	{0},				/* timing parameters */
 	{				/* electrical configuration */

plat/marvell/marvell.mk

@@ -16,6 +16,10 @@ $(eval $(call add_define,MARVELL_SECURE_BOOT))
 PALLADIUM			:= 0
 $(eval $(call add_define,PALLADIUM))
 
+# Set board to work with DDR 32bit
+DDR32				:= 0
+$(eval $(call add_define,DDR32))
+
 ifeq (${MARVELL_SECURE_BOOT},1)
 DOIMAGE_SEC_FLAGS := -c $(DOIMAGE_SEC)
 DOIMAGE_LIBS_CHECK = \