Commit 5c77ec4b authored by Jon Medhurst's avatar Jon Medhurst Committed by Sandrine Bailleux
Browse files

juno: Port mailbox initialisation



Note, on Juno mailboxes are 16 bytes because any bigger and they would
overlap the memory used for MHU payload data for SCP->AP transfers.
Signed-off-by: default avatarJon Medhurst <tixy@linaro.org>
parent 6ba5c70d
......@@ -67,60 +67,15 @@ cb_panic:
* mailbox.
*
* TODO: Not a good idea to save lr in a temp reg
* TODO: PSYSR is a common register and should be
* accessed using locks. Since its not possible
* to use locks immediately after a cold reset
* we are relying on the fact that after a cold
* reset all cpus will read the same WK field
* -----------------------------------------------------
*/
platform_get_entrypoint: ; .type platform_get_entrypoint, %function
mov x9, x30 // lr
mov x2, x0
ldr x1, =PWRC_BASE
str w2, [x1, #PSYSR_OFF]
ldr w2, [x1, #PSYSR_OFF]
ubfx w2, w2, #PSYSR_WK_SHIFT, #PSYSR_WK_MASK
cbnz w2, warm_reset
mov x0, x2
b exit
warm_reset:
/* ---------------------------------------------
* A per-cpu mailbox is maintained in the tru-
* sted DRAM. Its flushed out of the caches
* after every update using normal memory so
* its safe to read it here with SO attributes
* ---------------------------------------------
*/
ldr x10, =TZDRAM_BASE + MBOX_OFF
bl platform_get_core_pos
lsl x0, x0, #CACHE_WRITEBACK_SHIFT
ldr x0, [x10, x0]
cbz x0, _panic
exit:
ldr x1, =TRUSTED_MAILBOXES_BASE
lsl x0, x0, #TRUSTED_MAILBOX_SHIFT
ldr x0, [x1, x0]
ret x9
_panic: b _panic
/* -----------------------------------------------------
* void platform_mem_init (void);
*
* Zero out the mailbox registers in the TZDRAM. The
* mmu is turned off right now and only the primary can
* ever execute this code. Secondaries will read the
* mailboxes using SO accesses. In short, BL31 will
* update the mailboxes after mapping the tzdram as
* normal memory. It will flush its copy after update.
* BL1 will always read the mailboxes with the MMU off
* -----------------------------------------------------
*/
platform_mem_init: ; .type platform_mem_init, %function
ldr x0, =TZDRAM_BASE + MBOX_OFF
stp xzr, xzr, [x0, #0]
stp xzr, xzr, [x0, #0x10]
stp xzr, xzr, [x0, #0x20]
stp xzr, xzr, [x0, #0x30]
ret
/* -----------------------------------------------------
......@@ -132,7 +87,6 @@ platform_mem_init: ; .type platform_mem_init, %function
*/
platform_cold_boot_init: ; .type platform_cold_boot_init, %function
mov x20, x0
bl platform_mem_init
bl read_mpidr
mov x19, x0
......
......@@ -93,8 +93,9 @@ void disable_mmu(void)
static const mmap_region mmap[] = {
{ TZROM_BASE, TZROM_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
{ MHU_SECURE_BASE, MHU_SECURE_SIZE, (MHU_PAYLOAD_CACHED ? MT_MEMORY : MT_DEVICE)
| MT_RW | MT_SECURE },
// { TZRAM_BASE, TZRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE }, /* configure_mmu() meminfo arg sets subset of this */
{ TZDRAM_BASE, TZDRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE },
{ FLASH_BASE, FLASH_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
{ EMMC_BASE, EMMC_SIZE, MT_MEMORY | MT_RO | MT_SECURE },
{ PSRAM_BASE, PSRAM_SIZE, MT_MEMORY | MT_RW | MT_SECURE }, /* Used for 'TZDRAM' */
......
......@@ -85,8 +85,16 @@
#define TZROM_BASE 0x00000000
#define TZROM_SIZE 0x00010000
#define TZRAM_BASE 0x04000000
#define TZRAM_SIZE 0x00040000
#define MHU_SECURE_BASE 0x04000000
#define MHU_SECURE_SIZE 0x00001000
#define MHU_PAYLOAD_CACHED 0
#define TRUSTED_MAILBOXES_BASE MHU_SECURE_BASE
#define TRUSTED_MAILBOX_SHIFT 4
#define TZRAM_BASE 0x04001000
#define TZRAM_SIZE 0x0003F000
#define FLASH_BASE 0x08000000
#define FLASH_SIZE 0x04000000
......@@ -114,12 +122,6 @@
#define DEVICE1_BASE 0x40000000
#define DEVICE1_SIZE 0x40000000
/* Use PSRAM for 'TZDRAM' */
#define TZDRAM_BASE PSRAM_BASE
#define TZDRAM_SIZE PSRAM_SIZE
#define MBOX_OFF 0x1000
#define AFFMAP_OFF 0x1200
#define DRAM_BASE 0x80000000
#define DRAM_SIZE 0x80000000
......@@ -217,11 +219,6 @@
#ifndef __ASSEMBLY__
typedef volatile struct {
unsigned long value
__attribute__((__aligned__(CACHE_WRITEBACK_GRANULE)));
} mailbox;
/*******************************************************************************
* Function and variable prototypes
******************************************************************************/
......
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