Add workaround for errata 1220197 for Cortex-A76

Streaming store under specific conditions might cause deadlock or data
corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write
streaming to the L2 to prevent this.

Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

docs/cpu-specific-build-macros.rst

@@ -150,6 +150,9 @@ For Cortex-A76, the following errata build flags are defined :
 -  ``ERRATA_A76_1130799``: This applies errata 1130799 workaround to Cortex-A76
    CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
 
+-  ``ERRATA_A76_1220197``: This applies errata 1220197 workaround to Cortex-A76
+   CPU. This needs to be enabled only for revision <= r2p0 of the CPU.
+
 DSU Errata Workarounds
 ----------------------
 

include/lib/cpus/aarch64/cortex_a76.h

@@ -18,6 +18,8 @@
 #define CORTEX_A76_CPUPWRCTLR_EL1	S3_0_C15_C2_7
 #define CORTEX_A76_CPUECTLR_EL1		S3_0_C15_C1_4
 
+#define CORTEX_A76_CPUECTLR_EL1_WS_THR_L2	(ULL(3) << 24)
+
 /*******************************************************************************
  * CPU Auxiliary Control register specific definitions.
  ******************************************************************************/

lib/cpus/aarch64/cortex_a76.S

@@ -217,6 +217,34 @@ func check_errata_1130799
 	b	cpu_rev_var_ls
 endfunc check_errata_1130799
 
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex A76 Errata #1220197.
+	 * This applies only to revision <= r2p0 of Cortex A76.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * --------------------------------------------------
+	 */
+func errata_a76_1220197_wa
+/*
+ * Compare x0 against revision r2p0
+ */
+	mov	x17, x30
+	bl	check_errata_1220197
+	cbz	x0, 1f
+	mrs	x1, CORTEX_A76_CPUECTLR_EL1
+	orr	x1, x1, #CORTEX_A76_CPUECTLR_EL1_WS_THR_L2
+	msr	CORTEX_A76_CPUECTLR_EL1, x1
+	isb
+1:
+	ret	x17
+endfunc errata_a76_1220197_wa
+
+func check_errata_1220197
+	mov	x1, #0x20
+	b	cpu_rev_var_ls
+endfunc check_errata_1220197
+
 func check_errata_cve_2018_3639
 #if WORKAROUND_CVE_2018_3639
 	mov	x0, #ERRATA_APPLIES
@@ -242,11 +270,18 @@ endfunc cortex_a76_disable_wa_cve_2018_3639
 func cortex_a76_reset_func
 	mov	x19, x30
 	bl	cpu_get_rev_var
+	mov	x18, x0
 
 #if ERRATA_A76_1130799
+	mov	x0, x18
 	bl	errata_a76_1130799_wa
 #endif
 
+#if ERRATA_A76_1220197
+	mov	x0, x18
+	bl	errata_a76_1220197_wa
+#endif
+
 #if WORKAROUND_CVE_2018_3639
 	/* If the PE implements SSBS, we don't need the dynamic workaround */
 	mrs	x0, id_aa64pfr1_el1
@@ -310,6 +345,7 @@ func cortex_a76_errata_report
 	 * checking functions of each errata.
 	 */
 	report_errata ERRATA_A76_1130799, cortex_a76, 1130799
+	report_errata ERRATA_A76_1220197, cortex_a76, 1220197
 	report_errata WORKAROUND_CVE_2018_3639, cortex_a76, cve_2018_3639
 	report_errata ERRATA_DSU_936184, cortex_a76, dsu_936184
 

lib/cpus/cpu-ops.mk

@@ -135,6 +135,10 @@ ERRATA_A75_790748	?=0
 # only to revision <= r2p0 of the Cortex A76 cpu.
 ERRATA_A76_1130799	?=0
 
+# Flag to apply erratum 1220197 workaround during reset. This erratum applies
+# only to revision <= r2p0 of the Cortex A76 cpu.
+ERRATA_A76_1220197	?=0
+
 # Flag to apply T32 CLREX workaround during reset. This erratum applies
 # only to r0p0 and r1p0 of the Neoverse N1 cpu.
 ERRATA_N1_1043202	?=1
@@ -220,6 +224,10 @@ $(eval $(call add_define,ERRATA_A75_790748))
 $(eval $(call assert_boolean,ERRATA_A76_1130799))
 $(eval $(call add_define,ERRATA_A76_1130799))
 
+# Process ERRATA_A76_1220197 flag
+$(eval $(call assert_boolean,ERRATA_A76_1220197))
+$(eval $(call add_define,ERRATA_A76_1220197))
+
 # Process ERRATA_N1_1043202 flag
 $(eval $(call assert_boolean,ERRATA_N1_1043202))
 $(eval $(call add_define,ERRATA_N1_1043202))