Commit 5ea0b028 authored by Varun Wadekar's avatar Varun Wadekar
Browse files

Tegra: handler for per-soc early setup



This patch adds a weak handler for early platform setup which
can be overriden by the soc-specific handlers to perform any
early setup tasks.

Change-Id: I1a7a98d59b2332a3030c6dca5a9b7be977177326
Signed-off-by: default avatarVarun Wadekar <vwadekar@nvidia.com>
parent 939dcf25
...@@ -79,6 +79,17 @@ static plat_params_from_bl2_t plat_bl31_params_from_bl2 = { ...@@ -79,6 +79,17 @@ static plat_params_from_bl2_t plat_bl31_params_from_bl2 = {
******************************************************************************/ ******************************************************************************/
extern uint64_t ns_image_entrypoint; extern uint64_t ns_image_entrypoint;
/*******************************************************************************
* The following platform setup functions are weakly defined. They
* provide typical implementations that will be overridden by a SoC.
******************************************************************************/
#pragma weak plat_early_platform_setup
void plat_early_platform_setup(void)
{
; /* do nothing */
}
/******************************************************************************* /*******************************************************************************
* Return a pointer to the 'entry_point_info' structure of the next image for * Return a pointer to the 'entry_point_info' structure of the next image for
* security state specified. BL33 corresponds to the non-secure image type * security state specified. BL33 corresponds to the non-secure image type
...@@ -160,6 +171,9 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2, ...@@ -160,6 +171,9 @@ void bl31_early_platform_setup(bl31_params_t *from_bl2,
/* Initialise crash console */ /* Initialise crash console */
plat_crash_console_init(); plat_crash_console_init();
/* Early platform setup for Tegra SoCs */
plat_early_platform_setup();
INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ? INFO("BL3-1: Boot CPU: %s Processor [%lx]\n", (impl == DENVER_IMPL) ?
"Denver" : "ARM", read_mpidr()); "Denver" : "ARM", read_mpidr());
} }
......
...@@ -83,6 +83,7 @@ int tegra_prepare_cpu_on_finish(unsigned long mpidr); ...@@ -83,6 +83,7 @@ int tegra_prepare_cpu_on_finish(unsigned long mpidr);
/* Declarations for tegra_bl31_setup.c */ /* Declarations for tegra_bl31_setup.c */
plat_params_from_bl2_t *bl31_get_plat_params(void); plat_params_from_bl2_t *bl31_get_plat_params(void);
int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes); int bl31_check_ns_address(uint64_t base, uint64_t size_in_bytes);
void plat_early_platform_setup(void);
/* Declarations for tegra_delay_timer.c */ /* Declarations for tegra_delay_timer.c */
void tegra_delay_timer_init(void); void tegra_delay_timer_init(void);
......
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