Rename Cortex Hercules AE to Cortex 78 AE

Change-Id: Ic0ca51a855660509264ff0d084c068e1421ad09a
Signed-off-by: Jimmy Brisson <jimmy.brisson@arm.com>

include/lib/cpus/aarch64/cortex_hercules_ae.h → include/lib/cpus/aarch64/cortex_a78_ae.h

@@ -4,11 +4,11 @@
  * SPDX-License-Identifier: BSD-3-Clause
  */
 
-#ifndef CORTEX_HERCULES_AE_H
-#define CORTEX_HERCULES_AE_H
+#ifndef CORTEX_A78_AE_H
+#define CORTEX_A78_AE_H
 
 #include <cortex_a78.h>
 
-#define CORTEX_HERCULES_AE_MIDR U(0x410FD420)
+#define CORTEX_A78_AE_MIDR U(0x410FD420)
 
-#endif /* CORTEX_HERCULES_AE_H */
+#endif /* CORTEX_A78_AE_H */

lib/cpus/aarch64/cortex_hercules_ae.S → lib/cpus/aarch64/cortex_a78_ae.S

@@ -7,21 +7,21 @@
 #include <arch.h>
 #include <asm_macros.S>
 #include <common/bl_common.h>
-#include <cortex_hercules_ae.h>
+#include <cortex_a78_ae.h>
 #include <cpu_macros.S>
 #include <plat_macros.S>
 
 /* Hardware handled coherency */
 #if HW_ASSISTED_COHERENCY == 0
-#error "cortex_hercules_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
+#error "cortex_a78_ae must be compiled with HW_ASSISTED_COHERENCY enabled"
 #endif
 
 	/* -------------------------------------------------
-	 * The CPU Ops reset function for Cortex-Hercules-AE
+	 * The CPU Ops reset function for Cortex-A78-AE
 	 * -------------------------------------------------
 	 */
 #if ENABLE_AMU
-func cortex_hercules_ae_reset_func
+func cortex_a78_ae_reset_func
 	/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
 	mrs	x0, actlr_el3
 	bic	x0, x0, #CORTEX_A78_ACTLR_TAM_BIT
@@ -42,14 +42,14 @@ func cortex_hercules_ae_reset_func
 	isb
 
 	ret
-endfunc cortex_hercules_ae_reset_func
+endfunc cortex_a78_ae_reset_func
 #endif
 
 	/* -------------------------------------------------------
 	 * HW will do the cache maintenance while powering down
 	 * -------------------------------------------------------
 	 */
-func cortex_hercules_ae_core_pwr_dwn
+func cortex_a78_ae_core_pwr_dwn
 	/* -------------------------------------------------------
 	 * Enable CPU power down bit in power control register
 	 * -------------------------------------------------------
@@ -59,19 +59,19 @@ func cortex_hercules_ae_core_pwr_dwn
 	msr	CORTEX_A78_CPUPWRCTLR_EL1, x0
 	isb
 	ret
-endfunc cortex_hercules_ae_core_pwr_dwn
+endfunc cortex_a78_ae_core_pwr_dwn
 
 	/*
-	 * Errata printing function for cortex_hercules_ae. Must follow AAPCS.
+	 * Errata printing function for cortex_a78_ae. Must follow AAPCS.
 	 */
 #if REPORT_ERRATA
-func cortex_hercules_ae_errata_report
+func cortex_a78_ae_errata_report
 	ret
-endfunc cortex_hercules_ae_errata_report
+endfunc cortex_a78_ae_errata_report
 #endif
 
 	/* -------------------------------------------------------
-	 * This function provides cortex_hercules_ae specific
+	 * This function provides cortex_a78_ae specific
 	 * register information for crash reporting.
 	 * It needs to return with x6 pointing to
 	 * a list of register names in ascii and
@@ -79,22 +79,22 @@ endfunc cortex_hercules_ae_errata_report
 	 * reported.
 	 * -------------------------------------------------------
 	 */
-.section .rodata.cortex_hercules_ae_regs, "aS"
-cortex_hercules_ae_regs:  /* The ascii list of register names to be reported */
+.section .rodata.cortex_a78_ae_regs, "aS"
+cortex_a78_ae_regs:  /* The ascii list of register names to be reported */
 	.asciz	"cpuectlr_el1", ""
 
-func cortex_hercules_ae_cpu_reg_dump
-	adr	x6, cortex_hercules_ae_regs
+func cortex_a78_ae_cpu_reg_dump
+	adr	x6, cortex_a78_ae_regs
 	mrs	x8, CORTEX_A78_CPUECTLR_EL1
 	ret
-endfunc cortex_hercules_ae_cpu_reg_dump
+endfunc cortex_a78_ae_cpu_reg_dump
 
 #if ENABLE_AMU
-#define HERCULES_AE_RESET_FUNC cortex_hercules_ae_reset_func
+#define A78_AE_RESET_FUNC cortex_a78_ae_reset_func
 #else
-#define HERCULES_AE_RESET_FUNC CPU_NO_RESET_FUNC
+#define A78_AE_RESET_FUNC CPU_NO_RESET_FUNC
 #endif
 
-declare_cpu_ops cortex_hercules_ae, CORTEX_HERCULES_AE_MIDR, \
-	HERCULES_AE_RESET_FUNC, \
-	cortex_hercules_ae_core_pwr_dwn
+declare_cpu_ops cortex_a78_ae, CORTEX_A78_AE_MIDR, \
+	A78_AE_RESET_FUNC, \
+	cortex_a78_ae_core_pwr_dwn

plat/arm/board/arm_fpga/platform.mk

@@ -62,7 +62,7 @@ else
 				lib/cpus/aarch64/neoverse_n1.S		\
 				lib/cpus/aarch64/neoverse_e1.S		\
 				lib/cpus/aarch64/neoverse_zeus.S	\
-				lib/cpus/aarch64/cortex_hercules_ae.S	\
+				lib/cpus/aarch64/cortex_a78_ae.S	\
 				lib/cpus/aarch64/cortex_a65.S		\
 				lib/cpus/aarch64/cortex_a65ae.S		\
 				lib/cpus/aarch64/cortex_klein.S		\

plat/arm/board/fvp/platform.mk

@@ -121,7 +121,7 @@ else
 					lib/cpus/aarch64/neoverse_n1.S		\
 					lib/cpus/aarch64/neoverse_e1.S		\
 					lib/cpus/aarch64/neoverse_zeus.S	\
-					lib/cpus/aarch64/cortex_hercules_ae.S	\
+					lib/cpus/aarch64/cortex_a78_ae.S	\
 					lib/cpus/aarch64/cortex_klein.S	        \
 					lib/cpus/aarch64/cortex_matterhorn.S	\
 					lib/cpus/aarch64/cortex_a65.S		\