Add workaround for errata 764081 of Cortex-A75

Implicit Error Synchronization Barrier (IESB) might not be correctly
generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all
expection levels.

Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>

docs/cpu-specific-build-macros.rst

@@ -137,6 +137,11 @@ For Cortex-A73, the following errata build flags are defined :
 -  ``ERRATA_A73_855423``: This applies errata 855423 workaround to Cortex-A73
    CPU. This needs to be enabled only for revision <= r0p1 of the CPU.
 
+For Cortex-A75, the following errata build flags are defined :
+
+-  ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
+   CPU. This needs to be enabled only for revision r0p0 of the CPU.
+
 DSU Errata Workarounds
 ----------------------
 

include/arch/aarch64/arch.h

@@ -255,6 +255,7 @@
 #define SCTLR_NTWE_BIT		(ULL(1) << 18)
 #define SCTLR_WXN_BIT		(ULL(1) << 19)
 #define SCTLR_UWXN_BIT		(ULL(1) << 20)
+#define SCTLR_IESB_BIT		(ULL(1) << 21)
 #define SCTLR_E0E_BIT		(ULL(1) << 24)
 #define SCTLR_EE_BIT		(ULL(1) << 25)
 #define SCTLR_UCI_BIT		(ULL(1) << 26)

lib/cpus/aarch64/cortex_a75.S

 /*
- * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
  */
@@ -10,8 +10,46 @@
 #include <cpuamu.h>
 #include <cpu_macros.S>
 
+	/* --------------------------------------------------
+	 * Errata Workaround for Cortex A75 Errata #764081.
+	 * This applies only to revision r0p0 of Cortex A75.
+	 * Inputs:
+	 * x0: variant[4:7] and revision[0:3] of current cpu.
+	 * Shall clobber: x0-x17
+	 * --------------------------------------------------
+	 */
+func errata_a75_764081_wa
+	/*
+	 * Compare x0 against revision r0p0
+	 */
+	mov	x17, x30
+	bl	check_errata_764081
+	cbz	x0, 1f
+	mrs	x1, sctlr_el3
+	orr	x1, x1 ,#SCTLR_IESB_BIT
+	msr	sctlr_el3, x1
+	isb
+1:
+	ret	x17
+endfunc errata_a75_764081_wa
+
+func check_errata_764081
+	mov	x1, #0x00
+	b	cpu_rev_var_ls
+endfunc check_errata_764081
+
+	/* -------------------------------------------------
+	 * The CPU Ops reset function for Cortex-A75.
+	 * -------------------------------------------------
+	 */
 func cortex_a75_reset_func
 	mov	x19, x30
+	bl	cpu_get_rev_var
+
+#if ERRATA_A75_764081
+	bl	errata_a75_764081_wa
+#endif
+
 #if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
 	cpu_check_csv2	x0, 1f
 	adr	x0, wa_cve_2017_5715_bpiall_vbar
@@ -109,6 +147,7 @@ func cortex_a75_errata_report
 	 * Report all errata. The revision-variant information is passed to
 	 * checking functions of each errata.
 	 */
+	report_errata ERRATA_A75_764081, cortex_a75, 764081
 	report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715
 	report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639
 	report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184

lib/cpus/cpu-ops.mk

@@ -123,6 +123,10 @@ ERRATA_A72_859971	?=0
 # only to revision <= r0p1 of the Cortex A73 cpu.
 ERRATA_A73_855423	?=0
 
+# Flag to apply erratum 764081 workaround during reset. This erratum applies
+# only to revision <= r0p0 of the Cortex A75 cpu.
+ERRATA_A75_764081	?=0
+
 # Flag to apply T32 CLREX workaround during reset. This erratum applies
 # only to r0p0 and r1p0 of the Neoverse N1 cpu.
 ERRATA_N1_1043202	?=1
@@ -196,6 +200,10 @@ $(eval $(call add_define,ERRATA_A72_859971))
 $(eval $(call assert_boolean,ERRATA_A73_855423))
 $(eval $(call add_define,ERRATA_A73_855423))
 
+# Process ERRATA_A75_764081 flag
+$(eval $(call assert_boolean,ERRATA_A75_764081))
+$(eval $(call add_define,ERRATA_A75_764081))
+
 # Process ERRATA_N1_1043202 flag
 $(eval $(call assert_boolean,ERRATA_N1_1043202))
 $(eval $(call add_define,ERRATA_N1_1043202))

lib/el3_runtime/aarch64/context_mgmt.c

@@ -173,6 +173,14 @@ void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
 					| SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
 	}
 
+#if ERRATA_A75_764081
+	/*
+	 * If workaround of errata 764081 for Cortex-A75 is used then set
+	 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
+	 */
+	sctlr_elx |= SCTLR_IESB_BIT;
+#endif
+
 	/*
 	 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
 	 * and other EL2 registers are set up by cm_prepare_ns_entry() as they
@@ -305,6 +313,14 @@ void cm_prepare_el3_exit(uint32_t security_state)
 							   CTX_SCTLR_EL1);
 			sctlr_elx &= SCTLR_EE_BIT;
 			sctlr_elx |= SCTLR_EL2_RES1;
+#if ERRATA_A75_764081
+			/*
+			 * If workaround of errata 764081 for Cortex-A75 is used
+			 * then set SCTLR_EL2.IESB to enable Implicit Error
+			 * Synchronization Barrier.
+			 */
+			sctlr_elx |= SCTLR_IESB_BIT;
+#endif
 			write_sctlr_el2(sctlr_elx);
 		} else if (el_implemented(2) != EL_IMPL_NONE) {
 			el2_unused = true;