Commit 5f70d8de authored by Matt Ma's avatar Matt Ma
Browse files

Replace macro ASM_ASSERTION with macro ENABLE_ASSERTIONS



This patch replaces the macro ASM_ASSERTION with the macro
ENABLE_ASSERTIONS in ARM Cortex-A53/57/72 MPCore Processor
related files. There is build error when ASM_ASSERTION is set
to 1 and ENABLE_ASSERTIONS is set to 0 because function
asm_assert in common/aarch32/debug.S is defined in the macro
ENABLE_ASSERTIONS but is called with the macro ASM_ASSERTION.

There is also the indication to use ENABLE_ASSERTIONS but not
ASM_ASSERTION in the Makefile.
Signed-off-by: default avatarMatt Ma <matt.ma@spreadtrum.com>
parent 203444c5
...@@ -174,7 +174,7 @@ func cortex_a53_core_pwr_dwn ...@@ -174,7 +174,7 @@ func cortex_a53_core_pwr_dwn
push {r12, lr} push {r12, lr}
/* Assert if cache is enabled */ /* Assert if cache is enabled */
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
ldcopr r0, SCTLR ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq) ASM_ASSERT(eq)
...@@ -204,7 +204,7 @@ func cortex_a53_cluster_pwr_dwn ...@@ -204,7 +204,7 @@ func cortex_a53_cluster_pwr_dwn
push {r12, lr} push {r12, lr}
/* Assert if cache is enabled */ /* Assert if cache is enabled */
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
ldcopr r0, SCTLR ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq) ASM_ASSERT(eq)
......
...@@ -406,7 +406,7 @@ func cortex_a57_core_pwr_dwn ...@@ -406,7 +406,7 @@ func cortex_a57_core_pwr_dwn
push {r12, lr} push {r12, lr}
/* Assert if cache is enabled */ /* Assert if cache is enabled */
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
ldcopr r0, SCTLR ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq) ASM_ASSERT(eq)
...@@ -448,7 +448,7 @@ func cortex_a57_cluster_pwr_dwn ...@@ -448,7 +448,7 @@ func cortex_a57_cluster_pwr_dwn
push {r12, lr} push {r12, lr}
/* Assert if cache is enabled */ /* Assert if cache is enabled */
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
ldcopr r0, SCTLR ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq) ASM_ASSERT(eq)
......
...@@ -120,7 +120,7 @@ func cortex_a72_core_pwr_dwn ...@@ -120,7 +120,7 @@ func cortex_a72_core_pwr_dwn
push {r12, lr} push {r12, lr}
/* Assert if cache is enabled */ /* Assert if cache is enabled */
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
ldcopr r0, SCTLR ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq) ASM_ASSERT(eq)
...@@ -167,7 +167,7 @@ func cortex_a72_cluster_pwr_dwn ...@@ -167,7 +167,7 @@ func cortex_a72_cluster_pwr_dwn
push {r12, lr} push {r12, lr}
/* Assert if cache is enabled */ /* Assert if cache is enabled */
#if ASM_ASSERTION #if ENABLE_ASSERTIONS
ldcopr r0, SCTLR ldcopr r0, SCTLR
tst r0, #SCTLR_C_BIT tst r0, #SCTLR_C_BIT
ASM_ASSERT(eq) ASM_ASSERT(eq)
......
...@@ -24,9 +24,6 @@ ARM_ARCH_MINOR := 0 ...@@ -24,9 +24,6 @@ ARM_ARCH_MINOR := 0
# in EL3. The platform port can change this value if needed. # in EL3. The platform port can change this value if needed.
ARM_GIC_ARCH := 2 ARM_GIC_ARCH := 2
# Flag used to indicate if ASM_ASSERTION should be enabled for the build.
ASM_ASSERTION := 0
# Base commit to perform code check on # Base commit to perform code check on
BASE_COMMIT := origin/master BASE_COMMIT := origin/master
......
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