Merge changes I3c0a402f,I9ce5b9df,I08719015,If541278f,I99f1a697 into integration

* changes: doc: renesas: Update code owner for Renesas platforms doc: renesas: Document platforms based on RZ/G2 SoC's renesas: rzg: Add PFC support for RZ/G2M renesas: rzg: Add QoS support for RZ/G2M renesas: rzg: Add support for DRAM initialization

Merge changes I3c0a402f,I9ce5b9df,I08719015,If541278f,I99f1a697 into integration
* changes: doc: renesas: Update code owner for Renesas platforms doc: renesas: Document platforms based on RZ/G2 SoC's renesas: rzg: Add PFC support for RZ/G2M renesas: rzg: Add QoS support for RZ/G2M renesas: rzg: Add support for DRAM initialization
6047a105 · Madhukar Pappireddy · TrustedFirmware Code Review · dfa04b3d · d60642a4 · 6047a105
Commit 6047a105 authored Jan 15, 2021 by Madhukar Pappireddy Committed by TrustedFirmware Code Review Jan 15, 2021
--- a/docs/about/maintainers.rst
+++ b/docs/about/maintainers.rst
@@ -482,10 +482,25 @@ Renesas rcar-gen3 platform port
 :M: Marek Vasut <marek.vasut@gmail.com>
 :G: `marex`_
 :F: docs/plat/rcar-gen3.rst
+:F: plat/renesas/common
 :F: plat/renesas/rcar
+:F: drivers/renesas/common
 :F: drivers/renesas/rcar
 :F: tools/renesas/rcar_layout_create
+Renesas RZ/G2 platform port
+^^^^^^^^^^^^^^^^^^^^^^^^^^^
+:M: Biju Das <biju.das.jz@bp.renesas.com>
+:G: `bijucdas`_
+:M: Marek Vasut <marek.vasut@gmail.com>
+:G: `marex`_
+:F: docs/plat/rz-g2.rst
+:F: plat/renesas/common
+:F: plat/renesas/rzg
+:F: drivers/renesas/common
+:F: drivers/renesas/rzg
+:F: tools/renesas/rzg_layout_create
 RockChip platform port
 ^^^^^^^^^^^^^^^^^^^^^^
 :M: Tony Xie <tony.xie@rock-chips.com>
@@ -601,6 +616,7 @@ Build system
 .. _AlexeiFedorov: https://github.com/AlexeiFedorov
 .. _Andre-ARM: https://github.com/Andre-ARM
 .. _Anson-Huang: https://github.com/Anson-Huang
+.. _bijucdas: https://github.com/bijucdas
 .. _bryanodonoghue: https://github.com/bryanodonoghue
 .. _b49020: https://github.com/b49020
 .. _carlocaione: https://github.com/carlocaione

--- a/docs/plat/index.rst
+++ b/docs/plat/index.rst
@@ -32,6 +32,7 @@ Platform Ports
   rpi3
   rpi4
   rcar-gen3
+   rz-g2
   rockchip
   socionext-uniphier
   synquacer

--- a/docs/plat/rz-g2.rst
+++ b/docs/plat/rz-g2.rst
+Renesas RZ/G
+============
+The "RZ/G" Family of high-end 64-bit Arm®-based microprocessors (MPUs)
+enables the solutions required for the smart society of the future.
+Through a variety of Arm Cortex®-A53 and A57-based devices, engineers can
+easily implement high-resolution human machine interfaces (HMI), embedded
+vision, embedded artificial intelligence (e-AI) and real-time control and
+industrial ethernet connectivity.
+The scalable RZ/G hardware platform and flexible software platform
+cover the full product range, from the premium class to the entry
+level. Plug-ins are available for multiple open-source software tools.
+Renesas RZ/G2 reference platforms:
+----------------------------------
+--------------+----------------------------------------------------------------------------------+
+| Board        |      Details                                                                     |
+==============+===============+==================================================================+
+| hihope-rzg2h | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2H SoC       |
+|              +----------------------------------------------------------------------------------+
+|              | http://hihope.org/product/musashi                                                |
+--------------+----------------------------------------------------------------------------------+
+| hihope-rzg2m | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2M SoC       |
+|              +----------------------------------------------------------------------------------+
+|              | http://hihope.org/product/musashi                                                |
+--------------+----------------------------------------------------------------------------------+
+| hihope-rzg2n | "96 boards" compatible board from Hoperun equipped with Renesas RZ/G2N SoC       |
+|              +----------------------------------------------------------------------------------+
+|              | http://hihope.org/product/musashi                                                |
+--------------+----------------------------------------------------------------------------------+
+| ek874        | "96 boards" compatible board from Silicon Linux equipped with Renesas RZ/G2E SoC |
+|              +----------------------------------------------------------------------------------+
+|              | https://www.si-linux.co.jp/index.php?CAT%2FCAT874                                |
+--------------+----------------------------------------------------------------------------------+
+`boards info <https://www.renesas.com/us/en/products/rzg-linux-platform/rzg-marcketplace/board-solutions.html#rzg2>`__
+The current TF-A port has been tested on the HiHope RZ/G2M
+SoC_id r8a774a1 revision ES1.3.
+::
+    ARM CA57 (ARMv8) 1.5 GHz dual core, with NEON/VFPv4, L1$ I/D 48K/32K, L2$ 1MB
+    ARM CA53 (ARMv8) 1.2 GHz quad core, with NEON/VFPv4, L1$ I/D 32K/32K, L2$ 512K
+    Memory controller for LPDDR4-3200 4GB in 2 channels(32-bit bus mode)
+    Two- and three-dimensional graphics engines,
+    Video processing units,
+    Display Output,
+    Video Input,
+    SD card host interface,
+    USB3.0 and USB2.0 interfaces,
+    CAN interfaces,
+    Ethernet AVB,
+    Wi-Fi + BT,
+    PCI Express Interfaces,
+    Memories
+        INTERNAL 384KB SYSTEM RAM
+        DDR 4 GB LPDDR4
+        QSPI FLASH 64MB
+        EMMC 32 GB EMMC (HS400 240 MBYTES/S)
+        MICROSD-CARD SLOT (SDR104 100 MBYTES/S)
+Overview
+--------
+On RZ/G2 SoCs the BOOTROM starts the cpu at EL3; for this port BL2
+will therefore be entered at this exception level (the Renesas' ATF
+reference tree [1] resets into EL1 before entering BL2 - see its
+bl2.ld.S)
+BL2 initializes DDR before determining the boot reason (cold or warm).
+Once BL2 boots, it determines the boot reason, writes it to shared
+memory (BOOT_KIND_BASE) together with the BL31 parameters
+(PARAMS_BASE) and jumps to BL31.
+To all effects, BL31 is as if it is being entered in reset mode since
+it still needs to initialize the rest of the cores; this is the reason
+behind using direct shared memory access to  BOOT_KIND_BASE _and_
+PARAMS_BASE instead of using registers to get to those locations (see
+el3_common_macros.S and bl31_entrypoint.S for the RESET_TO_BL31 use
+case).
+[1] https://github.com/renesas-rz/meta-rzg2/tree/BSP-1.0.5/recipes-bsp/arm-trusted-firmware/files
+How to build
+------------
+The TF-A build options depend on the target board so you will have to
+refer to those specific instructions. What follows is customized to
+the HiHope RZ/G2M development kit used in this port.
+Build Tested:
+~~~~~~~~~~~~~
+.. code:: bash
+       make bl2 bl31 rzg LOG_LEVEL=40 PLAT=rzg LSI=G2M RCAR_DRAM_SPLIT=2\
+       RCAR_LOSSY_ENABLE=1 SPD="none" MBEDTLS_DIR=$mbedtls
+System Tested:
+~~~~~~~~~~~~~~
+* mbed_tls:
+  git@github.com:ARMmbed/mbedtls.git [devel]
+|  commit 72ca39737f974db44723760623d1b29980c00a88
+|  Merge: ef94c4fcf dd9ec1c57
+|  Author: Janos Follath <janos.follath@arm.com>
+|  Date:   Wed Oct 7 09:21:01 2020 +0100
+* u-boot:
+  The port has beent tested using mainline uboot with HiHope RZ/G2M board
+  specific patches.
+|  commit 46ce9e777c1314ccb78906992b94001194eaa87b
+|  Author: Heiko Schocher <hs@denx.de>
+|  Date:   Tue Nov 3 15:22:36 2020 +0100
+* linux:
+  The port has beent tested using mainline kernel.
+|  commit f8394f232b1eab649ce2df5c5f15b0e528c92091
+|  Author: Linus Torvalds <torvalds@linux-foundation.org>
+|  Date:   Sun Nov 8 16:10:16 2020 -0800
+|  Linux 5.10-rc3
+TF-A Build Procedure
+~~~~~~~~~~~~~~~~~~~~
+-  Fetch all the above 3 repositories.
+-  Prepare the AARCH64 toolchain.
+-  Build u-boot using hihope_rzg2_defconfig.
+   Result: u-boot-elf.srec
+.. code:: bash
+       make CROSS_COMPILE=aarch64-linux-gnu-
+	  hihope_rzg2_defconfig
+       make CROSS_COMPILE=aarch64-linux-gnu-
+-  Build TF-A
+   Result: bootparam_sa0.srec, cert_header_sa6.srec, bl2.srec, bl31.srec
+.. code:: bash
+       make bl2 bl31 rzg LOG_LEVEL=40 PLAT=rzg LSI=G2M RCAR_DRAM_SPLIT=2\
+       RCAR_LOSSY_ENABLE=1 SPD="none" MBEDTLS_DIR=$mbedtls
+Install Procedure
+~~~~~~~~~~~~~~~~~
+- Boot the board in Mini-monitor mode and enable access to the
+  QSPI flash.
+- Use the flash_writer utility[2] to flash all the SREC files.
+[2] https://github.com/renesas-rz/rzg2_flash_writer
+Boot trace
+----------
+::
+   INFO:    ARM GICv2 driver initialized
+   NOTICE:  BL2: RZ/G2 Initial Program Loader(CA57) Rev.2.0.6
+   NOTICE:  BL2: PRR is RZ/G2M Ver.1.3
+   NOTICE:  BL2: Board is HiHope RZ/G2M Rev.4.0
+   NOTICE:  BL2: Boot device is QSPI Flash(40MHz)
+   NOTICE:  BL2: LCM state is unknown
+   NOTICE:  BL2: DDR3200(rev.0.40)
+   NOTICE:  BL2: [COLD_BOOT]
+   NOTICE:  BL2: DRAM Split is 2ch
+   NOTICE:  BL2: QoS is default setting(rev.0.19)
+   NOTICE:  BL2: DRAM refresh interval 1.95 usec
+   NOTICE:  BL2: Periodic Write DQ Training
+   NOTICE:  BL2: CH0: 400000000 - 47fffffff, 2 GiB
+   NOTICE:  BL2: CH2: 600000000 - 67fffffff, 2 GiB
+   NOTICE:  BL2: Lossy Decomp areas
+   NOTICE:       Entry 0: DCMPAREACRAx:0x80000540 DCMPAREACRBx:0x570
+   NOTICE:       Entry 1: DCMPAREACRAx:0x40000000 DCMPAREACRBx:0x0
+   NOTICE:       Entry 2: DCMPAREACRAx:0x20000000 DCMPAREACRBx:0x0
+   NOTICE:  BL2: FDT at 0xe631db30
+   NOTICE:  BL2: v2.3(release):v2.4-rc0-2-g1433701e5
+   NOTICE:  BL2: Built : 13:45:26, Nov  7 2020
+   NOTICE:  BL2: Normal boot
+   INFO:    BL2: Doing platform setup
+   INFO:    BL2: Loading image id 3
+   NOTICE:  BL2: dst=0xe631d200 src=0x8180000 len=512(0x200)
+   NOTICE:  BL2: dst=0x43f00000 src=0x8180400 len=6144(0x1800)
+   WARNING: r-car ignoring the BL31 size from certificate,using RCAR_TRUSTED_SRAM_SIZE instead
+   INFO:    Loading image id=3 at address 0x44000000
+   NOTICE:  rcar_file_len: len: 0x0003e000
+   NOTICE:  BL2: dst=0x44000000 src=0x81c0000 len=253952(0x3e000)
+   INFO:    Image id=3 loaded: 0x44000000 - 0x4403e000
+   INFO:    BL2: Loading image id 5
+   INFO:    Loading image id=5 at address 0x50000000
+   NOTICE:  rcar_file_len: len: 0x00100000
+   NOTICE:  BL2: dst=0x50000000 src=0x8300000 len=1048576(0x100000)
+   INFO:    Image id=5 loaded: 0x50000000 - 0x50100000
+   NOTICE:  BL2: Booting BL31
+   INFO:    Entry point address = 0x44000000
+   INFO:    SPSR = 0x3cd
+   U-Boot 2021.01-rc1-00244-gac37e14fbd (Nov 04 2020 - 20:03:34 +0000)
+   CPU: Renesas Electronics R8A774A1 rev 1.3
+   Model: HopeRun HiHope RZ/G2M with sub board
+   DRAM:  3.9 GiB
+   MMC:   mmc@ee100000: 0, mmc@ee160000: 1
+   Loading Environment from MMC... OK
+   In:    serial@e6e88000
+   Out:   serial@e6e88000
+   Err:   serial@e6e88000
+   Net:   eth0: ethernet@e6800000
+   Hit any key to stop autoboot:  0
+   =>
--- a/drivers/renesas/rzg/ddr/boot_init_dram.h
+++ b/drivers/renesas/rzg/ddr/boot_init_dram.h
+/*
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef BOOT_INIT_DRAM_H
+#define BOOT_INIT_DRAM_H
+extern int32_t rzg_dram_init(void);
+#define INITDRAM_OK		0
+#define INITDRAM_NG		0xffffffff
+#define INITDRAM_ERR_I		0xffffffff
+#define INITDRAM_ERR_O		0xfffffffe
+#define INITDRAM_ERR_T		0xfffffff0
+#endif /* BOOT_INIT_DRAM_H */
--- a/drivers/renesas/rzg/ddr/ddr.mk
+++ b/drivers/renesas/rzg/ddr/ddr.mk
+#
+# Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+include drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
--- a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
+++ b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
--- a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c
+++ b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_config.c
+/*
+ * Copyright (c) 2021, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#define BOARDNUM 2
+#define BOARD_JUDGE_AUTO
+#ifdef BOARD_JUDGE_AUTO
+static uint32_t _board_judge(uint32_t prr_product);
+static uint32_t boardcnf_get_brd_type(uint32_t prr_product)
+{
+	return _board_judge(prr_product);
+}
+#else /* BOARD_JUDGE_AUTO */
+static uint32_t boardcnf_get_brd_type(void)
+{
+	return 1U;
+}
+#endif /* BOARD_JUDGE_AUTO */
+#define DDR_FAST_INIT
+struct _boardcnf_ch {
+	uint8_t ddr_density[CS_CNT];
+	uint64_t ca_swap;
+	uint16_t dqs_swap;
+	uint32_t dq_swap[SLICE_CNT];
+	uint8_t dm_swap[SLICE_CNT];
+	uint16_t wdqlvl_patt[16];
+	int8_t cacs_adj[16];
+	int8_t dm_adj_w[SLICE_CNT];
+	int8_t dq_adj_w[SLICE_CNT * 8U];
+	int8_t dm_adj_r[SLICE_CNT];
+	int8_t dq_adj_r[SLICE_CNT * 8U];
+};
+struct _boardcnf {
+	uint8_t phyvalid;
+	uint8_t dbi_en;
+	uint16_t cacs_dly;
+	int16_t cacs_dly_adj;
+	uint16_t dqdm_dly_w;
+	uint16_t dqdm_dly_r;
+	struct _boardcnf_ch ch[DRAM_CH_CNT];
+};
+#define WDQLVL_PAT {\
+	0x00AA,\
+	0x0055,\
+	0x00AA,\
+	0x0155,\
+	0x01CC,\
+	0x0133,\
+	0x00CC,\
+	0x0033,\
+	0x00F0,\
+	0x010F,\
+	0x01F0,\
+	0x010F,\
+	0x00F0,\
+	0x00F0,\
+	0x000F,\
+	0x010F}
+static const struct _boardcnf boardcnfs[BOARDNUM] = {
+	{
+/* boardcnf[0] HopeRun HiHope RZ/G2M 16Gbit/1rank/2ch board with G2M SoC */
+	 .phyvalid = 0x03,
+	 .dbi_en = 0x01,
+	 .cacs_dly = 0x02c0,
+	 .cacs_dly_adj = 0,
+	 .dqdm_dly_w = 0x0300,
+	 .dqdm_dly_r = 0x00a0,
+	 .ch = {
+		{
+		 {0x04, 0xff},
+		 0x00345201U,
+		 0x3201,
+		 {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
+		 {0x08, 0x08, 0x08, 0x08},
+		 WDQLVL_PAT,
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0},
+		 {0, 0, 0, 0},
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0},
+		 {0, 0, 0, 0},
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0}
+		},
+		{
+		 {0x04, 0xff},
+		 0x00302154U,
+		 0x2310,
+		 {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
+		 {0x08, 0x08, 0x08, 0x08},
+		 WDQLVL_PAT,
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0},
+		 {0, 0, 0, 0},
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0},
+		 {0, 0, 0, 0},
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0}
+		}
+		}
+	},
+/* boardcnf[1] HopeRun HiHope RZ/G2M 8Gbit/2rank/2ch board with G2M SoC */
+	{
+	 0x03,
+	 0x01,
+	 0x02c0,
+	 0,
+	 0x0300,
+	 0x00a0,
+	{
+		{
+		 {0x02, 0x02},
+		 0x00345201U,
+		 0x3201,
+		 {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
+		 {0x08, 0x08, 0x08, 0x08},
+		 WDQLVL_PAT,
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0},
+		 {0, 0, 0, 0},
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0},
+		 {0, 0, 0, 0},
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0}
+		},
+		{
+		 {0x02, 0x02},
+		 0x00302154U,
+		 0x2310,
+		 {0x01672543U, 0x45361207U, 0x45632107U, 0x60715234U},
+		 {0x08, 0x08, 0x08, 0x08},
+		 WDQLVL_PAT,
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0},
+		 {0, 0, 0, 0},
+		 {0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0,
+		  0, 0, 0, 0, 0, 0, 0, 0},
+		{0, 0, 0, 0},
+		{0, 0, 0, 0, 0, 0, 0, 0,
+		 0, 0, 0, 0, 0, 0, 0, 0,
+		 0, 0, 0, 0, 0, 0, 0, 0,
+		 0, 0, 0, 0, 0, 0, 0, 0}
+		}
+	}
+	}
+};
+void boardcnf_get_brd_clk(uint32_t brd, uint32_t *clk, uint32_t *div)
+{
+	uint32_t md;
+	md = (mmio_read_32(RST_MODEMR) >> 13) & 0x3U;
+	switch (md) {
+	case 0x0U:
+		*clk = 50U;
+		*div = 3U;
+		break;
+	case 0x1U:
+		*clk = 60U;
+		*div = 3U;
+		break;
+	case 0x2U:
+		*clk = 75U;
+		*div = 3U;
+		break;
+	case 0x3U:
+		*clk = 100U;
+		*div = 3U;
+		break;
+	default:
+		break;
+	}
+	(void)brd;
+}
+void boardcnf_get_ddr_mbps(uint32_t brd, uint32_t *mbps, uint32_t *div)
+{
+	uint32_t md;
+	md = (mmio_read_32(RST_MODEMR) >> 17U) & 0x5U;
+	md = (md | (md >> 1U)) & 0x3U;
+	switch (md) {
+	case 0x0U:
+		*mbps = 3200U;
+		*div = 1U;
+		break;
+	case 0x1U:
+		*mbps = 2800U;
+		*div = 1U;
+		break;
+	case 0x2U:
+		*mbps = 2400U;
+		*div = 1U;
+		break;
+	case 0x3U:
+		*mbps = 1600U;
+		*div = 1U;
+		break;
+	default:
+		break;
+	}
+	(void)brd;
+}
+#define _def_REFPERIOD  1890
+#define M3_SAMPLE_TT_A84        0xB866CC10U, 0x3B250421U
+#define M3_SAMPLE_TT_A85        0xB866CC10U, 0x3AA50421U
+#define M3_SAMPLE_TT_A86        0xB866CC10U, 0x3AA48421U
+#define M3_SAMPLE_FF_B45        0xB866CC10U, 0x3AB00C21U
+#define M3_SAMPLE_FF_B49        0xB866CC10U, 0x39B10C21U
+#define M3_SAMPLE_FF_B56        0xB866CC10U, 0x3AAF8C21U
+#define M3_SAMPLE_SS_E24        0xB866CC10U, 0x3BA39421U
+#define M3_SAMPLE_SS_E28        0xB866CC10U, 0x3C231421U
+#define M3_SAMPLE_SS_E32        0xB866CC10U, 0x3C241421U
+static const uint32_t termcode_by_sample[20][3] = {
+	{ M3_SAMPLE_TT_A84, 0x000158D5U },
+	{ M3_SAMPLE_TT_A85, 0x00015955U },
+	{ M3_SAMPLE_TT_A86, 0x00015955U },
+	{ M3_SAMPLE_FF_B45, 0x00015690U },
+	{ M3_SAMPLE_FF_B49, 0x00015753U },
+	{ M3_SAMPLE_FF_B56, 0x00015793U },
+	{ M3_SAMPLE_SS_E24, 0x00015996U },
+	{ M3_SAMPLE_SS_E28, 0x000159D7U },
+	{ M3_SAMPLE_SS_E32, 0x00015997U },
+	{ 0xFFFFFFFFU, 0xFFFFFFFFU, 0x0001554FU}
+};
+#ifdef BOARD_JUDGE_AUTO
+/* Board detect function */
+#define GPIO_INDT5	0xE605500CU
+#define LPDDR4_2RANK	(0x01U << 25U)
+static uint32_t _board_judge(uint32_t prr_product)
+{
+	uint32_t boardInfo;
+	uint32_t boardid = 1U;
+	if (prr_product == PRR_PRODUCT_M3) {
+		if ((mmio_read_32(PRR) & PRR_CUT_MASK) != RCAR_M3_CUT_VER11) {
+			boardInfo = mmio_read_32(GPIO_INDT5);
+			if ((boardInfo & LPDDR4_2RANK) == 0U) {
+				boardid = 0U;
+			}
+		}
+	}
+	return boardid;
+}
+#endif /* BOARD_JUDGE_AUTO */
--- a/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h
+++ b/drivers/renesas/rzg/ddr/ddr_b/boot_init_dram_regdef.h
+/*
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef RZG_BOOT_INIT_DRAM_REGDEF_H
+#define RZG_BOOT_INIT_DRAM_REGDEF_H
+#define RCAR_DDR_VERSION	"rev.0.40"
+#define DRAM_CH_CNT		0x04U
+#define SLICE_CNT		0x04U
+#define CS_CNT			0x02U
+/* order : CS0A, CS0B, CS1A, CS1B */
+#define CSAB_CNT		(CS_CNT * 2U)
+/* order : CH0A, CH0B, CH1A, CH1B, CH2A, CH2B, CH3A, CH3B */
+#define CHAB_CNT		(DRAM_CH_CNT * 2)
+/* pll setting */
+#define CLK_DIV(a, diva, b, divb) (((a) * (divb)) / ((b) * (diva)))
+#define CLK_MUL(a, diva, b, divb) (((a) * (b)) / ((diva) * (divb)))
+/* for ddr density setting */
+#define DBMEMCONF_REG(d3, row, bank, col, dw)	\
+	(((d3) << 30U) | ((row) << 24U) | ((bank) << 16U) | ((col) << 8U) | (dw))
+#define DBMEMCONF_REGD(density)		\
+	(DBMEMCONF_REG((density) % 2U, ((density) + 1U) / \
+	2U + (29U - 3U - 10U - 2U), 3U, 10U, 2U))
+#define DBMEMCONF_VAL(ch, cs) (DBMEMCONF_REGD(DBMEMCONF_DENS(ch, cs)))
+/* refresh mode */
+#define DBSC_REFINTS		(0x0U)
+/* system registers */
+#define CPG_FRQCRB		(CPG_BASE + 0x0004U)
+#define CPG_PLLECR		(CPG_BASE + 0x00D0U)
+#define CPG_MSTPSR5		(CPG_BASE + 0x003CU)
+#define CPG_SRCR4		(CPG_BASE + 0x00BCU)
+#define CPG_PLL3CR		(CPG_BASE + 0x00DCU)
+#define CPG_ZB3CKCR		(CPG_BASE + 0x0380U)
+#define CPG_FRQCRD		(CPG_BASE + 0x00E4U)
+#define CPG_SMSTPCR5		(CPG_BASE + 0x0144U)
+#define CPG_CPGWPR		(CPG_BASE + 0x0900U)
+#define CPG_SRSTCLR4		(CPG_BASE + 0x0950U)
+#define CPG_FRQCRB_KICK_BIT	BIT(31)
+#define CPG_PLLECR_PLL3E_BIT	BIT(3)
+#define CPG_PLLECR_PLL3ST_BIT	BIT(11)
+#define CPG_ZB3CKCR_ZB3ST_BIT	BIT(11)
+#define RST_BASE		(0xE6160000U)
+#define RST_MODEMR		(RST_BASE + 0x0060U)
+#define LIFEC_CHIPID(x)		(0xE6110040U + 0x04U * (x))
+/* DBSC registers */
+#include "ddr_regs.h"
+#define DBSC_DBMONCONF4		0xE6793010U
+#define DBSC_PLL_LOCK(ch)	(0xE6794054U + 0x100U * (ch))
+#define DBSC_PLL_LOCK_0		0xE6794054U
+#define DBSC_PLL_LOCK_1		0xE6794154U
+#define DBSC_PLL_LOCK_2		0xE6794254U
+#define DBSC_PLL_LOCK_3		0xE6794354U
+/* STAT registers */
+#define MSTAT_SL_INIT		0xE67E8000U
+#define MSTAT_REF_ARS		0xE67E8004U
+#define MSTATQ_STATQC		0xE67E8008U
+#define MSTATQ_WTENABLE		0xE67E8030U
+#define MSTATQ_WTREFRESH	0xE67E8034U
+#define MSTATQ_WTSETTING0	0xE67E8038U
+#define MSTATQ_WTSETTING1	0xE67E803CU
+#define QOS_BASE1		(0xE67F0000U)
+#define QOSCTRL_RAS		(QOS_BASE1 + 0x0000U)
+#define QOSCTRL_FIXTH		(QOS_BASE1 + 0x0004U)
+#define QOSCTRL_RAEN		(QOS_BASE1 + 0x0018U)
+#define QOSCTRL_REGGD		(QOS_BASE1 + 0x0020U)
+#define QOSCTRL_DANN		(QOS_BASE1 + 0x0030U)
+#define QOSCTRL_DANT		(QOS_BASE1 + 0x0038U)
+#define QOSCTRL_EC		(QOS_BASE1 + 0x003CU)
+#define QOSCTRL_EMS		(QOS_BASE1 + 0x0040U)
+#define QOSCTRL_INSFC		(QOS_BASE1 + 0x0050U)
+#define QOSCTRL_BERR		(QOS_BASE1 + 0x0054U)
+#define QOSCTRL_RACNT0		(QOS_BASE1 + 0x0080U)
+#define QOSCTRL_STATGEN0	(QOS_BASE1 + 0x0088U)
+/* other module */
+#define THS1_THCTR		0xE6198020U
+#define THS1_TEMP		0xE6198028U
+#endif /* RZG_BOOT_INIT_DRAM_REGDEF_H */
--- a/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
+++ b/drivers/renesas/rzg/ddr/ddr_b/ddr_b.mk
+#
+# Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+BL2_SOURCES += drivers/renesas/rzg/ddr/ddr_b/boot_init_dram.c
--- a/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h
+++ b/drivers/renesas/rzg/ddr/ddr_b/ddr_regdef.h
--- a/drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h
+++ b/drivers/renesas/rzg/ddr/ddr_b/init_dram_tbl_g2m.h
+/*
+ * Copyright (c) 2020U, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef RZG_INIT_DRAM_TABLE_G2M_H
+#define RZG_INIT_DRAM_TABLE_G2M_H
+#define DDR_PHY_SLICE_REGSET_OFS_G2M  0x0800U
+#define DDR_PHY_ADR_V_REGSET_OFS_G2M  0x0a00U
+#define DDR_PHY_ADR_I_REGSET_OFS_G2M  0x0a80U
+#define DDR_PHY_ADR_G_REGSET_OFS_G2M  0x0b80U
+#define DDR_PI_REGSET_OFS_G2M         0x0200U
+#define DDR_PHY_SLICE_REGSET_SIZE_G2M 0x80U
+#define DDR_PHY_ADR_V_REGSET_SIZE_G2M 0x80U
+#define DDR_PHY_ADR_I_REGSET_SIZE_G2M 0x80U
+#define DDR_PHY_ADR_G_REGSET_SIZE_G2M 0x80U
+#define DDR_PI_REGSET_SIZE_G2M        0x100U
+#define DDR_PHY_SLICE_REGSET_NUM_G2M  89
+#define DDR_PHY_ADR_V_REGSET_NUM_G2M  37
+#define DDR_PHY_ADR_I_REGSET_NUM_G2M  37
+#define DDR_PHY_ADR_G_REGSET_NUM_G2M  64
+#define DDR_PI_REGSET_NUM_G2M         202
+static const uint32_t DDR_PHY_SLICE_REGSET_G2M[DDR_PHY_SLICE_REGSET_NUM_G2M] = {
+	/*0800*/ 0x76543210U,
+	/*0801*/ 0x0004f008U,
+	/*0802*/ 0x00000000U,
+	/*0803*/ 0x00000000U,
+	/*0804*/ 0x00010000U,
+	/*0805*/ 0x036e6e0eU,
+	/*0806*/ 0x026e6e0eU,
+	/*0807*/ 0x00010300U,
+	/*0808*/ 0x04000100U,
+	/*0809*/ 0x00000300U,
+	/*080a*/ 0x001700c0U,
+	/*080b*/ 0x00b00201U,
+	/*080c*/ 0x00030020U,
+	/*080d*/ 0x00000000U,
+	/*080e*/ 0x00000000U,
+	/*080f*/ 0x00000000U,
+	/*0810*/ 0x00000000U,
+	/*0811*/ 0x00000000U,
+	/*0812*/ 0x00000000U,
+	/*0813*/ 0x00000000U,
+	/*0814*/ 0x09000000U,
+	/*0815*/ 0x04080000U,
+	/*0816*/ 0x04080400U,
+	/*0817*/ 0x00000000U,
+	/*0818*/ 0x32103210U,
+	/*0819*/ 0x00800708U,
+	/*081a*/ 0x000f000cU,
+	/*081b*/ 0x00000100U,
+	/*081c*/ 0x55aa55aaU,
+	/*081d*/ 0x33cc33ccU,
+	/*081e*/ 0x0ff00ff0U,
+	/*081f*/ 0x0f0ff0f0U,
+	/*0820*/ 0x00018e38U,
+	/*0821*/ 0x00000000U,
+	/*0822*/ 0x00000000U,
+	/*0823*/ 0x00000000U,
+	/*0824*/ 0x00000000U,
+	/*0825*/ 0x00000000U,
+	/*0826*/ 0x00000000U,
+	/*0827*/ 0x00000000U,
+	/*0828*/ 0x00000000U,
+	/*0829*/ 0x00000000U,
+	/*082a*/ 0x00000000U,
+	/*082b*/ 0x00000000U,
+	/*082c*/ 0x00000000U,
+	/*082d*/ 0x00000000U,
+	/*082e*/ 0x00000000U,
+	/*082f*/ 0x00000000U,
+	/*0830*/ 0x00000000U,
+	/*0831*/ 0x00000000U,
+	/*0832*/ 0x00000000U,
+	/*0833*/ 0x00200000U,
+	/*0834*/ 0x08200820U,
+	/*0835*/ 0x08200820U,
+	/*0836*/ 0x08200820U,
+	/*0837*/ 0x08200820U,
+	/*0838*/ 0x08200820U,
+	/*0839*/ 0x00000820U,
+	/*083a*/ 0x03000300U,
+	/*083b*/ 0x03000300U,
+	/*083c*/ 0x03000300U,
+	/*083d*/ 0x03000300U,
+	/*083e*/ 0x00000300U,
+	/*083f*/ 0x00000000U,
+	/*0840*/ 0x00000000U,
+	/*0841*/ 0x00000000U,
+	/*0842*/ 0x00000000U,
+	/*0843*/ 0x00a00000U,
+	/*0844*/ 0x00a000a0U,
+	/*0845*/ 0x00a000a0U,
+	/*0846*/ 0x00a000a0U,
+	/*0847*/ 0x00a000a0U,
+	/*0848*/ 0x00a000a0U,
+	/*0849*/ 0x00a000a0U,
+	/*084a*/ 0x00a000a0U,
+	/*084b*/ 0x00a000a0U,
+	/*084c*/ 0x010900a0U,
+	/*084d*/ 0x02000104U,
+	/*084e*/ 0x00000000U,
+	/*084f*/ 0x00010000U,
+	/*0850*/ 0x00000200U,
+	/*0851*/ 0x4041a151U,
+	/*0852*/ 0xc00141a0U,
+	/*0853*/ 0x0e0100c0U,
+	/*0854*/ 0x0010000cU,
+	/*0855*/ 0x0c064208U,
+	/*0856*/ 0x000f0c18U,
+	/*0857*/ 0x00e00140U,
+	/*0858*/ 0x00000c20U
+};
+static const uint32_t DDR_PHY_ADR_V_REGSET_G2M[DDR_PHY_ADR_V_REGSET_NUM_G2M] = {
+	/*0a00*/ 0x00000000U,
+	/*0a01*/ 0x00000000U,
+	/*0a02*/ 0x00000000U,
+	/*0a03*/ 0x00000000U,
+	/*0a04*/ 0x00000000U,
+	/*0a05*/ 0x00000000U,
+	/*0a06*/ 0x00000002U,
+	/*0a07*/ 0x00000000U,
+	/*0a08*/ 0x00000000U,
+	/*0a09*/ 0x00000000U,
+	/*0a0a*/ 0x00400320U,
+	/*0a0b*/ 0x00000040U,
+	/*0a0c*/ 0x00dcba98U,
+	/*0a0d*/ 0x00000000U,
+	/*0a0e*/ 0x00dcba98U,
+	/*0a0f*/ 0x01000000U,
+	/*0a10*/ 0x00020003U,
+	/*0a11*/ 0x00000000U,
+	/*0a12*/ 0x00000000U,
+	/*0a13*/ 0x00000000U,
+	/*0a14*/ 0x0000002aU,
+	/*0a15*/ 0x00000015U,
+	/*0a16*/ 0x00000015U,
+	/*0a17*/ 0x0000002aU,
+	/*0a18*/ 0x00000033U,
+	/*0a19*/ 0x0000000cU,
+	/*0a1a*/ 0x0000000cU,
+	/*0a1b*/ 0x00000033U,
+	/*0a1c*/ 0x0a418820U,
+	/*0a1d*/ 0x003f0000U,
+	/*0a1e*/ 0x0000003fU,
+	/*0a1f*/ 0x0002c06eU,
+	/*0a20*/ 0x02c002c0U,
+	/*0a21*/ 0x02c002c0U,
+	/*0a22*/ 0x000002c0U,
+	/*0a23*/ 0x42080010U,
+	/*0a24*/ 0x00000003U
+};
+static const uint32_t DDR_PHY_ADR_I_REGSET_G2M[DDR_PHY_ADR_I_REGSET_NUM_G2M] = {
+	/*0a80*/ 0x04040404U,
+	/*0a81*/ 0x00000404U,
+	/*0a82*/ 0x00000000U,
+	/*0a83*/ 0x00000000U,
+	/*0a84*/ 0x00000000U,
+	/*0a85*/ 0x00000000U,
+	/*0a86*/ 0x00000002U,
+	/*0a87*/ 0x00000000U,
+	/*0a88*/ 0x00000000U,
+	/*0a89*/ 0x00000000U,
+	/*0a8a*/ 0x00400320U,
+	/*0a8b*/ 0x00000040U,
+	/*0a8c*/ 0x00000000U,
+	/*0a8d*/ 0x00000000U,
+	/*0a8e*/ 0x00000000U,
+	/*0a8f*/ 0x01000000U,
+	/*0a90*/ 0x00020003U,
+	/*0a91*/ 0x00000000U,
+	/*0a92*/ 0x00000000U,
+	/*0a93*/ 0x00000000U,
+	/*0a94*/ 0x0000002aU,
+	/*0a95*/ 0x00000015U,
+	/*0a96*/ 0x00000015U,
+	/*0a97*/ 0x0000002aU,
+	/*0a98*/ 0x00000033U,
+	/*0a99*/ 0x0000000cU,
+	/*0a9a*/ 0x0000000cU,
+	/*0a9b*/ 0x00000033U,
+	/*0a9c*/ 0x00000000U,
+	/*0a9d*/ 0x00000000U,
+	/*0a9e*/ 0x00000000U,
+	/*0a9f*/ 0x0002c06eU,
+	/*0aa0*/ 0x02c002c0U,
+	/*0aa1*/ 0x02c002c0U,
+	/*0aa2*/ 0x000002c0U,
+	/*0aa3*/ 0x42080010U,
+	/*0aa4*/ 0x00000003U
+};
+static const uint32_t DDR_PHY_ADR_G_REGSET_G2M[DDR_PHY_ADR_G_REGSET_NUM_G2M] = {
+	/*0b80*/ 0x00000001U,
+	/*0b81*/ 0x00000000U,
+	/*0b82*/ 0x00000005U,
+	/*0b83*/ 0x04000f00U,
+	/*0b84*/ 0x00020080U,
+	/*0b85*/ 0x00020055U,
+	/*0b86*/ 0x00000000U,
+	/*0b87*/ 0x00000000U,
+	/*0b88*/ 0x00000000U,
+	/*0b89*/ 0x00000050U,
+	/*0b8a*/ 0x00000000U,
+	/*0b8b*/ 0x01010100U,
+	/*0b8c*/ 0x00000600U,
+	/*0b8d*/ 0x50640000U,
+	/*0b8e*/ 0x01421142U,
+	/*0b8f*/ 0x00000142U,
+	/*0b90*/ 0x00000000U,
+	/*0b91*/ 0x000f1600U,
+	/*0b92*/ 0x0f160f16U,
+	/*0b93*/ 0x0f160f16U,
+	/*0b94*/ 0x00000003U,
+	/*0b95*/ 0x0002c000U,
+	/*0b96*/ 0x02c002c0U,
+	/*0b97*/ 0x000002c0U,
+	/*0b98*/ 0x03421342U,
+	/*0b99*/ 0x00000342U,
+	/*0b9a*/ 0x00000000U,
+	/*0b9b*/ 0x00000000U,
+	/*0b9c*/ 0x05020000U,
+	/*0b9d*/ 0x00000000U,
+	/*0b9e*/ 0x00027f6eU,
+	/*0b9f*/ 0x047f027fU,
+	/*0ba0*/ 0x00027f6eU,
+	/*0ba1*/ 0x00047f6eU,
+	/*0ba2*/ 0x0003554fU,
+	/*0ba3*/ 0x0001554fU,
+	/*0ba4*/ 0x0001554fU,
+	/*0ba5*/ 0x0001554fU,
+	/*0ba6*/ 0x0001554fU,
+	/*0ba7*/ 0x00003feeU,
+	/*0ba8*/ 0x0001554fU,
+	/*0ba9*/ 0x00003feeU,
+	/*0baa*/ 0x0001554fU,
+	/*0bab*/ 0x00027f6eU,
+	/*0bac*/ 0x0001554fU,
+	/*0bad*/ 0x00000000U,
+	/*0bae*/ 0x00000000U,
+	/*0baf*/ 0x00000000U,
+	/*0bb0*/ 0x65000000U,
+	/*0bb1*/ 0x00000000U,
+	/*0bb2*/ 0x00000000U,
+	/*0bb3*/ 0x00000201U,
+	/*0bb4*/ 0x00000000U,
+	/*0bb5*/ 0x00000000U,
+	/*0bb6*/ 0x00000000U,
+	/*0bb7*/ 0x00000000U,
+	/*0bb8*/ 0x00000000U,
+	/*0bb9*/ 0x00000000U,
+	/*0bba*/ 0x00000000U,
+	/*0bbb*/ 0x00000000U,
+	/*0bbc*/ 0x06e40000U,
+	/*0bbd*/ 0x00000000U,
+	/*0bbe*/ 0x00000000U,
+	/*0bbf*/ 0x00010000U
+};
+static const uint32_t DDR_PI_REGSET_G2M[DDR_PI_REGSET_NUM_G2M] = {
+	/*0200*/ 0x00000b00U,
+	/*0201*/ 0x00000100U,
+	/*0202*/ 0x00000000U,
+	/*0203*/ 0x0000ffffU,
+	/*0204*/ 0x00000000U,
+	/*0205*/ 0x0000ffffU,
+	/*0206*/ 0x00000000U,
+	/*0207*/ 0x304cffffU,
+	/*0208*/ 0x00000200U,
+	/*0209*/ 0x00000200U,
+	/*020a*/ 0x00000200U,
+	/*020b*/ 0x00000200U,
+	/*020c*/ 0x0000304cU,
+	/*020d*/ 0x00000200U,
+	/*020e*/ 0x00000200U,
+	/*020f*/ 0x00000200U,
+	/*0210*/ 0x00000200U,
+	/*0211*/ 0x0000304cU,
+	/*0212*/ 0x00000200U,
+	/*0213*/ 0x00000200U,
+	/*0214*/ 0x00000200U,
+	/*0215*/ 0x00000200U,
+	/*0216*/ 0x00010000U,
+	/*0217*/ 0x00000003U,
+	/*0218*/ 0x01000001U,
+	/*0219*/ 0x00000000U,
+	/*021a*/ 0x00000000U,
+	/*021b*/ 0x00000000U,
+	/*021c*/ 0x00000000U,
+	/*021d*/ 0x00000000U,
+	/*021e*/ 0x00000000U,
+	/*021f*/ 0x00000000U,
+	/*0220*/ 0x00000000U,
+	/*0221*/ 0x00000000U,
+	/*0222*/ 0x00000000U,
+	/*0223*/ 0x00000000U,
+	/*0224*/ 0x00000000U,
+	/*0225*/ 0x00000000U,
+	/*0226*/ 0x00000000U,
+	/*0227*/ 0x00000000U,
+	/*0228*/ 0x00000000U,
+	/*0229*/ 0x0f000101U,
+	/*022a*/ 0x08492d25U,
+	/*022b*/ 0x0e0c0004U,
+	/*022c*/ 0x000e5000U,
+	/*022d*/ 0x00000250U,
+	/*022e*/ 0x00460003U,
+	/*022f*/ 0x182600cfU,
+	/*0230*/ 0x182600cfU,
+	/*0231*/ 0x00000005U,
+	/*0232*/ 0x00000000U,
+	/*0233*/ 0x00000000U,
+	/*0234*/ 0x00000000U,
+	/*0235*/ 0x00000000U,
+	/*0236*/ 0x00000000U,
+	/*0237*/ 0x00000000U,
+	/*0238*/ 0x00000000U,
+	/*0239*/ 0x01000000U,
+	/*023a*/ 0x00040404U,
+	/*023b*/ 0x01280a00U,
+	/*023c*/ 0x00000000U,
+	/*023d*/ 0x000f0000U,
+	/*023e*/ 0x00001803U,
+	/*023f*/ 0x00000000U,
+	/*0240*/ 0x00000000U,
+	/*0241*/ 0x00060002U,
+	/*0242*/ 0x00010001U,
+	/*0243*/ 0x01000101U,
+	/*0244*/ 0x04020201U,
+	/*0245*/ 0x00080804U,
+	/*0246*/ 0x00000000U,
+	/*0247*/ 0x08030000U,
+	/*0248*/ 0x15150408U,
+	/*0249*/ 0x00000000U,
+	/*024a*/ 0x00000000U,
+	/*024b*/ 0x00000000U,
+	/*024c*/ 0x000f0f00U,
+	/*024d*/ 0x0000001eU,
+	/*024e*/ 0x00000000U,
+	/*024f*/ 0x01000300U,
+	/*0250*/ 0x00000000U,
+	/*0251*/ 0x00000000U,
+	/*0252*/ 0x01000000U,
+	/*0253*/ 0x00010101U,
+	/*0254*/ 0x000e0e0eU,
+	/*0255*/ 0x000c0c0cU,
+	/*0256*/ 0x02060601U,
+	/*0257*/ 0x00000000U,
+	/*0258*/ 0x00000003U,
+	/*0259*/ 0x00181703U,
+	/*025a*/ 0x00280006U,
+	/*025b*/ 0x00280016U,
+	/*025c*/ 0x00000016U,
+	/*025d*/ 0x00000000U,
+	/*025e*/ 0x00000000U,
+	/*025f*/ 0x00000000U,
+	/*0260*/ 0x140a0000U,
+	/*0261*/ 0x0005010aU,
+	/*0262*/ 0x03018d03U,
+	/*0263*/ 0x000a018dU,
+	/*0264*/ 0x00060100U,
+	/*0265*/ 0x01000006U,
+	/*0266*/ 0x018e018eU,
+	/*0267*/ 0x018e0100U,
+	/*0268*/ 0x1111018eU,
+	/*0269*/ 0x10010204U,
+	/*026a*/ 0x09090650U,
+	/*026b*/ 0x20110202U,
+	/*026c*/ 0x00201000U,
+	/*026d*/ 0x00201000U,
+	/*026e*/ 0x04041000U,
+	/*026f*/ 0x18020100U,
+	/*0270*/ 0x00010118U,
+	/*0271*/ 0x004b004aU,
+	/*0272*/ 0x050f0000U,
+	/*0273*/ 0x0c01021eU,
+	/*0274*/ 0x34000000U,
+	/*0275*/ 0x00000000U,
+	/*0276*/ 0x00000000U,
+	/*0277*/ 0x00000000U,
+	/*0278*/ 0x0000d400U,
+	/*0279*/ 0x0031002eU,
+	/*027a*/ 0x00111136U,
+	/*027b*/ 0x002e00d4U,
+	/*027c*/ 0x11360031U,
+	/*027d*/ 0x0000d411U,
+	/*027e*/ 0x0031002eU,
+	/*027f*/ 0x00111136U,
+	/*0280*/ 0x002e00d4U,
+	/*0281*/ 0x11360031U,
+	/*0282*/ 0x0000d411U,
+	/*0283*/ 0x0031002eU,
+	/*0284*/ 0x00111136U,
+	/*0285*/ 0x002e00d4U,
+	/*0286*/ 0x11360031U,
+	/*0287*/ 0x00d40011U,
+	/*0288*/ 0x0031002eU,
+	/*0289*/ 0x00111136U,
+	/*028a*/ 0x002e00d4U,
+	/*028b*/ 0x11360031U,
+	/*028c*/ 0x0000d411U,
+	/*028d*/ 0x0031002eU,
+	/*028e*/ 0x00111136U,
+	/*028f*/ 0x002e00d4U,
+	/*0290*/ 0x11360031U,
+	/*0291*/ 0x0000d411U,
+	/*0292*/ 0x0031002eU,
+	/*0293*/ 0x00111136U,
+	/*0294*/ 0x002e00d4U,
+	/*0295*/ 0x11360031U,
+	/*0296*/ 0x02000011U,
+	/*0297*/ 0x018d018dU,
+	/*0298*/ 0x0c08018dU,
+	/*0299*/ 0x1f121d22U,
+	/*029a*/ 0x4301b344U,
+	/*029b*/ 0x10172006U,
+	/*029c*/ 0x1d220c10U,
+	/*029d*/ 0x00001f12U,
+	/*029e*/ 0x4301b344U,
+	/*029f*/ 0x10172006U,
+	/*02a0*/ 0x1d220c10U,
+	/*02a1*/ 0x00001f12U,
+	/*02a2*/ 0x4301b344U,
+	/*02a3*/ 0x10172006U,
+	/*02a4*/ 0x02000210U,
+	/*02a5*/ 0x02000200U,
+	/*02a6*/ 0x02000200U,
+	/*02a7*/ 0x02000200U,
+	/*02a8*/ 0x02000200U,
+	/*02a9*/ 0x00000000U,
+	/*02aa*/ 0x00000000U,
+	/*02ab*/ 0x00000000U,
+	/*02ac*/ 0x00000000U,
+	/*02ad*/ 0x00000000U,
+	/*02ae*/ 0x00000000U,
+	/*02af*/ 0x00000000U,
+	/*02b0*/ 0x00000000U,
+	/*02b1*/ 0x00000000U,
+	/*02b2*/ 0x00000000U,
+	/*02b3*/ 0x00000000U,
+	/*02b4*/ 0x00000000U,
+	/*02b5*/ 0x00000400U,
+	/*02b6*/ 0x15141312U,
+	/*02b7*/ 0x11100f0eU,
+	/*02b8*/ 0x080b0c0dU,
+	/*02b9*/ 0x05040a09U,
+	/*02ba*/ 0x01000706U,
+	/*02bb*/ 0x00000302U,
+	/*02bc*/ 0x01030201U,
+	/*02bd*/ 0x00304c00U,
+	/*02be*/ 0x0001e2f8U,
+	/*02bf*/ 0x0000304cU,
+	/*02c0*/ 0x0001e2f8U,
+	/*02c1*/ 0x0000304cU,
+	/*02c2*/ 0x0001e2f8U,
+	/*02c3*/ 0x08000000U,
+	/*02c4*/ 0x00000100U,
+	/*02c5*/ 0x00000000U,
+	/*02c6*/ 0x00000000U,
+	/*02c7*/ 0x00000000U,
+	/*02c8*/ 0x00000000U,
+	/*02c9*/ 0x00000002U
+};
+#endif /* RZG_INIT_DRAM_TABLE_G2M_H */
--- a/drivers/renesas/rzg/ddr/dram_sub_func.h
+++ b/drivers/renesas/rzg/ddr/dram_sub_func.h
+/*
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef DRAM_SUB_FUNC_H
+#define DRAM_SUB_FUNC_H
+#define DRAM_UPDATE_STATUS_ERR	-1
+#define DRAM_BOOT_STATUS_COLD	0
+#define DRAM_BOOT_STATUS_WARM	1
+#endif /* DRAM_SUB_FUNC_H */
--- a/drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
+++ b/drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
--- a/drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.h
+++ b/drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.h
+/*
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef PFC_INIT_G2M_H
+#define PFC_INIT_G2M_H
+void pfc_init_g2m(void);
+#endif /* PFC_INIT_G2M_H */
--- a/drivers/renesas/rzg/pfc/pfc.mk
+++ b/drivers/renesas/rzg/pfc/pfc.mk
+#
+# Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+ifeq (${RCAR_LSI},${RCAR_AUTO})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
+else ifdef RCAR_LSI_CUT_COMPAT
+  ifeq (${RCAR_LSI},${RZ_G2M})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
+  endif
+else
+  ifeq (${RCAR_LSI},${RZ_G2M})
+    BL2_SOURCES += drivers/renesas/rzg/pfc/G2M/pfc_init_g2m.c
+  endif
+endif
+BL2_SOURCES += drivers/renesas/rzg/pfc/pfc_init.c
--- a/drivers/renesas/rzg/pfc/pfc_init.c
+++ b/drivers/renesas/rzg/pfc/pfc_init.c
+/*
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#include <stdint.h>
+#include <common/debug.h>
+#include <lib/mmio.h>
+#if RCAR_LSI == RCAR_AUTO
+#include "G2M/pfc_init_g2m.h"
+#endif /* RCAR_LSI == RCAR_AUTO */
+#if (RCAR_LSI == RZ_G2M)
+#include "G2M/pfc_init_g2m.h"
+#endif /* RCAR_LSI == RZ_G2M */
+#include "rcar_def.h"
+#define PRR_PRODUCT_ERR(reg)				\
+	do {						\
+		ERROR("LSI Product ID(PRR=0x%x) PFC init not supported.\n", \
+			reg);				\
+		panic();				\
+	} while (0)
+#define PRR_CUT_ERR(reg)				\
+	do {						\
+		ERROR("LSI Cut ID(PRR=0x%x) PFC init not supported.\n", \
+			reg);				\
+		panic();\
+	} while (0)
+void rzg_pfc_init(void)
+{
+	uint32_t reg;
+	reg = mmio_read_32(RCAR_PRR);
+#if RCAR_LSI == RCAR_AUTO
+	switch (reg & PRR_PRODUCT_MASK) {
+	case PRR_PRODUCT_M3:
+		pfc_init_g2m();
+		break;
+	default:
+		PRR_PRODUCT_ERR(reg);
+		break;
+	}
+#elif RCAR_LSI_CUT_COMPAT /* RCAR_LSI == RCAR_AUTO */
+	switch (reg & PRR_PRODUCT_MASK) {
+	case PRR_PRODUCT_M3:
+#if RCAR_LSI != RZ_G2M
+		PRR_PRODUCT_ERR(reg);
+#else /* RCAR_LSI != RZ_G2M */
+		pfc_init_g2m();
+#endif /* RCAR_LSI != RZ_G2M */
+		break;
+	default:
+		PRR_PRODUCT_ERR(reg);
+		break;
+	}
+#else /* RCAR_LSI == RCAR_AUTO */
+#if (RCAR_LSI == RZ_G2M)
+	if ((reg & PRR_PRODUCT_MASK) != PRR_PRODUCT_M3) {
+		PRR_PRODUCT_ERR(reg);
+	}
+	pfc_init_m3();
+#else /* RCAR_LSI == RZ_G2M */
+#error "Don't have PFC initialize routine(unknown)."
+#endif /* RCAR_LSI == RZ_G2M */
+#endif /* RCAR_LSI == RCAR_AUTO */
+}
--- a/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.c
+++ b/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.c
--- a/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.h
+++ b/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10.h
+/*
+ * Copyright (c) 2020, Renesas Electronics Corporation. All rights reserved.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef QOS_INIT_G2M_V10_H
+#define QOS_INIT_G2M_V10_H
+void qos_init_g2m_v10(void);
+#endif /* QOS_INIT_G2M_V10_H */
--- a/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10_mstat.h
+++ b/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v10_mstat.h
--- a/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11.c
+++ b/drivers/renesas/rzg/qos/G2M/qos_init_g2m_v11.c